2019-01-22 02:05:50 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2015-10-07 03:25:49 +08:00
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*/
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/* Broadcom Cygnus SoC internal transceivers support. */
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#include "bcm-phy-lib.h"
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#include <linux/brcmphy.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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2019-03-21 03:53:13 +08:00
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struct bcm_omega_phy_priv {
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u64 *stats;
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};
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2015-10-07 03:25:49 +08:00
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/* Broadcom Cygnus Phy specific registers */
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#define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
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static int bcm_cygnus_afe_config(struct phy_device *phydev)
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{
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int rc;
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/* ensure smdspclk is enabled */
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rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30);
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if (rc < 0)
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return rc;
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/* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
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rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
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if (rc < 0)
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return rc;
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/* AFE_HPF_TRIM_OTHERS bit11=1, short cascode enable for all modes*/
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
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if (rc < 0)
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return rc;
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/* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
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if (rc < 0)
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return rc;
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/* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
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rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
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if (rc < 0)
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return rc;
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/* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
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rc = bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
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if (rc < 0)
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return rc;
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/* Adjust bias current trim to overcome digital offSet */
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rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02);
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if (rc < 0)
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return rc;
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/* make rcal=100, since rdb default is 000 */
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2018-05-23 08:04:49 +08:00
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rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB1, 0x10);
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2015-10-07 03:25:49 +08:00
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if (rc < 0)
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return rc;
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/* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
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2018-05-23 08:04:49 +08:00
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rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x10);
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2015-10-07 03:25:49 +08:00
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if (rc < 0)
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return rc;
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/* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
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2018-05-23 08:04:49 +08:00
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rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x00);
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2015-10-07 03:25:49 +08:00
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return 0;
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}
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static int bcm_cygnus_config_init(struct phy_device *phydev)
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{
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int reg, rc;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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/* Mask interrupts globally. */
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reg |= MII_BCM54XX_ECR_IM;
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rc = phy_write(phydev, MII_BCM54XX_ECR, reg);
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if (rc)
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return rc;
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/* Unmask events of interest */
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reg = ~(MII_BCM54XX_INT_DUPLEX |
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MII_BCM54XX_INT_SPEED |
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MII_BCM54XX_INT_LINK);
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rc = phy_write(phydev, MII_BCM54XX_IMR, reg);
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if (rc)
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return rc;
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/* Apply AFE settings for the PHY */
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rc = bcm_cygnus_afe_config(phydev);
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if (rc)
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return rc;
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/* Advertise EEE */
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2016-11-23 03:40:56 +08:00
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rc = bcm_phy_set_eee(phydev, true);
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2015-10-07 03:25:49 +08:00
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if (rc)
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return rc;
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/* Enable APD */
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return bcm_phy_enable_apd(phydev, false);
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}
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static int bcm_cygnus_resume(struct phy_device *phydev)
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{
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int rc;
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genphy_resume(phydev);
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/* Re-initialize the PHY to apply AFE work-arounds and
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* configurations when coming out of suspend.
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*/
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rc = bcm_cygnus_config_init(phydev);
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if (rc)
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return rc;
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/* restart auto negotiation with the new settings */
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return genphy_config_aneg(phydev);
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}
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2019-03-21 03:53:13 +08:00
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static int bcm_omega_config_init(struct phy_device *phydev)
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{
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u8 count, rev;
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int ret = 0;
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rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
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pr_info_once("%s: %s PHY revision: 0x%02x\n",
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phydev_name(phydev), phydev->drv->name, rev);
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/* Dummy read to a register to workaround an issue upon reset where the
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* internal inverter may not allow the first MDIO transaction to pass
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* the MDIO management controller and make us return 0xffff for such
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* reads.
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*/
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phy_read(phydev, MII_BMSR);
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switch (rev) {
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case 0x00:
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ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
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break;
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default:
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break;
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}
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if (ret)
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return ret;
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ret = bcm_phy_downshift_get(phydev, &count);
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if (ret)
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return ret;
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/* Only enable EEE if Wirespeed/downshift is disabled */
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ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
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if (ret)
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return ret;
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return bcm_phy_enable_apd(phydev, true);
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}
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static int bcm_omega_resume(struct phy_device *phydev)
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{
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int ret;
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/* Re-apply workarounds coming out suspend/resume */
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ret = bcm_omega_config_init(phydev);
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if (ret)
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return ret;
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/* 28nm Gigabit PHYs come out of reset without any half-duplex
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* or "hub" compliant advertised mode, fix that. This does not
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* cause any problems with the PHY library since genphy_config_aneg()
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* gracefully handles auto-negotiated and forced modes.
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*/
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return genphy_config_aneg(phydev);
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}
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static int bcm_omega_get_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return bcm_phy_downshift_get(phydev, (u8 *)data);
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default:
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return -EOPNOTSUPP;
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}
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}
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static int bcm_omega_set_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna,
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const void *data)
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{
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u8 count = *(u8 *)data;
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int ret;
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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ret = bcm_phy_downshift_set(phydev, count);
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break;
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default:
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return -EOPNOTSUPP;
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}
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if (ret)
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return ret;
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/* Disable EEE advertisement since this prevents the PHY
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* from successfully linking up, trigger auto-negotiation restart
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* to let the MAC decide what to do.
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*/
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ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
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if (ret)
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return ret;
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return genphy_restart_aneg(phydev);
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}
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static void bcm_omega_get_phy_stats(struct phy_device *phydev,
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struct ethtool_stats *stats, u64 *data)
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{
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struct bcm_omega_phy_priv *priv = phydev->priv;
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bcm_phy_get_stats(phydev, priv->stats, stats, data);
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}
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static int bcm_omega_probe(struct phy_device *phydev)
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{
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struct bcm_omega_phy_priv *priv;
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priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phydev->priv = priv;
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priv->stats = devm_kcalloc(&phydev->mdio.dev,
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bcm_phy_get_sset_count(phydev), sizeof(u64),
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GFP_KERNEL);
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if (!priv->stats)
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return -ENOMEM;
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return 0;
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}
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2015-10-07 03:25:49 +08:00
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static struct phy_driver bcm_cygnus_phy_driver[] = {
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{
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.phy_id = PHY_ID_BCM_CYGNUS,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom Cygnus PHY",
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2019-04-13 02:47:03 +08:00
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/* PHY_GBIT_FEATURES */
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2015-10-07 03:25:49 +08:00
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.config_init = bcm_cygnus_config_init,
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.config_intr = bcm_phy_config_intr,
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2020-11-01 20:51:06 +08:00
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.handle_interrupt = bcm_phy_handle_interrupt,
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2015-10-07 03:25:49 +08:00
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.suspend = genphy_suspend,
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.resume = bcm_cygnus_resume,
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2019-03-21 03:53:13 +08:00
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}, {
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.phy_id = PHY_ID_BCM_OMEGA,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom Omega Combo GPHY",
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2019-04-13 02:47:03 +08:00
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/* PHY_GBIT_FEATURES */
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2019-03-21 03:53:13 +08:00
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.flags = PHY_IS_INTERNAL,
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.config_init = bcm_omega_config_init,
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.suspend = genphy_suspend,
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.resume = bcm_omega_resume,
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.get_tunable = bcm_omega_get_tunable,
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.set_tunable = bcm_omega_set_tunable,
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.get_sset_count = bcm_phy_get_sset_count,
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.get_strings = bcm_phy_get_strings,
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.get_stats = bcm_omega_get_phy_stats,
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.probe = bcm_omega_probe,
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}
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};
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2015-10-07 03:25:49 +08:00
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static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {
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{ PHY_ID_BCM_CYGNUS, 0xfffffff0, },
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2019-03-21 03:53:13 +08:00
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{ PHY_ID_BCM_OMEGA, 0xfffffff0, },
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2015-10-07 03:25:49 +08:00
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, bcm_cygnus_phy_tbl);
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module_phy_driver(bcm_cygnus_phy_driver);
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MODULE_DESCRIPTION("Broadcom Cygnus internal PHY driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Broadcom Corporation");
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