2020-03-06 12:28:26 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
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2021-02-12 22:34:00 +08:00
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* Copyright (C) 2019-2021 Linaro Ltd.
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2020-03-06 12:28:26 +08:00
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*/
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/bitfield.h>
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#include <linux/dma-direction.h>
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#include "gsi.h"
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#include "gsi_trans.h"
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#include "ipa.h"
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#include "ipa_endpoint.h"
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#include "ipa_table.h"
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#include "ipa_cmd.h"
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#include "ipa_mem.h"
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/**
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* DOC: IPA Immediate Commands
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*
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* The AP command TX endpoint is used to issue immediate commands to the IPA.
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* An immediate command is generally used to request the IPA do something
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* other than data transfer to another endpoint.
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*
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* Immediate commands are represented by GSI transactions just like other
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* transfer requests, represented by a single GSI TRE. Each immediate
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* command has a well-defined format, having a payload of a known length.
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* This allows the transfer element's length field to be used to hold an
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* immediate command's opcode. The payload for a command resides in DRAM
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* and is described by a single scatterlist entry in its transaction.
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* Commands do not require a transaction completion callback. To commit
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* an immediate command transaction, either gsi_trans_commit_wait() or
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* gsi_trans_commit_wait_timeout() is used.
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*/
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/* Some commands can wait until indicated pipeline stages are clear */
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enum pipeline_clear_options {
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2020-11-17 07:38:01 +08:00
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pipeline_clear_hps = 0x0,
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pipeline_clear_src_grp = 0x1,
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pipeline_clear_full = 0x2,
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2020-03-06 12:28:26 +08:00
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};
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/* IPA_CMD_IP_V{4,6}_{FILTER,ROUTING}_INIT */
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struct ipa_cmd_hw_ip_fltrt_init {
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__le64 hash_rules_addr;
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__le64 flags;
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__le64 nhash_rules_addr;
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};
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/* Field masks for ipa_cmd_hw_ip_fltrt_init structure fields */
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#define IP_FLTRT_FLAGS_HASH_SIZE_FMASK GENMASK_ULL(11, 0)
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#define IP_FLTRT_FLAGS_HASH_ADDR_FMASK GENMASK_ULL(27, 12)
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#define IP_FLTRT_FLAGS_NHASH_SIZE_FMASK GENMASK_ULL(39, 28)
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#define IP_FLTRT_FLAGS_NHASH_ADDR_FMASK GENMASK_ULL(55, 40)
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/* IPA_CMD_HDR_INIT_LOCAL */
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struct ipa_cmd_hw_hdr_init_local {
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__le64 hdr_table_addr;
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__le32 flags;
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__le32 reserved;
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};
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/* Field masks for ipa_cmd_hw_hdr_init_local structure fields */
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#define HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK GENMASK(11, 0)
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#define HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK GENMASK(27, 12)
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/* IPA_CMD_REGISTER_WRITE */
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2021-03-24 21:15:23 +08:00
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/* For IPA v4.0+, the pipeline clear options are encoded in the opcode */
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2020-03-06 12:28:26 +08:00
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#define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)
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#define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)
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struct ipa_cmd_register_write {
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2021-03-24 21:15:23 +08:00
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__le16 flags; /* Unused/reserved prior to IPA v4.0 */
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2020-03-06 12:28:26 +08:00
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__le16 offset;
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__le32 value;
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__le32 value_mask;
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__le32 clear_options; /* Unused/reserved for IPA v4.0+ */
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};
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/* Field masks for ipa_cmd_register_write structure fields */
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2021-03-24 21:15:23 +08:00
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/* The next field is present for IPA v4.0+ */
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2020-03-06 12:28:26 +08:00
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#define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11)
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2021-03-24 21:15:23 +08:00
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/* The next field is not present for IPA v4.0+ */
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2020-03-06 12:28:26 +08:00
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#define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15)
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2021-03-24 21:15:23 +08:00
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/* The next field and its values are not present for IPA v4.0+ */
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2020-03-06 12:28:26 +08:00
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#define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0)
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/* IPA_CMD_IP_PACKET_INIT */
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struct ipa_cmd_ip_packet_init {
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u8 dest_endpoint;
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u8 reserved[7];
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};
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/* Field masks for ipa_cmd_ip_packet_init dest_endpoint field */
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#define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0)
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/* IPA_CMD_DMA_SHARED_MEM */
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/* For IPA v4.0+, this opcode gets modified with pipeline clear options */
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#define DMA_SHARED_MEM_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)
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#define DMA_SHARED_MEM_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)
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struct ipa_cmd_hw_dma_mem_mem {
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__le16 clear_after_read; /* 0 or DMA_SHARED_MEM_CLEAR_AFTER_READ */
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__le16 size;
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__le16 local_addr;
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__le16 flags;
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__le64 system_addr;
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};
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/* Flag allowing atomic clear of target region after reading data (v4.0+)*/
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#define DMA_SHARED_MEM_CLEAR_AFTER_READ GENMASK(15, 15)
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/* Field masks for ipa_cmd_hw_dma_mem_mem structure fields */
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#define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0)
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2021-03-24 21:15:23 +08:00
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/* The next two fields are not present for IPA v4.0+ */
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2020-03-06 12:28:26 +08:00
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#define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1)
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#define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2)
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/* IPA_CMD_IP_PACKET_TAG_STATUS */
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struct ipa_cmd_ip_packet_tag_status {
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__le64 tag;
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};
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#define IP_PACKET_TAG_STATUS_TAG_FMASK GENMASK_ULL(63, 16)
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/* Immediate command payload */
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union ipa_cmd_payload {
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struct ipa_cmd_hw_ip_fltrt_init table_init;
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struct ipa_cmd_hw_hdr_init_local hdr_init_local;
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struct ipa_cmd_register_write register_write;
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struct ipa_cmd_ip_packet_init ip_packet_init;
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struct ipa_cmd_hw_dma_mem_mem dma_shared_mem;
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struct ipa_cmd_ip_packet_tag_status ip_packet_tag_status;
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};
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static void ipa_cmd_validate_build(void)
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{
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/* The sizes of a filter and route tables need to fit into fields
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* in the ipa_cmd_hw_ip_fltrt_init structure. Although hashed tables
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* might not be used, non-hashed and hashed tables have the same
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* maximum size. IPv4 and IPv6 filter tables have the same number
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* of entries, as and IPv4 and IPv6 route tables have the same number
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* of entries.
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*/
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2021-03-29 01:31:11 +08:00
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#define TABLE_SIZE (TABLE_COUNT_MAX * sizeof(__le64))
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2020-03-06 12:28:26 +08:00
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#define TABLE_COUNT_MAX max_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX)
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BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK));
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BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK));
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#undef TABLE_COUNT_MAX
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#undef TABLE_SIZE
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2021-07-27 01:40:07 +08:00
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/* Hashed and non-hashed fields are assumed to be the same size */
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BUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK) !=
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field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK));
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BUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK) !=
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field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK));
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2021-07-27 01:40:10 +08:00
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/* Valid endpoint numbers must fit in the IP packet init command */
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BUILD_BUG_ON(field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK) <
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IPA_ENDPOINT_MAX - 1);
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2021-07-27 01:40:07 +08:00
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}
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2020-03-06 12:28:26 +08:00
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/* Validate a memory region holding a table */
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2021-07-27 01:40:07 +08:00
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bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, bool route)
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2020-03-06 12:28:26 +08:00
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{
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2021-07-27 01:40:07 +08:00
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u32 offset_max = field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK);
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u32 size_max = field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK);
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const char *table = route ? "route" : "filter";
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2020-03-06 12:28:26 +08:00
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struct device *dev = &ipa->pdev->dev;
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2021-07-27 01:40:07 +08:00
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/* Size must fit in the immediate command field that holds it */
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if (mem->size > size_max) {
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dev_err(dev, "%s table region size too large\n", table);
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dev_err(dev, " (0x%04x > 0x%04x)\n",
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mem->size, size_max);
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return false;
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}
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/* Offset must fit in the immediate command field that holds it */
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2020-03-06 12:28:26 +08:00
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if (mem->offset > offset_max ||
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ipa->mem_offset > offset_max - mem->offset) {
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2021-07-27 01:40:07 +08:00
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dev_err(dev, "%s table region offset too large\n", table);
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2021-03-20 22:17:28 +08:00
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
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ipa->mem_offset, mem->offset, offset_max);
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2020-03-06 12:28:26 +08:00
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return false;
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}
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2021-07-27 01:40:07 +08:00
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/* Entire memory range must fit within IPA-local memory */
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2020-03-06 12:28:26 +08:00
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if (mem->offset > ipa->mem_size ||
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mem->size > ipa->mem_size - mem->offset) {
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2021-07-27 01:40:07 +08:00
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dev_err(dev, "%s table region out of range\n", table);
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2021-03-20 22:17:28 +08:00
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
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mem->offset, mem->size, ipa->mem_size);
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2020-03-06 12:28:26 +08:00
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return false;
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}
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return true;
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}
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/* Validate the memory region that holds headers */
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static bool ipa_cmd_header_valid(struct ipa *ipa)
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{
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struct device *dev = &ipa->pdev->dev;
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2021-06-11 03:23:02 +08:00
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const struct ipa_mem *mem;
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2020-03-06 12:28:26 +08:00
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u32 offset_max;
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u32 size_max;
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2021-06-11 03:23:02 +08:00
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u32 offset;
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2020-03-06 12:28:26 +08:00
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u32 size;
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2021-06-11 03:23:02 +08:00
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/* In ipa_cmd_hdr_init_local_add() we record the offset and size of
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* the header table memory area in an immediate command. Make sure
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* the offset and size fit in the fields that need to hold them, and
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* that the entire range is within the overall IPA memory range.
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2021-03-20 22:17:28 +08:00
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*/
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2020-03-06 12:28:26 +08:00
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offset_max = field_max(HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK);
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2021-06-11 03:23:02 +08:00
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size_max = field_max(HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK);
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/* The header memory area contains both the modem and AP header
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* regions. The modem portion defines the address of the region.
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*/
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2021-06-11 03:23:07 +08:00
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mem = ipa_mem_find(ipa, IPA_MEM_MODEM_HEADER);
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2021-06-11 03:23:02 +08:00
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offset = mem->offset;
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size = mem->size;
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/* Make sure the offset fits in the IPA command */
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if (offset > offset_max || ipa->mem_offset > offset_max - offset) {
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2021-03-20 22:17:28 +08:00
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dev_err(dev, "header table region offset too large\n");
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
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2021-06-11 03:23:02 +08:00
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ipa->mem_offset, offset, offset_max);
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2021-03-20 22:17:28 +08:00
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2020-03-06 12:28:26 +08:00
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return false;
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}
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2021-06-11 03:23:07 +08:00
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/* Add the size of the AP portion (if defined) to the combined size */
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mem = ipa_mem_find(ipa, IPA_MEM_AP_HEADER);
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if (mem)
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size += mem->size;
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2021-03-20 22:17:28 +08:00
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2021-06-11 03:23:02 +08:00
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/* Make sure the combined size fits in the IPA command */
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2021-03-20 22:17:28 +08:00
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if (size > size_max) {
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dev_err(dev, "header table region size too large\n");
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dev_err(dev, " (0x%04x > 0x%08x)\n", size, size_max);
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return false;
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}
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2021-06-11 03:23:02 +08:00
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/* Make sure the entire combined area fits in IPA memory */
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if (size > ipa->mem_size || offset > ipa->mem_size - size) {
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2021-03-20 22:17:28 +08:00
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dev_err(dev, "header table region out of range\n");
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
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2021-06-11 03:23:02 +08:00
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offset, size, ipa->mem_size);
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2021-03-20 22:17:28 +08:00
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2020-03-06 12:28:26 +08:00
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return false;
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}
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return true;
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}
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/* Indicate whether an offset can be used with a register_write command */
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static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa,
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const char *name, u32 offset)
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{
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struct ipa_cmd_register_write *payload;
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struct device *dev = &ipa->pdev->dev;
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u32 offset_max;
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u32 bit_count;
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/* The maximum offset in a register_write immediate command depends
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2021-03-24 21:15:23 +08:00
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* on the version of IPA. A 16 bit offset is always supported,
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* but starting with IPA v4.0 some additional high-order bits are
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* allowed.
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2020-03-06 12:28:26 +08:00
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*/
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bit_count = BITS_PER_BYTE * sizeof(payload->offset);
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2021-03-24 21:15:23 +08:00
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if (ipa->version >= IPA_VERSION_4_0)
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2020-03-06 12:28:26 +08:00
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bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK);
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BUILD_BUG_ON(bit_count > 32);
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2021-02-12 22:34:00 +08:00
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offset_max = ~0U >> (32 - bit_count);
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2020-03-06 12:28:26 +08:00
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|
2021-02-12 22:34:00 +08:00
|
|
|
/* Make sure the offset can be represented by the field(s)
|
|
|
|
* that holds it. Also make sure the offset is not outside
|
|
|
|
* the overall IPA memory range.
|
|
|
|
*/
|
2020-03-06 12:28:26 +08:00
|
|
|
if (offset > offset_max || ipa->mem_offset > offset_max - offset) {
|
|
|
|
dev_err(dev, "%s offset too large 0x%04x + 0x%04x > 0x%04x)\n",
|
2021-02-12 22:34:00 +08:00
|
|
|
name, ipa->mem_offset, offset, offset_max);
|
2020-03-06 12:28:26 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check whether offsets passed to register_write are valid */
|
|
|
|
static bool ipa_cmd_register_write_valid(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
const char *name;
|
|
|
|
u32 offset;
|
|
|
|
|
2021-02-12 22:34:00 +08:00
|
|
|
/* If hashed tables are supported, ensure the hash flush register
|
|
|
|
* offset will fit in a register write IPA immediate command.
|
|
|
|
*/
|
2021-02-12 22:34:01 +08:00
|
|
|
if (ipa_table_hash_support(ipa)) {
|
2021-02-12 22:34:00 +08:00
|
|
|
offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version);
|
|
|
|
name = "filter/route hash flush";
|
|
|
|
if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
|
|
|
|
return false;
|
|
|
|
}
|
2020-03-06 12:28:26 +08:00
|
|
|
|
2021-02-12 22:34:00 +08:00
|
|
|
/* Each endpoint can have a status endpoint associated with it,
|
|
|
|
* and this is recorded in an endpoint register. If the modem
|
|
|
|
* crashes, we reset the status endpoint for all modem endpoints
|
|
|
|
* using a register write IPA immediate command. Make sure the
|
|
|
|
* worst case (highest endpoint number) offset of that endpoint
|
|
|
|
* fits in the register write command field(s) that must hold it.
|
|
|
|
*/
|
|
|
|
offset = IPA_REG_ENDP_STATUS_N_OFFSET(IPA_ENDPOINT_COUNT - 1);
|
2020-03-06 12:28:26 +08:00
|
|
|
name = "maximal endpoint status";
|
|
|
|
if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ipa_cmd_data_valid(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
if (!ipa_cmd_header_valid(ipa))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!ipa_cmd_register_write_valid(ipa))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int ipa_cmd_pool_init(struct gsi_channel *channel, u32 tre_max)
|
|
|
|
{
|
|
|
|
struct gsi_trans_info *trans_info = &channel->trans_info;
|
|
|
|
struct device *dev = channel->gsi->dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* This is as good a place as any to validate build constants */
|
|
|
|
ipa_cmd_validate_build();
|
|
|
|
|
|
|
|
/* Even though command payloads are allocated one at a time,
|
|
|
|
* a single transaction can require up to tlv_count of them,
|
|
|
|
* so we treat them as if that many can be allocated at once.
|
|
|
|
*/
|
|
|
|
ret = gsi_trans_pool_init_dma(dev, &trans_info->cmd_pool,
|
|
|
|
sizeof(union ipa_cmd_payload),
|
|
|
|
tre_max, channel->tlv_count);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Each TRE needs a command info structure */
|
|
|
|
ret = gsi_trans_pool_init(&trans_info->info_pool,
|
|
|
|
sizeof(struct ipa_cmd_info),
|
|
|
|
tre_max, channel->tlv_count);
|
|
|
|
if (ret)
|
|
|
|
gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_cmd_pool_exit(struct gsi_channel *channel)
|
|
|
|
{
|
|
|
|
struct gsi_trans_info *trans_info = &channel->trans_info;
|
|
|
|
struct device *dev = channel->gsi->dev;
|
|
|
|
|
|
|
|
gsi_trans_pool_exit(&trans_info->info_pool);
|
|
|
|
gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool);
|
|
|
|
}
|
|
|
|
|
|
|
|
static union ipa_cmd_payload *
|
|
|
|
ipa_cmd_payload_alloc(struct ipa *ipa, dma_addr_t *addr)
|
|
|
|
{
|
|
|
|
struct gsi_trans_info *trans_info;
|
|
|
|
struct ipa_endpoint *endpoint;
|
|
|
|
|
|
|
|
endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
|
|
|
|
trans_info = &ipa->gsi.channel[endpoint->channel_id].trans_info;
|
|
|
|
|
|
|
|
return gsi_trans_pool_alloc_dma(&trans_info->cmd_pool, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If hash_size is 0, hash_offset and hash_addr ignored. */
|
|
|
|
void ipa_cmd_table_init_add(struct gsi_trans *trans,
|
|
|
|
enum ipa_cmd_opcode opcode, u16 size, u32 offset,
|
|
|
|
dma_addr_t addr, u16 hash_size, u32 hash_offset,
|
|
|
|
dma_addr_t hash_addr)
|
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
|
|
|
enum dma_data_direction direction = DMA_TO_DEVICE;
|
|
|
|
struct ipa_cmd_hw_ip_fltrt_init *payload;
|
|
|
|
union ipa_cmd_payload *cmd_payload;
|
|
|
|
dma_addr_t payload_addr;
|
|
|
|
u64 val;
|
|
|
|
|
|
|
|
/* Record the non-hash table offset and size */
|
|
|
|
offset += ipa->mem_offset;
|
|
|
|
val = u64_encode_bits(offset, IP_FLTRT_FLAGS_NHASH_ADDR_FMASK);
|
|
|
|
val |= u64_encode_bits(size, IP_FLTRT_FLAGS_NHASH_SIZE_FMASK);
|
|
|
|
|
|
|
|
/* The hash table offset and address are zero if its size is 0 */
|
|
|
|
if (hash_size) {
|
|
|
|
/* Record the hash table offset and size */
|
|
|
|
hash_offset += ipa->mem_offset;
|
|
|
|
val |= u64_encode_bits(hash_offset,
|
|
|
|
IP_FLTRT_FLAGS_HASH_ADDR_FMASK);
|
|
|
|
val |= u64_encode_bits(hash_size,
|
|
|
|
IP_FLTRT_FLAGS_HASH_SIZE_FMASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
|
|
|
|
payload = &cmd_payload->table_init;
|
|
|
|
|
|
|
|
/* Fill in all offsets and sizes and the non-hash table address */
|
|
|
|
if (hash_size)
|
|
|
|
payload->hash_rules_addr = cpu_to_le64(hash_addr);
|
|
|
|
payload->flags = cpu_to_le64(val);
|
|
|
|
payload->nhash_rules_addr = cpu_to_le64(addr);
|
|
|
|
|
|
|
|
gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
|
|
|
|
direction, opcode);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize header space in IPA-local memory */
|
|
|
|
void ipa_cmd_hdr_init_local_add(struct gsi_trans *trans, u32 offset, u16 size,
|
|
|
|
dma_addr_t addr)
|
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
|
|
|
enum ipa_cmd_opcode opcode = IPA_CMD_HDR_INIT_LOCAL;
|
|
|
|
enum dma_data_direction direction = DMA_TO_DEVICE;
|
|
|
|
struct ipa_cmd_hw_hdr_init_local *payload;
|
|
|
|
union ipa_cmd_payload *cmd_payload;
|
|
|
|
dma_addr_t payload_addr;
|
|
|
|
u32 flags;
|
|
|
|
|
|
|
|
offset += ipa->mem_offset;
|
|
|
|
|
|
|
|
/* With this command we tell the IPA where in its local memory the
|
|
|
|
* header tables reside. The content of the buffer provided is
|
|
|
|
* also written via DMA into that space. The IPA hardware owns
|
|
|
|
* the table, but the AP must initialize it.
|
|
|
|
*/
|
|
|
|
cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
|
|
|
|
payload = &cmd_payload->hdr_init_local;
|
|
|
|
|
|
|
|
payload->hdr_table_addr = cpu_to_le64(addr);
|
|
|
|
flags = u32_encode_bits(size, HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK);
|
|
|
|
flags |= u32_encode_bits(offset, HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK);
|
|
|
|
payload->flags = cpu_to_le32(flags);
|
|
|
|
|
|
|
|
gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
|
|
|
|
direction, opcode);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value,
|
|
|
|
u32 mask, bool clear_full)
|
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
|
|
|
struct ipa_cmd_register_write *payload;
|
|
|
|
union ipa_cmd_payload *cmd_payload;
|
|
|
|
u32 opcode = IPA_CMD_REGISTER_WRITE;
|
|
|
|
dma_addr_t payload_addr;
|
|
|
|
u32 clear_option;
|
|
|
|
u32 options;
|
|
|
|
u16 flags;
|
|
|
|
|
|
|
|
/* pipeline_clear_src_grp is not used */
|
|
|
|
clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps;
|
|
|
|
|
2021-03-24 21:15:23 +08:00
|
|
|
/* IPA v4.0+ represents the pipeline clear options in the opcode. It
|
|
|
|
* also supports a larger offset by encoding additional high-order
|
|
|
|
* bits in the payload flags field.
|
|
|
|
*/
|
|
|
|
if (ipa->version >= IPA_VERSION_4_0) {
|
2020-03-06 12:28:26 +08:00
|
|
|
u16 offset_high;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* Opcode encodes pipeline clear options */
|
|
|
|
/* SKIP_CLEAR is always 0 (don't skip pipeline clear) */
|
|
|
|
val = u16_encode_bits(clear_option,
|
|
|
|
REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK);
|
|
|
|
opcode |= val;
|
|
|
|
|
|
|
|
/* Extract the high 4 bits from the offset */
|
|
|
|
offset_high = (u16)u32_get_bits(offset, GENMASK(19, 16));
|
|
|
|
offset &= (1 << 16) - 1;
|
|
|
|
|
|
|
|
/* Extract the top 4 bits and encode it into the flags field */
|
|
|
|
flags = u16_encode_bits(offset_high,
|
|
|
|
REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK);
|
|
|
|
options = 0; /* reserved */
|
|
|
|
|
|
|
|
} else {
|
|
|
|
flags = 0; /* SKIP_CLEAR flag is always 0 */
|
|
|
|
options = u16_encode_bits(clear_option,
|
|
|
|
REGISTER_WRITE_CLEAR_OPTIONS_FMASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
|
|
|
|
payload = &cmd_payload->register_write;
|
|
|
|
|
|
|
|
payload->flags = cpu_to_le16(flags);
|
|
|
|
payload->offset = cpu_to_le16((u16)offset);
|
|
|
|
payload->value = cpu_to_le32(value);
|
|
|
|
payload->value_mask = cpu_to_le32(mask);
|
|
|
|
payload->clear_options = cpu_to_le32(options);
|
|
|
|
|
|
|
|
gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
|
|
|
|
DMA_NONE, opcode);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Skip IP packet processing on the next data transfer on a TX channel */
|
|
|
|
static void ipa_cmd_ip_packet_init_add(struct gsi_trans *trans, u8 endpoint_id)
|
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
|
|
|
enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_INIT;
|
|
|
|
enum dma_data_direction direction = DMA_TO_DEVICE;
|
|
|
|
struct ipa_cmd_ip_packet_init *payload;
|
|
|
|
union ipa_cmd_payload *cmd_payload;
|
|
|
|
dma_addr_t payload_addr;
|
|
|
|
|
|
|
|
cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
|
|
|
|
payload = &cmd_payload->ip_packet_init;
|
|
|
|
|
|
|
|
payload->dest_endpoint = u8_encode_bits(endpoint_id,
|
|
|
|
IPA_PACKET_INIT_DEST_ENDPOINT_FMASK);
|
|
|
|
|
|
|
|
gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
|
|
|
|
direction, opcode);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Use a DMA command to read or write a block of IPA-resident memory */
|
|
|
|
void ipa_cmd_dma_shared_mem_add(struct gsi_trans *trans, u32 offset, u16 size,
|
|
|
|
dma_addr_t addr, bool toward_ipa)
|
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
|
|
|
enum ipa_cmd_opcode opcode = IPA_CMD_DMA_SHARED_MEM;
|
|
|
|
struct ipa_cmd_hw_dma_mem_mem *payload;
|
|
|
|
union ipa_cmd_payload *cmd_payload;
|
|
|
|
enum dma_data_direction direction;
|
|
|
|
dma_addr_t payload_addr;
|
|
|
|
u16 flags;
|
|
|
|
|
|
|
|
/* size and offset must fit in 16 bit fields */
|
2021-07-27 01:40:10 +08:00
|
|
|
WARN_ON(!size);
|
|
|
|
WARN_ON(size > U16_MAX);
|
|
|
|
WARN_ON(offset > U16_MAX || ipa->mem_offset > U16_MAX - offset);
|
2020-03-06 12:28:26 +08:00
|
|
|
|
|
|
|
offset += ipa->mem_offset;
|
|
|
|
|
|
|
|
cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
|
|
|
|
payload = &cmd_payload->dma_shared_mem;
|
|
|
|
|
|
|
|
/* payload->clear_after_read was reserved prior to IPA v4.0. It's
|
|
|
|
* never needed for current code, so it's 0 regardless of version.
|
|
|
|
*/
|
|
|
|
payload->size = cpu_to_le16(size);
|
|
|
|
payload->local_addr = cpu_to_le16(offset);
|
|
|
|
/* payload->flags:
|
|
|
|
* direction: 0 = write to IPA, 1 read from IPA
|
|
|
|
* Starting at v4.0 these are reserved; either way, all zero:
|
|
|
|
* pipeline clear: 0 = wait for pipeline clear (don't skip)
|
|
|
|
* clear_options: 0 = pipeline_clear_hps
|
|
|
|
* Instead, for v4.0+ these are encoded in the opcode. But again
|
|
|
|
* since both values are 0 we won't bother OR'ing them in.
|
|
|
|
*/
|
|
|
|
flags = toward_ipa ? 0 : DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK;
|
|
|
|
payload->flags = cpu_to_le16(flags);
|
|
|
|
payload->system_addr = cpu_to_le64(addr);
|
|
|
|
|
|
|
|
direction = toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
|
|
|
|
|
|
|
|
gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
|
|
|
|
direction, opcode);
|
|
|
|
}
|
|
|
|
|
2021-01-27 02:57:02 +08:00
|
|
|
static void ipa_cmd_ip_tag_status_add(struct gsi_trans *trans)
|
2020-03-06 12:28:26 +08:00
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
|
|
|
enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_TAG_STATUS;
|
|
|
|
enum dma_data_direction direction = DMA_TO_DEVICE;
|
|
|
|
struct ipa_cmd_ip_packet_tag_status *payload;
|
|
|
|
union ipa_cmd_payload *cmd_payload;
|
|
|
|
dma_addr_t payload_addr;
|
|
|
|
|
|
|
|
cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
|
|
|
|
payload = &cmd_payload->ip_packet_tag_status;
|
|
|
|
|
2021-01-27 02:57:02 +08:00
|
|
|
payload->tag = le64_encode_bits(0, IP_PACKET_TAG_STATUS_TAG_FMASK);
|
2020-03-06 12:28:26 +08:00
|
|
|
|
|
|
|
gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
|
|
|
|
direction, opcode);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Issue a small command TX data transfer */
|
2021-01-27 02:57:03 +08:00
|
|
|
static void ipa_cmd_transfer_add(struct gsi_trans *trans)
|
2020-03-06 12:28:26 +08:00
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
|
|
|
enum dma_data_direction direction = DMA_TO_DEVICE;
|
|
|
|
enum ipa_cmd_opcode opcode = IPA_CMD_NONE;
|
|
|
|
union ipa_cmd_payload *payload;
|
|
|
|
dma_addr_t payload_addr;
|
|
|
|
|
|
|
|
/* Just transfer a zero-filled payload structure */
|
|
|
|
payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
|
|
|
|
|
|
|
|
gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
|
|
|
|
direction, opcode);
|
|
|
|
}
|
|
|
|
|
2021-01-27 02:56:58 +08:00
|
|
|
/* Add immediate commands to a transaction to clear the hardware pipeline */
|
|
|
|
void ipa_cmd_pipeline_clear_add(struct gsi_trans *trans)
|
2020-03-06 12:28:26 +08:00
|
|
|
{
|
|
|
|
struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
|
2020-05-08 03:14:04 +08:00
|
|
|
struct ipa_endpoint *endpoint;
|
2020-03-06 12:28:26 +08:00
|
|
|
|
2021-01-27 02:57:01 +08:00
|
|
|
/* This will complete when the transfer is received */
|
|
|
|
reinit_completion(&ipa->completion);
|
|
|
|
|
2021-01-27 02:56:58 +08:00
|
|
|
/* Issue a no-op register write command (mask 0 means no write) */
|
2020-05-08 03:14:04 +08:00
|
|
|
ipa_cmd_register_write_add(trans, 0, 0, 0, true);
|
2021-01-27 02:56:58 +08:00
|
|
|
|
|
|
|
/* Send a data packet through the IPA pipeline. The packet_init
|
|
|
|
* command says to send the next packet directly to the exception
|
|
|
|
* endpoint without any other IPA processing. The tag_status
|
|
|
|
* command requests that status be generated on completion of
|
2021-01-27 02:57:02 +08:00
|
|
|
* that transfer, and that it will be tagged with a value.
|
2021-01-27 02:56:58 +08:00
|
|
|
* Finally, the transfer command sends a small packet of data
|
|
|
|
* (instead of a command) using the command endpoint.
|
|
|
|
*/
|
|
|
|
endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX];
|
2020-05-08 03:14:04 +08:00
|
|
|
ipa_cmd_ip_packet_init_add(trans, endpoint->endpoint_id);
|
2021-01-27 02:57:02 +08:00
|
|
|
ipa_cmd_ip_tag_status_add(trans);
|
2021-01-27 02:57:03 +08:00
|
|
|
ipa_cmd_transfer_add(trans);
|
2020-03-06 12:28:26 +08:00
|
|
|
}
|
|
|
|
|
2021-01-27 02:56:58 +08:00
|
|
|
/* Returns the number of commands required to clear the pipeline */
|
|
|
|
u32 ipa_cmd_pipeline_clear_count(void)
|
2020-03-06 12:28:26 +08:00
|
|
|
{
|
|
|
|
return 4;
|
|
|
|
}
|
|
|
|
|
2021-01-27 02:57:01 +08:00
|
|
|
void ipa_cmd_pipeline_clear_wait(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
wait_for_completion(&ipa->completion);
|
|
|
|
}
|
|
|
|
|
2020-03-06 12:28:26 +08:00
|
|
|
static struct ipa_cmd_info *
|
|
|
|
ipa_cmd_info_alloc(struct ipa_endpoint *endpoint, u32 tre_count)
|
|
|
|
{
|
|
|
|
struct gsi_channel *channel;
|
|
|
|
|
|
|
|
channel = &endpoint->ipa->gsi.channel[endpoint->channel_id];
|
|
|
|
|
|
|
|
return gsi_trans_pool_alloc(&channel->trans_info.info_pool, tre_count);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate a transaction for the command TX endpoint */
|
|
|
|
struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count)
|
|
|
|
{
|
|
|
|
struct ipa_endpoint *endpoint;
|
|
|
|
struct gsi_trans *trans;
|
|
|
|
|
|
|
|
endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
|
|
|
|
|
|
|
|
trans = gsi_channel_trans_alloc(&ipa->gsi, endpoint->channel_id,
|
|
|
|
tre_count, DMA_NONE);
|
|
|
|
if (trans)
|
|
|
|
trans->info = ipa_cmd_info_alloc(endpoint, tre_count);
|
|
|
|
|
|
|
|
return trans;
|
|
|
|
}
|