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OpenCloudOS-Kernel/arch/arm/boot/dts/sh73a0.dtsi

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ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 20:12:43 +08:00
/*
* Device Tree Source for the SH73A0 SoC
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "renesas,sh73a0";
cpus {
ARM: mach-shmobile: sh73a0: Add reg and device_type properties to cpus Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-28 08:41:40 +08:00
#address-cells = <1>;
#size-cells = <0>;
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 20:12:43 +08:00
cpu@0 {
ARM: mach-shmobile: sh73a0: Add reg and device_type properties to cpus Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-28 08:41:40 +08:00
device_type = "cpu";
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 20:12:43 +08:00
compatible = "arm,cortex-a9";
ARM: mach-shmobile: sh73a0: Add reg and device_type properties to cpus Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-28 08:41:40 +08:00
reg = <0>;
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 20:12:43 +08:00
};
cpu@1 {
ARM: mach-shmobile: sh73a0: Add reg and device_type properties to cpus Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-28 08:41:40 +08:00
device_type = "cpu";
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 20:12:43 +08:00
compatible = "arm,cortex-a9";
ARM: mach-shmobile: sh73a0: Add reg and device_type properties to cpus Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-28 08:41:40 +08:00
reg = <1>;
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 20:12:43 +08:00
};
};
gic: interrupt-controller@f0001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xf0001000 0x1000>,
<0xf0000100 0x100>;
};
ARM: mach-shmobile: sh73a0: Minimal setup using DT Allow a minimal setup of the sh73a0 SoC using a flattened device tree. In particular, Configure the i2c controllers using a flattened device tree. SCI serial controller and CMT clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC. *** Please note that the clock initialisation scheme used in this patch does not currently work with SMP as there is a yet to be resolved lock-up in workqueue initialisation. CONFIG_SMP must be disabled when using this code. *** Includes update from Thierry Reding to no longer use gic_handle_irq() Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> fix
2012-11-21 21:00:15 +08:00
i2c0: i2c@0xe6820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6820000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 167 0x4
0 168 0x4
0 169 0x4
0 170 0x4>;
};
i2c1: i2c@0xe6822000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6822000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 51 0x4
0 52 0x4
0 53 0x4
0 54 0x4>;
};
i2c2: i2c@0xe6824000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6824000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 171 0x4
0 172 0x4
0 173 0x4
0 174 0x4>;
};
i2c3: i2c@0xe6826000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6826000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 183 0x4
0 184 0x4
0 185 0x4
0 186 0x4>;
};
i2c4: i2c@0xe6828000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6828000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 187 0x4
0 188 0x4
0 189 0x4
0 190 0x4>;
};
ARM: shmobile: sh73a0: move SDHI and MMCIF DT nodes to sh73a0.dtsi To avoid having to repeat common DT node properties in all .dts files move them to SoC's .dtsi file, setting their status to "disabled." Individual boards will pick up devices, that they want to use and change their DT node status to enabled. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-03-19 20:47:43 +08:00
mmcif: mmcif@0x10010000 {
compatible = "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 140 0x4
0 141 0x4>;
reg-io-width = <4>;
status = "disabled";
};
sdhi0: sdhi@0xee100000 {
compatible = "renesas,shmobile-sdhi";
reg = <0xee100000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 83 4
0 84 4
0 85 4>;
toshiba,mmc-has-idle-wait;
status = "disabled";
};
/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
sdhi1: sdhi@0xee120000 {
compatible = "renesas,shmobile-sdhi";
reg = <0xee120000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 88 4
0 89 4>;
toshiba,mmc-wrprotect-disable;
toshiba,mmc-has-idle-wait;
status = "disabled";
};
sdhi2: sdhi@0xee140000 {
compatible = "renesas,shmobile-sdhi";
reg = <0xee140000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 104 4
0 105 4>;
toshiba,mmc-wrprotect-disable;
toshiba,mmc-has-idle-wait;
status = "disabled";
};
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 20:12:43 +08:00
};