2017-03-04 07:37:23 +08:00
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v3_1.h"
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#include "vega10/soc15ip.h"
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#include "vega10/MP/mp_9_0_offset.h"
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#include "vega10/MP/mp_9_0_sh_mask.h"
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#include "vega10/GC/gc_9_0_offset.h"
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#include "vega10/SDMA0/sdma0_4_0_offset.h"
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#include "vega10/NBIO/nbio_6_1_offset.h"
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MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
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MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
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#define smnMP1_FIRMWARE_FLAGS 0x3010028
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static int
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psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
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{
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switch(ucode->ucode_id) {
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case AMDGPU_UCODE_ID_SDMA0:
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*type = GFX_FW_TYPE_SDMA0;
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break;
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case AMDGPU_UCODE_ID_SDMA1:
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*type = GFX_FW_TYPE_SDMA1;
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break;
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case AMDGPU_UCODE_ID_CP_CE:
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*type = GFX_FW_TYPE_CP_CE;
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break;
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case AMDGPU_UCODE_ID_CP_PFP:
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*type = GFX_FW_TYPE_CP_PFP;
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break;
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case AMDGPU_UCODE_ID_CP_ME:
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*type = GFX_FW_TYPE_CP_ME;
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break;
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case AMDGPU_UCODE_ID_CP_MEC1:
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*type = GFX_FW_TYPE_CP_MEC;
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break;
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case AMDGPU_UCODE_ID_CP_MEC1_JT:
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*type = GFX_FW_TYPE_CP_MEC_ME1;
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break;
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case AMDGPU_UCODE_ID_CP_MEC2:
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*type = GFX_FW_TYPE_CP_MEC;
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break;
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case AMDGPU_UCODE_ID_CP_MEC2_JT:
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*type = GFX_FW_TYPE_CP_MEC_ME2;
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break;
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case AMDGPU_UCODE_ID_RLC_G:
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*type = GFX_FW_TYPE_RLC_G;
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break;
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case AMDGPU_UCODE_ID_SMC:
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*type = GFX_FW_TYPE_SMU;
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break;
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case AMDGPU_UCODE_ID_UVD:
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*type = GFX_FW_TYPE_UVD;
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break;
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case AMDGPU_UCODE_ID_VCE:
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*type = GFX_FW_TYPE_VCE;
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break;
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case AMDGPU_UCODE_ID_MAXIMUM:
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default:
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return -EINVAL;
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}
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return 0;
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}
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int psp_v3_1_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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const char *chip_name;
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char fw_name[30];
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int err = 0;
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const struct psp_firmware_header_v1_0 *hdr;
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DRM_DEBUG("\n");
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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chip_name = "vega10";
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break;
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default: BUG();
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}
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
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err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
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if (err)
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goto out;
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err = amdgpu_ucode_validate(adev->psp.sos_fw);
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if (err)
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goto out;
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hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
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adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
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adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
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adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
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adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
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le32_to_cpu(hdr->sos_size_bytes);
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adev->psp.sys_start_addr = (uint8_t *)hdr +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes);
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adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
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le32_to_cpu(hdr->sos_offset_bytes);
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
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err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
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if (err)
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goto out;
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err = amdgpu_ucode_validate(adev->psp.asd_fw);
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if (err)
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goto out;
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hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
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adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
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adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
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adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
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adev->psp.asd_start_addr = (uint8_t *)hdr +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes);
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return 0;
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out:
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if (err) {
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dev_err(adev->dev,
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"psp v3.1: Failed to load firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->psp.sos_fw);
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adev->psp.sos_fw = NULL;
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release_firmware(adev->psp.asd_fw);
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adev->psp.asd_fw = NULL;
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}
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return err;
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}
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int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
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{
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int ret;
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uint32_t psp_gfxdrv_command_reg = 0;
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struct amdgpu_bo *psp_sysdrv;
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void *psp_sysdrv_virt = NULL;
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uint64_t psp_sysdrv_mem;
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struct amdgpu_device *adev = psp->adev;
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2017-03-28 19:48:10 +08:00
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uint32_t size, sol_reg;
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/* Check sOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81));
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if (sol_reg)
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return 0;
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2017-03-04 07:37:23 +08:00
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/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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if (ret)
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return ret;
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/*
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* Create a 1 meg GART memory to store the psp sys driver
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* binary with a 1 meg aligned address
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*/
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size = (psp->sys_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) &
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(~(PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1));
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ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT,
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AMDGPU_GEM_DOMAIN_GTT,
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&psp_sysdrv,
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&psp_sysdrv_mem,
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&psp_sysdrv_virt);
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if (ret)
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return ret;
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/* Copy PSP System Driver binary to memory */
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memcpy(psp_sysdrv_virt, psp->sys_start_addr, psp->sys_bin_size);
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/* Provide the sys driver to bootrom */
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WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),
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(uint32_t)(psp_sysdrv_mem >> 20));
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psp_gfxdrv_command_reg = 1 << 16;
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WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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psp_gfxdrv_command_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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amdgpu_bo_free_kernel(&psp_sysdrv, &psp_sysdrv_mem, &psp_sysdrv_virt);
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return ret;
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}
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int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
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{
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int ret;
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unsigned int psp_gfxdrv_command_reg = 0;
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struct amdgpu_bo *psp_sos;
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void *psp_sos_virt = NULL;
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uint64_t psp_sos_mem;
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struct amdgpu_device *adev = psp->adev;
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2017-03-28 19:48:10 +08:00
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uint32_t size, sol_reg;
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/* Check sOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81));
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if (sol_reg)
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return 0;
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2017-03-04 07:37:23 +08:00
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/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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if (ret)
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return ret;
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size = (psp->sos_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) &
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(~((uint64_t)PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1));
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ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT,
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AMDGPU_GEM_DOMAIN_GTT,
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&psp_sos,
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&psp_sos_mem,
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&psp_sos_virt);
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if (ret)
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return ret;
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/* Copy Secure OS binary to PSP memory */
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memcpy(psp_sos_virt, psp->sos_start_addr, psp->sos_bin_size);
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/* Provide the PSP secure OS to bootrom */
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WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),
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(uint32_t)(psp_sos_mem >> 20));
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psp_gfxdrv_command_reg = 2 << 16;
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WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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psp_gfxdrv_command_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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#if 0
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
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RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)),
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0, true);
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#endif
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amdgpu_bo_free_kernel(&psp_sos, &psp_sos_mem, &psp_sos_virt);
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return ret;
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}
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int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
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{
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int ret;
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uint64_t fw_mem_mc_addr = ucode->mc_addr;
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memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
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cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
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cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
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cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
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cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
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ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
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if (ret)
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DRM_ERROR("Unknown firmware type\n");
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return ret;
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}
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int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct psp_ring *ring;
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struct amdgpu_device *adev = psp->adev;
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ring = &psp->km_ring;
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ring->ring_type = ring_type;
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/* allocate 4k Page of Local Frame Buffer memory for ring */
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ring->ring_size = 0x1000;
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ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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if (ret) {
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ring->ring_size = 0;
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return ret;
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}
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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|
|
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg);
|
|
|
|
/* Write high address of the ring to C2PMSG_70 */
|
|
|
|
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
|
|
|
|
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg);
|
|
|
|
/* Write size of ring to C2PMSG_71 */
|
|
|
|
psp_ring_reg = ring->ring_size;
|
|
|
|
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg);
|
|
|
|
/* Write the ring initialization command to C2PMSG_64 */
|
|
|
|
psp_ring_reg = ring_type;
|
|
|
|
psp_ring_reg = psp_ring_reg << 16;
|
|
|
|
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg);
|
|
|
|
|
|
|
|
/* there might be handshake issue with hardware which needs delay */
|
|
|
|
mdelay(20);
|
|
|
|
|
|
|
|
/* Wait for response flag (bit 31) in C2PMSG_64 */
|
|
|
|
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
|
|
|
|
0x80000000, 0x8000FFFF, false);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int psp_v3_1_cmd_submit(struct psp_context *psp,
|
|
|
|
struct amdgpu_firmware_info *ucode,
|
|
|
|
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
|
|
|
|
int index)
|
|
|
|
{
|
|
|
|
unsigned int psp_write_ptr_reg = 0;
|
|
|
|
struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
|
|
|
|
struct psp_ring *ring = &psp->km_ring;
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
uint32_t ring_size_dw = ring->ring_size / 4;
|
|
|
|
uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
|
|
|
|
|
|
|
|
/* KM (GPCOM) prepare write pointer */
|
|
|
|
psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67));
|
|
|
|
|
|
|
|
/* Update KM RB frame pointer to new frame */
|
|
|
|
/* write_frame ptr increments by size of rb_frame in bytes */
|
|
|
|
/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
|
|
|
|
if ((psp_write_ptr_reg % ring_size_dw) == 0)
|
|
|
|
write_frame = ring->ring_mem;
|
|
|
|
else
|
|
|
|
write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
|
|
|
|
|
|
|
|
/* Initialize KM RB frame */
|
|
|
|
memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
|
|
|
|
|
|
|
|
/* Update KM RB frame */
|
|
|
|
write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
|
|
|
|
write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
|
|
|
|
write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
|
|
|
|
write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
|
|
|
|
write_frame->fence_value = index;
|
|
|
|
|
|
|
|
/* Update the write Pointer in DWORDs */
|
|
|
|
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
|
|
|
|
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
|
|
|
|
unsigned int *sram_data_reg_offset,
|
|
|
|
enum AMDGPU_UCODE_ID ucode_id)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
switch(ucode_id) {
|
|
|
|
/* TODO: needs to confirm */
|
|
|
|
#if 0
|
|
|
|
case AMDGPU_UCODE_ID_SMC:
|
|
|
|
*sram_offset = 0;
|
|
|
|
*sram_addr_reg_offset = 0;
|
|
|
|
*sram_data_reg_offset = 0;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_CE:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_PFP:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_ME:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_MEC1:
|
|
|
|
*sram_offset = 0x10000;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_MEC2:
|
|
|
|
*sram_offset = 0x10000;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_RLC_G:
|
|
|
|
*sram_offset = 0x2000;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_SDMA0:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* TODO: needs to confirm */
|
|
|
|
#if 0
|
|
|
|
case AMDGPU_UCODE_ID_SDMA1:
|
|
|
|
*sram_offset = ;
|
|
|
|
*sram_addr_reg_offset = ;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_UVD:
|
|
|
|
*sram_offset = ;
|
|
|
|
*sram_addr_reg_offset = ;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_VCE:
|
|
|
|
*sram_offset = ;
|
|
|
|
*sram_addr_reg_offset = ;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_MAXIMUM:
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool psp_v3_1_compare_sram_data(struct psp_context *psp,
|
|
|
|
struct amdgpu_firmware_info *ucode,
|
|
|
|
enum AMDGPU_UCODE_ID ucode_type)
|
|
|
|
{
|
|
|
|
int err = 0;
|
|
|
|
unsigned int fw_sram_reg_val = 0;
|
|
|
|
unsigned int fw_sram_addr_reg_offset = 0;
|
|
|
|
unsigned int fw_sram_data_reg_offset = 0;
|
|
|
|
unsigned int ucode_size;
|
|
|
|
uint32_t *ucode_mem = NULL;
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
|
|
|
|
err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
|
|
|
|
&fw_sram_data_reg_offset, ucode_type);
|
|
|
|
if (err)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
|
|
|
|
|
|
|
|
ucode_size = ucode->ucode_size;
|
|
|
|
ucode_mem = (uint32_t *)ucode->kaddr;
|
2017-04-04 23:36:20 +08:00
|
|
|
while (ucode_size) {
|
2017-03-04 07:37:23 +08:00
|
|
|
fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
|
|
|
|
|
|
|
|
if (*ucode_mem != fw_sram_reg_val)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
ucode_mem++;
|
|
|
|
/* 4 bytes */
|
|
|
|
ucode_size -= 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
|
|
|
|
{
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
2017-04-04 23:40:13 +08:00
|
|
|
uint32_t reg;
|
2017-03-04 07:37:23 +08:00
|
|
|
|
2017-04-04 23:40:13 +08:00
|
|
|
reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;
|
|
|
|
WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg);
|
2017-03-04 07:37:23 +08:00
|
|
|
reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2));
|
2017-04-04 23:40:13 +08:00
|
|
|
return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
|
2017-03-04 07:37:23 +08:00
|
|
|
}
|