2021-08-02 16:59:33 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
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#define __SOC_MEDIATEK_MT8192_MMSYS_H
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#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
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#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
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#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
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#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
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#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
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#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
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#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
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#define MT8192_DISP_AAL0_SEL_IN 0xf38
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#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
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#define MT8192_DISP_DSI0_SEL_IN 0xf40
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#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
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#define MT8192_DISP_OVL0_GO_BLEND BIT(0)
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#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0)
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#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
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#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0)
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#define MT8192_DISP_OVL0_GO_BG BIT(1)
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#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2)
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#define MT8192_DISP_OVL0_2L_GO_BG BIT(3)
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#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
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#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4)
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#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
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#define MT8192_RDMA0_SOUT_COLOR0 0x1
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#define MT8192_CCORR0_SOUT_AAL0 0x1
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#define MT8192_AAL0_SEL_IN_CCORR0 0x1
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#define MT8192_DSI0_SEL_IN_DITHER0 0x1
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static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
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MT8192_OVL0_MOUT_EN_DISP_RDMA0
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}, {
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DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
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MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
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MT8192_OVL2_2L_MOUT_EN_RDMA4
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}, {
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2022-04-19 17:41:41 +08:00
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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2021-08-02 16:59:33 +08:00
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MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
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MT8192_DITHER0_MOUT_IN_DSI0
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
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MT8192_RDMA0_SEL_IN_OVL0_2L
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}, {
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DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
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MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
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MT8192_AAL0_SEL_IN_CCORR0
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}, {
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2022-04-19 17:41:41 +08:00
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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soc: mediatek: mt8192-mmsys: Fix dither to dsi0 path's input sel
In commit d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"),
the mmsys routing table for mt8192 was introduced but the input selector
for DITHER->DSI0 has no value assigned to it.
This means that we are clearing bit 0 instead of setting it, blocking
communication between these two blocks; due to that, any display that
is connected to DSI0 will not work, as no data will go through.
The effect of that issue is that, during bootup, the DRM will block for
some time, while atomically waiting for a vblank that never happens;
later, the situation doesn't get better, leaving the display in a
non-functional state.
To fix this issue, fix the route entry in the table by assigning the
dither input selector to MT8192_DISP_DSI0_SEL_IN.
Fixes: d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220128142056.359900-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-28 22:20:56 +08:00
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MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
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MT8192_DSI0_SEL_IN_DITHER0
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2021-08-02 16:59:33 +08:00
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
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MT8192_RDMA0_SOUT_COLOR0
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}, {
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DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
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MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
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MT8192_CCORR0_SOUT_AAL0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
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MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
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MT8192_DISP_OVL0_GO_BG
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
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MT8192_DISP_OVL0_2L_GO_BLEND
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}
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};
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#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
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