2010-03-19 12:47:10 +08:00
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/*
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* Header for the new SH dmaengine driver
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef SH_DMA_H
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#define SH_DMA_H
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#include <linux/list.h>
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#include <linux/dmaengine.h>
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/* Used by slave DMA clients to request DMA to/from a specific peripheral */
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struct sh_dmae_slave {
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unsigned int slave_id; /* Set by the platform */
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struct device *dma_dev; /* Set by the platform */
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2010-04-21 23:36:49 +08:00
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const struct sh_dmae_slave_config *config; /* Set by the driver */
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2010-03-19 12:47:10 +08:00
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};
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struct sh_dmae_regs {
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u32 sar; /* SAR / source address */
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u32 dar; /* DAR / destination address */
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u32 tcr; /* TCR / transfer count */
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};
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struct sh_desc {
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struct sh_dmae_regs hw;
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struct list_head node;
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struct dma_async_tx_descriptor async_tx;
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2011-10-14 01:04:23 +08:00
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enum dma_transfer_direction direction;
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2010-03-19 12:47:10 +08:00
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dma_cookie_t cookie;
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size_t partial;
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int chunks;
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int mark;
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};
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2010-04-21 23:36:49 +08:00
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2010-03-19 12:47:10 +08:00
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struct sh_dmae_slave_config {
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unsigned int slave_id;
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dma_addr_t addr;
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u32 chcr;
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char mid_rid;
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};
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struct sh_dmae_channel {
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unsigned int offset;
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unsigned int dmars;
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unsigned int dmars_bit;
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2012-01-04 22:34:17 +08:00
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unsigned int chclr_offset;
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2010-03-19 12:47:10 +08:00
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};
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struct sh_dmae_pdata {
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2010-04-21 23:36:49 +08:00
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const struct sh_dmae_slave_config *slave;
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2010-03-19 12:47:10 +08:00
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int slave_num;
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2010-04-21 23:36:49 +08:00
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const struct sh_dmae_channel *channel;
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2010-03-19 12:47:10 +08:00
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int channel_num;
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unsigned int ts_low_shift;
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unsigned int ts_low_mask;
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unsigned int ts_high_shift;
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unsigned int ts_high_mask;
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2010-04-21 23:36:49 +08:00
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const unsigned int *ts_shift;
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2010-03-19 12:47:10 +08:00
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int ts_shift_num;
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u16 dmaor_init;
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2011-06-17 16:20:40 +08:00
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unsigned int chcr_offset;
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2011-06-17 16:20:51 +08:00
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u32 chcr_ie_bit;
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2011-06-17 16:20:56 +08:00
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unsigned int dmaor_is_32bit:1;
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2011-06-17 16:21:05 +08:00
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unsigned int needs_tend_set:1;
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unsigned int no_dmars:1;
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2012-01-04 22:34:17 +08:00
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unsigned int chclr_present:1;
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2012-01-18 17:14:25 +08:00
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unsigned int slave_only:1;
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2010-03-19 12:47:10 +08:00
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};
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/* DMA register */
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#define SAR 0x00
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#define DAR 0x04
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#define TCR 0x08
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#define CHCR 0x0C
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#define DMAOR 0x40
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2011-06-17 16:21:05 +08:00
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#define TEND 0x18 /* USB-DMAC */
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2010-03-19 12:47:10 +08:00
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001
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/* Definitions for the SuperH DMAC */
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#define REQ_L 0x00000000
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#define REQ_E 0x00080000
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#define RACK_H 0x00000000
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#define RACK_L 0x00040000
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#define ACK_R 0x00000000
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#define ACK_W 0x00020000
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#define ACK_H 0x00000000
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#define ACK_L 0x00010000
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#define DM_INC 0x00004000
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#define DM_DEC 0x00008000
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#define DM_FIX 0x0000c000
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#define SM_INC 0x00001000
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#define SM_DEC 0x00002000
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#define SM_FIX 0x00003000
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#define RS_IN 0x00000200
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#define RS_OUT 0x00000300
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#define TS_BLK 0x00000040
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#define TM_BUR 0x00000020
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#define CHCR_DE 0x00000001
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#define CHCR_TE 0x00000002
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#define CHCR_IE 0x00000004
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#endif
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