42 lines
1.4 KiB
ReStructuredText
42 lines
1.4 KiB
ReStructuredText
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====================
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HugeTLBpage on ARM64
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====================
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Hugepage relies on making efficient use of TLBs to improve performance of
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address translations. The benefit depends on both -
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- the size of hugepages
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- size of entries supported by the TLBs
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The ARM64 port supports two flavours of hugepages.
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1) Block mappings at the pud/pmd level
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--------------------------------------
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These are regular hugepages where a pmd or a pud page table entry points to a
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block of memory. Regardless of the supported size of entries in TLB, block
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mappings reduce the depth of page table walk needed to translate hugepage
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addresses.
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2) Using the Contiguous bit
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---------------------------
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The architecture provides a contiguous bit in the translation table entries
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(D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
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contiguous set of entries that can be cached in a single TLB entry.
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The contiguous bit is used in Linux to increase the mapping size at the pmd and
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pte (last) level. The number of supported contiguous entries varies by page size
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and level of the page table.
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The following hugepage sizes are supported -
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====== ======== ==== ======== ===
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- CONT PTE PMD CONT PMD PUD
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====== ======== ==== ======== ===
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4K: 64K 2M 32M 1G
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16K: 2M 32M 1G
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64K: 2M 512M 16G
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====== ======== ==== ======== ===
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