84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _DM_PP_INTERFACE_
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#define _DM_PP_INTERFACE_
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#define PP_MAX_CLOCK_LEVELS 8
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struct pp_clock_with_latency {
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uint32_t clocks_in_khz;
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uint32_t latency_in_us;
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};
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struct pp_clock_levels_with_latency {
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uint32_t num_levels;
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struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS];
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};
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struct pp_clock_with_voltage {
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uint32_t clocks_in_khz;
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uint32_t voltage_in_mv;
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};
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struct pp_clock_levels_with_voltage {
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uint32_t num_levels;
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struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
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};
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#define PP_MAX_WM_SETS 4
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enum pp_wm_set_id {
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DC_WM_SET_A = 0,
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DC_WM_SET_B,
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DC_WM_SET_C,
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DC_WM_SET_D,
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DC_WM_SET_INVALID = 0xffff,
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};
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struct pp_wm_set_with_dmif_clock_range_soc15 {
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enum pp_wm_set_id wm_set_id;
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uint32_t wm_min_dcefclk_in_khz;
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uint32_t wm_max_dcefclk_in_khz;
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uint32_t wm_min_memclk_in_khz;
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uint32_t wm_max_memclk_in_khz;
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};
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struct pp_wm_set_with_mcif_clock_range_soc15 {
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enum pp_wm_set_id wm_set_id;
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uint32_t wm_min_socclk_in_khz;
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uint32_t wm_max_socclk_in_khz;
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uint32_t wm_min_memclk_in_khz;
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uint32_t wm_max_memclk_in_khz;
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};
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struct pp_wm_sets_with_clock_ranges_soc15 {
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uint32_t num_wm_sets_dmif;
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uint32_t num_wm_sets_mcif;
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struct pp_wm_set_with_dmif_clock_range_soc15
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wm_sets_dmif[PP_MAX_WM_SETS];
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struct pp_wm_set_with_mcif_clock_range_soc15
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wm_sets_mcif[PP_MAX_WM_SETS];
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};
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#endif /* _DM_PP_INTERFACE_ */
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