2019-06-04 16:11:33 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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2013-01-18 17:42:20 +08:00
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#
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# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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#
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config ARC
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def_bool y
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2016-11-01 04:46:38 +08:00
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select ARC_TIMERS
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mm/debug: add tests validating architecture page table helpers
This adds tests which will validate architecture page table helpers and
other accessors in their compliance with expected generic MM semantics.
This will help various architectures in validating changes to existing
page table helpers or addition of new ones.
This test covers basic page table entry transformations including but not
limited to old, young, dirty, clean, write, write protect etc at various
level along with populating intermediate entries with next page table page
and validating them.
Test page table pages are allocated from system memory with required size
and alignments. The mapped pfns at page table levels are derived from a
real pfn representing a valid kernel text symbol. This test gets called
via late_initcall().
This test gets built and run when CONFIG_DEBUG_VM_PGTABLE is selected.
Any architecture, which is willing to subscribe this test will need to
select ARCH_HAS_DEBUG_VM_PGTABLE. For now this is limited to arc, arm64,
x86, s390 and powerpc platforms where the test is known to build and run
successfully Going forward, other architectures too can subscribe the test
after fixing any build or runtime problems with their page table helpers.
Folks interested in making sure that a given platform's page table helpers
conform to expected generic MM semantics should enable the above config
which will just trigger this test during boot. Any non conformity here
will be reported as an warning which would need to be fixed. This test
will help catch any changes to the agreed upon semantics expected from
generic MM and enable platforms to accommodate it thereafter.
[anshuman.khandual@arm.com: v17]
Link: http://lkml.kernel.org/r/1587436495-22033-3-git-send-email-anshuman.khandual@arm.com
[anshuman.khandual@arm.com: v18]
Link: http://lkml.kernel.org/r/1588564865-31160-3-git-send-email-anshuman.khandual@arm.com
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Qian Cai <cai@lca.pw>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Tested-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> [s390]
Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> [ppc32]
Reviewed-by: Ingo Molnar <mingo@kernel.org>
Cc: Mike Rapoport <rppt@linux.ibm.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Kirill A. Shutemov <kirill@shutemov.name>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Link: http://lkml.kernel.org/r/1583919272-24178-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-06-05 07:47:15 +08:00
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select ARCH_HAS_DEBUG_VM_PGTABLE
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2019-06-14 22:26:41 +08:00
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select ARCH_HAS_DMA_PREP_COHERENT
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2018-08-17 01:20:33 +08:00
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select ARCH_HAS_PTE_SPECIAL
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2019-01-08 02:36:20 +08:00
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select ARCH_HAS_SETUP_DMA_OPS
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2018-05-18 21:41:32 +08:00
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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2015-08-08 20:21:58 +08:00
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select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
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32-bit userspace ABI: introduce ARCH_32BIT_OFF_T config option
All new 32-bit architectures should have 64-bit userspace off_t type, but
existing architectures has 32-bit ones.
To enforce the rule, new config option is added to arch/Kconfig that defaults
ARCH_32BIT_OFF_T to be disabled for new 32-bit architectures. All existing
32-bit architectures enable it explicitly.
New option affects force_o_largefile() behaviour. Namely, if userspace
off_t is 64-bits long, we have no reason to reject user to open big files.
Note that even if architectures has only 64-bit off_t in the kernel
(arc, c6x, h8300, hexagon, nios2, openrisc, and unicore32),
a libc may use 32-bit off_t, and therefore want to limit the file size
to 4GB unless specified differently in the open flags.
Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Yury Norov <ynorov@marvell.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-05-16 16:18:49 +08:00
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select ARCH_32BIT_OFF_T
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2019-12-04 08:46:31 +08:00
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select BUILDTIME_TABLE_SORT
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2013-01-18 17:42:18 +08:00
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select CLONE_BACKWARDS
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2016-01-14 14:50:08 +08:00
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select COMMON_CLK
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2019-06-14 22:26:41 +08:00
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select DMA_DIRECT_REMAP
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2015-07-27 19:53:28 +08:00
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select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
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2013-01-18 17:42:20 +08:00
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select GENERIC_CLOCKEVENTS
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select GENERIC_FIND_FIRST_BIT
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# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
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select GENERIC_IRQ_SHOW
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2016-03-11 04:44:13 +08:00
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select GENERIC_PCI_IOMAP
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2013-01-18 17:42:20 +08:00
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select GENERIC_PENDING_IRQ if SMP
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2018-11-19 19:29:17 +08:00
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select GENERIC_SCHED_CLOCK
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2013-01-18 17:42:20 +08:00
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select GENERIC_SMP_IDLE_THREAD
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2013-01-18 17:42:24 +08:00
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select HAVE_ARCH_KGDB
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2013-01-18 17:42:22 +08:00
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select HAVE_ARCH_TRACEHOOK
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2018-08-17 01:20:33 +08:00
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select HAVE_DEBUG_STACKOVERFLOW
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2019-11-19 23:26:15 +08:00
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select HAVE_DEBUG_KMEMLEAK
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2017-09-30 05:46:50 +08:00
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select HAVE_FUTEX_CMPXCHG if FUTEX
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2013-01-22 19:18:45 +08:00
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select HAVE_IOREMAP_PROT
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2018-08-17 01:20:33 +08:00
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select HAVE_KERNEL_GZIP
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select HAVE_KERNEL_LZMA
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2013-01-22 19:33:59 +08:00
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select HAVE_KPROBES
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select HAVE_KRETPROBES
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2017-01-17 02:48:09 +08:00
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select HAVE_MOD_ARCH_SPECIFIC
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2013-01-22 19:32:38 +08:00
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select HAVE_OPROFILE
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2013-01-18 17:42:24 +08:00
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select HAVE_PERF_EVENTS
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2016-01-01 17:42:54 +08:00
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select HANDLE_DOMAIN_IRQ
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2013-01-22 19:30:52 +08:00
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select IRQ_DOMAIN
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2013-01-18 17:42:20 +08:00
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select MODULES_USE_ELF_RELA
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2013-01-22 19:30:52 +08:00
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select OF
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select OF_EARLY_FLATTREE
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2018-11-16 03:05:34 +08:00
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select PCI_SYSCALL if PCI
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2016-09-29 02:53:17 +08:00
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select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
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2019-11-09 00:20:22 +08:00
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select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
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2020-09-03 22:22:35 +08:00
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select SET_FS
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2013-01-18 17:42:20 +08:00
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2018-07-26 21:15:43 +08:00
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config ARCH_HAS_CACHE_LINE_SIZE
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def_bool y
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2013-09-06 16:48:17 +08:00
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config TRACE_IRQFLAGS_SUPPORT
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def_bool y
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config LOCKDEP_SUPPORT
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def_bool y
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2013-01-18 17:42:20 +08:00
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config SCHED_OMIT_FRAME_POINTER
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def_bool y
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config GENERIC_CSUM
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def_bool y
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2016-04-18 13:19:56 +08:00
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config ARCH_DISCONTIGMEM_ENABLE
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2016-05-31 14:16:47 +08:00
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def_bool n
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2016-04-18 13:19:56 +08:00
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2013-01-18 17:42:20 +08:00
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config ARCH_FLATMEM_ENABLE
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def_bool y
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config MMU
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def_bool y
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2014-04-08 06:39:19 +08:00
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config NO_IOPORT_MAP
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2013-01-18 17:42:20 +08:00
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def_bool y
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config GENERIC_CALIBRATE_DELAY
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def_bool y
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config GENERIC_HWEIGHT
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def_bool y
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2013-01-18 17:42:23 +08:00
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config STACKTRACE_SUPPORT
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def_bool y
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select STACKTRACE
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2014-07-08 21:13:47 +08:00
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config HAVE_ARCH_TRANSPARENT_HUGEPAGE
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def_bool y
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depends on ARC_MMU_V4
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2013-01-18 17:42:20 +08:00
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menu "ARC Architecture Configuration"
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2013-01-22 19:21:50 +08:00
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menu "ARC Platform/SoC/Board"
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2013-01-18 17:42:20 +08:00
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2013-04-12 14:40:59 +08:00
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source "arch/arc/plat-tb10x/Kconfig"
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2014-01-27 21:51:34 +08:00
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source "arch/arc/plat-axs10x/Kconfig"
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2017-08-16 02:13:55 +08:00
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source "arch/arc/plat-hsdk/Kconfig"
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2013-01-22 19:21:50 +08:00
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2013-01-18 17:42:25 +08:00
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endmenu
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2013-01-18 17:42:20 +08:00
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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choice
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prompt "ARC Instruction Set"
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2018-11-30 20:51:56 +08:00
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default ISA_ARCV2
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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config ISA_ARCOMPACT
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bool "ARCompact ISA"
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lib/GCD.c: use binary GCD algorithm instead of Euclidean
The binary GCD algorithm is based on the following facts:
1. If a and b are all evens, then gcd(a,b) = 2 * gcd(a/2, b/2)
2. If a is even and b is odd, then gcd(a,b) = gcd(a/2, b)
3. If a and b are all odds, then gcd(a,b) = gcd((a-b)/2, b) = gcd((a+b)/2, b)
Even on x86 machines with reasonable division hardware, the binary
algorithm runs about 25% faster (80% the execution time) than the
division-based Euclidian algorithm.
On platforms like Alpha and ARMv6 where division is a function call to
emulation code, it's even more significant.
There are two variants of the code here, depending on whether a fast
__ffs (find least significant set bit) instruction is available. This
allows the unpredictable branches in the bit-at-a-time shifting loop to
be eliminated.
If fast __ffs is not available, the "even/odd" GCD variant is used.
I use the following code to benchmark:
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
#define swap(a, b) \
do { \
a ^= b; \
b ^= a; \
a ^= b; \
} while (0)
unsigned long gcd0(unsigned long a, unsigned long b)
{
unsigned long r;
if (a < b) {
swap(a, b);
}
if (b == 0)
return a;
while ((r = a % b) != 0) {
a = b;
b = r;
}
return b;
}
unsigned long gcd1(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
b >>= __builtin_ctzl(b);
for (;;) {
a >>= __builtin_ctzl(a);
if (a == b)
return a << __builtin_ctzl(r);
if (a < b)
swap(a, b);
a -= b;
}
}
unsigned long gcd2(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
r &= -r;
while (!(b & r))
b >>= 1;
for (;;) {
while (!(a & r))
a >>= 1;
if (a == b)
return a;
if (a < b)
swap(a, b);
a -= b;
a >>= 1;
if (a & r)
a += b;
a >>= 1;
}
}
unsigned long gcd3(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
b >>= __builtin_ctzl(b);
if (b == 1)
return r & -r;
for (;;) {
a >>= __builtin_ctzl(a);
if (a == 1)
return r & -r;
if (a == b)
return a << __builtin_ctzl(r);
if (a < b)
swap(a, b);
a -= b;
}
}
unsigned long gcd4(unsigned long a, unsigned long b)
{
unsigned long r = a | b;
if (!a || !b)
return r;
r &= -r;
while (!(b & r))
b >>= 1;
if (b == r)
return r;
for (;;) {
while (!(a & r))
a >>= 1;
if (a == r)
return r;
if (a == b)
return a;
if (a < b)
swap(a, b);
a -= b;
a >>= 1;
if (a & r)
a += b;
a >>= 1;
}
}
static unsigned long (*gcd_func[])(unsigned long a, unsigned long b) = {
gcd0, gcd1, gcd2, gcd3, gcd4,
};
#define TEST_ENTRIES (sizeof(gcd_func) / sizeof(gcd_func[0]))
#if defined(__x86_64__)
#define rdtscll(val) do { \
unsigned long __a,__d; \
__asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \
(val) = ((unsigned long long)__a) | (((unsigned long long)__d)<<32); \
} while(0)
static unsigned long long benchmark_gcd_func(unsigned long (*gcd)(unsigned long, unsigned long),
unsigned long a, unsigned long b, unsigned long *res)
{
unsigned long long start, end;
unsigned long long ret;
unsigned long gcd_res;
rdtscll(start);
gcd_res = gcd(a, b);
rdtscll(end);
if (end >= start)
ret = end - start;
else
ret = ~0ULL - start + 1 + end;
*res = gcd_res;
return ret;
}
#else
static inline struct timespec read_time(void)
{
struct timespec time;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &time);
return time;
}
static inline unsigned long long diff_time(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec - start.tv_nsec) < 0) {
temp.tv_sec = end.tv_sec - start.tv_sec - 1;
temp.tv_nsec = 1000000000ULL + end.tv_nsec - start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec - start.tv_sec;
temp.tv_nsec = end.tv_nsec - start.tv_nsec;
}
return temp.tv_sec * 1000000000ULL + temp.tv_nsec;
}
static unsigned long long benchmark_gcd_func(unsigned long (*gcd)(unsigned long, unsigned long),
unsigned long a, unsigned long b, unsigned long *res)
{
struct timespec start, end;
unsigned long gcd_res;
start = read_time();
gcd_res = gcd(a, b);
end = read_time();
*res = gcd_res;
return diff_time(start, end);
}
#endif
static inline unsigned long get_rand()
{
if (sizeof(long) == 8)
return (unsigned long)rand() << 32 | rand();
else
return rand();
}
int main(int argc, char **argv)
{
unsigned int seed = time(0);
int loops = 100;
int repeats = 1000;
unsigned long (*res)[TEST_ENTRIES];
unsigned long long elapsed[TEST_ENTRIES];
int i, j, k;
for (;;) {
int opt = getopt(argc, argv, "n:r:s:");
/* End condition always first */
if (opt == -1)
break;
switch (opt) {
case 'n':
loops = atoi(optarg);
break;
case 'r':
repeats = atoi(optarg);
break;
case 's':
seed = strtoul(optarg, NULL, 10);
break;
default:
/* You won't actually get here. */
break;
}
}
res = malloc(sizeof(unsigned long) * TEST_ENTRIES * loops);
memset(elapsed, 0, sizeof(elapsed));
srand(seed);
for (j = 0; j < loops; j++) {
unsigned long a = get_rand();
/* Do we have args? */
unsigned long b = argc > optind ? strtoul(argv[optind], NULL, 10) : get_rand();
unsigned long long min_elapsed[TEST_ENTRIES];
for (k = 0; k < repeats; k++) {
for (i = 0; i < TEST_ENTRIES; i++) {
unsigned long long tmp = benchmark_gcd_func(gcd_func[i], a, b, &res[j][i]);
if (k == 0 || min_elapsed[i] > tmp)
min_elapsed[i] = tmp;
}
}
for (i = 0; i < TEST_ENTRIES; i++)
elapsed[i] += min_elapsed[i];
}
for (i = 0; i < TEST_ENTRIES; i++)
printf("gcd%d: elapsed %llu\n", i, elapsed[i]);
k = 0;
srand(seed);
for (j = 0; j < loops; j++) {
unsigned long a = get_rand();
unsigned long b = argc > optind ? strtoul(argv[optind], NULL, 10) : get_rand();
for (i = 1; i < TEST_ENTRIES; i++) {
if (res[j][i] != res[j][0])
break;
}
if (i < TEST_ENTRIES) {
if (k == 0) {
k = 1;
fprintf(stderr, "Error:\n");
}
fprintf(stderr, "gcd(%lu, %lu): ", a, b);
for (i = 0; i < TEST_ENTRIES; i++)
fprintf(stderr, "%ld%s", res[j][i], i < TEST_ENTRIES - 1 ? ", " : "\n");
}
}
if (k == 0)
fprintf(stderr, "PASS\n");
free(res);
return 0;
}
Compiled with "-O2", on "VirtualBox 4.4.0-22-generic #38-Ubuntu x86_64" got:
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 10174
gcd1: elapsed 2120
gcd2: elapsed 2902
gcd3: elapsed 2039
gcd4: elapsed 2812
PASS
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 9309
gcd1: elapsed 2280
gcd2: elapsed 2822
gcd3: elapsed 2217
gcd4: elapsed 2710
PASS
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 9589
gcd1: elapsed 2098
gcd2: elapsed 2815
gcd3: elapsed 2030
gcd4: elapsed 2718
PASS
zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10
gcd0: elapsed 9914
gcd1: elapsed 2309
gcd2: elapsed 2779
gcd3: elapsed 2228
gcd4: elapsed 2709
PASS
[akpm@linux-foundation.org: avoid #defining a CONFIG_ variable]
Signed-off-by: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
Signed-off-by: George Spelvin <linux@horizon.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-21 08:03:57 +08:00
|
|
|
select CPU_NO_EFFICIENT_FFS
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
help
|
|
|
|
|
The original ARC ISA of ARC600/700 cores
|
|
|
|
|
|
2015-03-09 16:31:08 +08:00
|
|
|
config ISA_ARCV2
|
|
|
|
|
bool "ARC ISA v2"
|
2016-11-01 04:46:38 +08:00
|
|
|
select ARC_TIMERS_64BIT
|
2015-03-09 16:31:08 +08:00
|
|
|
help
|
|
|
|
|
ISA for the Next Generation ARC-HS cores
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
menu "ARC CPU Configuration"
|
|
|
|
|
|
|
|
|
|
choice
|
|
|
|
|
prompt "ARC Core"
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
default ARC_CPU_770 if ISA_ARCOMPACT
|
|
|
|
|
default ARC_CPU_HS if ISA_ARCV2
|
|
|
|
|
|
|
|
|
|
if ISA_ARCOMPACT
|
2013-01-18 17:42:20 +08:00
|
|
|
|
|
|
|
|
config ARC_CPU_750D
|
|
|
|
|
bool "ARC750D"
|
2015-06-26 15:12:53 +08:00
|
|
|
select ARC_CANT_LLSC
|
2013-01-18 17:42:20 +08:00
|
|
|
help
|
|
|
|
|
Support for ARC750 core
|
|
|
|
|
|
|
|
|
|
config ARC_CPU_770
|
|
|
|
|
bool "ARC770"
|
2013-11-07 17:17:16 +08:00
|
|
|
select ARC_HAS_SWAPE
|
2013-01-18 17:42:20 +08:00
|
|
|
help
|
|
|
|
|
Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
|
|
|
|
|
This core has a bunch of cool new features:
|
|
|
|
|
-MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
|
2019-03-11 21:57:59 +08:00
|
|
|
Shared Address Spaces (for sharing TLB entries in MMU)
|
2013-01-18 17:42:20 +08:00
|
|
|
-Caches: New Prog Model, Region Flush
|
|
|
|
|
-Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
|
|
|
|
|
|
2019-03-11 21:57:59 +08:00
|
|
|
endif #ISA_ARCOMPACT
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
|
|
|
|
|
config ARC_CPU_HS
|
|
|
|
|
bool "ARC-HS"
|
|
|
|
|
depends on ISA_ARCV2
|
|
|
|
|
help
|
|
|
|
|
Support for ARC HS38x Cores based on ARCv2 ISA
|
|
|
|
|
The notable features are:
|
2020-02-01 09:49:33 +08:00
|
|
|
- SMP configurations of up to 4 cores with coherency
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
- Optional L2 Cache and IO-Coherency
|
|
|
|
|
- Revised Interrupt Architecture (multiple priorites, reg banks,
|
|
|
|
|
auto stack switch, auto regfile save/restore)
|
|
|
|
|
- MMUv4 (PIPT dcache, Huge Pages)
|
|
|
|
|
- Instructions for
|
|
|
|
|
* 64bit load/store: LDD, STD
|
|
|
|
|
* Hardware assisted divide/remainder: DIV, REM
|
|
|
|
|
* Function prologue/epilogue: ENTER_S, LEAVE_S
|
|
|
|
|
* IRQ enable/disable: CLRI, SETI
|
|
|
|
|
* pop count: FFS, FLS
|
|
|
|
|
* SETcc, BMSKN, XBFU...
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
endchoice
|
|
|
|
|
|
2020-06-05 01:39:24 +08:00
|
|
|
config ARC_TUNE_MCPU
|
|
|
|
|
string "Override default -mcpu compiler flag"
|
|
|
|
|
default ""
|
|
|
|
|
help
|
|
|
|
|
Override default -mcpu=xxx compiler flag (which is set depending on
|
|
|
|
|
the ISA version) with the specified value.
|
|
|
|
|
NOTE: If specified flag isn't supported by current compiler the
|
|
|
|
|
ISA default value will be used as a fallback.
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
config CPU_BIG_ENDIAN
|
|
|
|
|
bool "Enable Big Endian Mode"
|
|
|
|
|
help
|
|
|
|
|
Build kernel for Big Endian Mode of ARC CPU
|
|
|
|
|
|
2013-01-18 17:42:23 +08:00
|
|
|
config SMP
|
2014-09-10 21:35:38 +08:00
|
|
|
bool "Symmetric Multi-Processing"
|
|
|
|
|
select ARC_MCIP if ISA_ARCV2
|
2013-01-18 17:42:23 +08:00
|
|
|
help
|
2014-09-10 21:35:38 +08:00
|
|
|
This enables support for systems with more than one CPU.
|
2013-01-18 17:42:23 +08:00
|
|
|
|
|
|
|
|
if SMP
|
|
|
|
|
|
|
|
|
|
config NR_CPUS
|
2013-06-03 20:19:59 +08:00
|
|
|
int "Maximum number of CPUs (2-4096)"
|
|
|
|
|
range 2 4096
|
2014-09-10 21:35:38 +08:00
|
|
|
default "4"
|
|
|
|
|
|
2015-10-09 13:56:12 +08:00
|
|
|
config ARC_SMP_HALT_ON_RESET
|
|
|
|
|
bool "Enable Halt-on-reset boot mode"
|
|
|
|
|
help
|
|
|
|
|
In SMP configuration cores can be configured as Halt-on-reset
|
|
|
|
|
or they could all start at same time. For Halt-on-reset, non
|
2020-02-01 09:49:33 +08:00
|
|
|
masters are parked until Master kicks them so they can start off
|
2015-10-09 13:56:12 +08:00
|
|
|
at designated entry point. For other case, all jump to common
|
|
|
|
|
entry point and spin wait for Master's signal.
|
|
|
|
|
|
2019-03-11 21:57:59 +08:00
|
|
|
endif #SMP
|
2013-01-18 17:42:23 +08:00
|
|
|
|
2016-09-30 01:00:14 +08:00
|
|
|
config ARC_MCIP
|
|
|
|
|
bool "ARConnect Multicore IP (MCIP) Support "
|
|
|
|
|
depends on ISA_ARCV2
|
|
|
|
|
default y if SMP
|
|
|
|
|
help
|
|
|
|
|
This IP block enables SMP in ARC-HS38 cores.
|
|
|
|
|
It provides for cross-core interrupts, multi-core debug
|
|
|
|
|
hardware semaphores, shared memory,....
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
menuconfig ARC_CACHE
|
|
|
|
|
bool "Enable Cache Support"
|
|
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
if ARC_CACHE
|
|
|
|
|
|
|
|
|
|
config ARC_CACHE_LINE_SHIFT
|
|
|
|
|
int "Cache Line Length (as power of 2)"
|
|
|
|
|
range 5 7
|
|
|
|
|
default "6"
|
|
|
|
|
help
|
|
|
|
|
Starting with ARC700 4.9, Cache line length is configurable,
|
|
|
|
|
This option specifies "N", with Line-len = 2 power N
|
|
|
|
|
So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
|
|
|
|
|
Linux only supports same line lengths for I and D caches.
|
|
|
|
|
|
|
|
|
|
config ARC_HAS_ICACHE
|
|
|
|
|
bool "Use Instruction Cache"
|
|
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
config ARC_HAS_DCACHE
|
|
|
|
|
bool "Use Data Cache"
|
|
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
config ARC_CACHE_PAGES
|
|
|
|
|
bool "Per Page Cache Control"
|
|
|
|
|
default y
|
|
|
|
|
depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
|
|
|
|
|
help
|
|
|
|
|
This can be used to over-ride the global I/D Cache Enable on a
|
|
|
|
|
per-page basis (but only for pages accessed via MMU such as
|
|
|
|
|
Kernel Virtual address or User Virtual Address)
|
|
|
|
|
TLB entries have a per-page Cache Enable Bit.
|
|
|
|
|
Note that Global I/D ENABLE + Per Page DISABLE works but corollary
|
|
|
|
|
Global DISABLE + Per Page ENABLE won't work
|
|
|
|
|
|
2013-05-10 00:24:51 +08:00
|
|
|
config ARC_CACHE_VIPT_ALIASING
|
|
|
|
|
bool "Support VIPT Aliasing D$"
|
2015-04-06 19:53:57 +08:00
|
|
|
depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
|
2013-05-10 00:24:51 +08:00
|
|
|
|
2019-03-11 21:57:59 +08:00
|
|
|
endif #ARC_CACHE
|
2013-01-18 17:42:20 +08:00
|
|
|
|
2013-01-18 17:42:25 +08:00
|
|
|
config ARC_HAS_ICCM
|
|
|
|
|
bool "Use ICCM"
|
|
|
|
|
help
|
|
|
|
|
Single Cycle RAMS to store Fast Path Code
|
|
|
|
|
|
|
|
|
|
config ARC_ICCM_SZ
|
|
|
|
|
int "ICCM Size in KB"
|
|
|
|
|
default "64"
|
|
|
|
|
depends on ARC_HAS_ICCM
|
|
|
|
|
|
|
|
|
|
config ARC_HAS_DCCM
|
|
|
|
|
bool "Use DCCM"
|
|
|
|
|
help
|
|
|
|
|
Single Cycle RAMS to store Fast Path Data
|
|
|
|
|
|
|
|
|
|
config ARC_DCCM_SZ
|
|
|
|
|
int "DCCM Size in KB"
|
|
|
|
|
default "64"
|
|
|
|
|
depends on ARC_HAS_DCCM
|
|
|
|
|
|
|
|
|
|
config ARC_DCCM_BASE
|
|
|
|
|
hex "DCCM map address"
|
|
|
|
|
default "0xA0000000"
|
|
|
|
|
depends on ARC_HAS_DCCM
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
choice
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
prompt "MMU Version"
|
2013-01-18 17:42:20 +08:00
|
|
|
default ARC_MMU_V3 if ARC_CPU_770
|
|
|
|
|
default ARC_MMU_V2 if ARC_CPU_750D
|
2015-04-06 19:52:39 +08:00
|
|
|
default ARC_MMU_V4 if ARC_CPU_HS
|
2013-01-18 17:42:20 +08:00
|
|
|
|
2015-09-29 18:31:13 +08:00
|
|
|
if ISA_ARCOMPACT
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
config ARC_MMU_V1
|
|
|
|
|
bool "MMU v1"
|
|
|
|
|
help
|
|
|
|
|
Orig ARC700 MMU
|
|
|
|
|
|
|
|
|
|
config ARC_MMU_V2
|
|
|
|
|
bool "MMU v2"
|
|
|
|
|
help
|
2017-09-26 11:47:59 +08:00
|
|
|
Fixed the deficiency of v1 - possible thrashing in memcpy scenario
|
2013-01-18 17:42:20 +08:00
|
|
|
when 2 D-TLB and 1 I-TLB entries index into same 2way set.
|
|
|
|
|
|
|
|
|
|
config ARC_MMU_V3
|
|
|
|
|
bool "MMU v3"
|
|
|
|
|
depends on ARC_CPU_770
|
|
|
|
|
help
|
|
|
|
|
Introduced with ARC700 4.10: New Features
|
|
|
|
|
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
|
|
|
|
|
Shared Address Spaces (SASID)
|
|
|
|
|
|
2015-09-29 18:31:13 +08:00
|
|
|
endif
|
|
|
|
|
|
2015-04-06 19:52:39 +08:00
|
|
|
config ARC_MMU_V4
|
|
|
|
|
bool "MMU v4"
|
|
|
|
|
depends on ISA_ARCV2
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
endchoice
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
choice
|
|
|
|
|
prompt "MMU Page Size"
|
|
|
|
|
default ARC_PAGE_SIZE_8K
|
|
|
|
|
|
|
|
|
|
config ARC_PAGE_SIZE_8K
|
|
|
|
|
bool "8KB"
|
|
|
|
|
help
|
|
|
|
|
Choose between 8k vs 16k
|
|
|
|
|
|
|
|
|
|
config ARC_PAGE_SIZE_16K
|
|
|
|
|
bool "16KB"
|
2015-07-17 02:45:17 +08:00
|
|
|
depends on ARC_MMU_V3 || ARC_MMU_V4
|
2013-01-18 17:42:20 +08:00
|
|
|
|
|
|
|
|
config ARC_PAGE_SIZE_4K
|
|
|
|
|
bool "4KB"
|
2015-07-17 02:45:17 +08:00
|
|
|
depends on ARC_MMU_V3 || ARC_MMU_V4
|
2013-01-18 17:42:20 +08:00
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2016-02-10 09:22:07 +08:00
|
|
|
choice
|
|
|
|
|
prompt "MMU Super Page Size"
|
|
|
|
|
depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
|
|
|
|
|
default ARC_HUGEPAGE_2M
|
|
|
|
|
|
|
|
|
|
config ARC_HUGEPAGE_2M
|
|
|
|
|
bool "2MB"
|
|
|
|
|
|
|
|
|
|
config ARC_HUGEPAGE_16M
|
|
|
|
|
bool "16MB"
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2016-04-18 13:19:56 +08:00
|
|
|
config NODES_SHIFT
|
|
|
|
|
int "Maximum NUMA Nodes (as a power of 2)"
|
2016-09-21 18:51:48 +08:00
|
|
|
default "0" if !DISCONTIGMEM
|
|
|
|
|
default "1" if DISCONTIGMEM
|
2016-04-18 13:19:56 +08:00
|
|
|
depends on NEED_MULTIPLE_NODES
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-04-18 13:19:56 +08:00
|
|
|
Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
|
|
|
|
|
zones.
|
|
|
|
|
|
2013-01-18 17:42:22 +08:00
|
|
|
config ARC_COMPACT_IRQ_LEVELS
|
2020-01-18 07:04:03 +08:00
|
|
|
depends on ISA_ARCOMPACT
|
2016-05-30 21:51:22 +08:00
|
|
|
bool "Setup Timer IRQ as high Priority"
|
2013-01-18 17:42:23 +08:00
|
|
|
# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
|
2016-05-30 21:51:22 +08:00
|
|
|
depends on !SMP
|
2013-01-18 17:42:22 +08:00
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
config ARC_FPU_SAVE_RESTORE
|
|
|
|
|
bool "Enable FPU state persistence across context switch"
|
|
|
|
|
help
|
2020-01-18 07:04:03 +08:00
|
|
|
ARCompact FPU has internal registers to assist with Double precision
|
|
|
|
|
Floating Point operations. There are control and stauts registers
|
|
|
|
|
for floating point exceptions and rounding modes. These are
|
|
|
|
|
preserved across task context switch when enabled.
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
|
2013-03-30 17:37:47 +08:00
|
|
|
config ARC_CANT_LLSC
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
config ARC_HAS_LLSC
|
|
|
|
|
bool "Insn: LLOCK/SCOND (efficient atomic ops)"
|
|
|
|
|
default y
|
2015-06-26 15:12:53 +08:00
|
|
|
depends on !ARC_CANT_LLSC
|
2013-01-18 17:42:20 +08:00
|
|
|
|
|
|
|
|
config ARC_HAS_SWAPE
|
|
|
|
|
bool "Insn: SWAPE (endian-swap)"
|
|
|
|
|
default y
|
|
|
|
|
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
if ISA_ARCV2
|
|
|
|
|
|
2019-01-31 00:32:41 +08:00
|
|
|
config ARC_USE_UNALIGNED_MEM_ACCESS
|
|
|
|
|
bool "Enable unaligned access in HW"
|
|
|
|
|
default y
|
|
|
|
|
select HAVE_EFFICIENT_UNALIGNED_ACCESS
|
|
|
|
|
help
|
|
|
|
|
The ARC HS architecture supports unaligned memory access
|
|
|
|
|
which is disabled by default. Enable unaligned access in
|
|
|
|
|
hardware and use software to use it
|
|
|
|
|
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
config ARC_HAS_LL64
|
|
|
|
|
bool "Insn: 64bit LDD/STD"
|
|
|
|
|
help
|
|
|
|
|
Enable gcc to generate 64-bit load/store instructions
|
|
|
|
|
ISA mandates even/odd registers to allow encoding of two
|
|
|
|
|
dest operands with 2 possible source operands.
|
|
|
|
|
default y
|
|
|
|
|
|
2015-07-17 02:45:38 +08:00
|
|
|
config ARC_HAS_DIV_REM
|
|
|
|
|
bool "Insn: div, divu, rem, remu"
|
|
|
|
|
default y
|
|
|
|
|
|
2017-04-21 06:36:51 +08:00
|
|
|
config ARC_HAS_ACCL_REGS
|
2020-03-06 04:02:50 +08:00
|
|
|
bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
|
2018-07-18 06:21:56 +08:00
|
|
|
default y
|
2017-04-21 06:36:51 +08:00
|
|
|
help
|
|
|
|
|
Depending on the configuration, CPU can contain accumulator reg-pair
|
|
|
|
|
(also referred to as r58:r59). These can also be used by gcc as GPR so
|
|
|
|
|
kernel needs to save/restore per process
|
|
|
|
|
|
2020-03-06 04:02:50 +08:00
|
|
|
config ARC_DSP_HANDLED
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2020-03-06 04:02:51 +08:00
|
|
|
config ARC_DSP_SAVE_RESTORE_REGS
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2020-03-06 04:02:50 +08:00
|
|
|
choice
|
|
|
|
|
prompt "DSP support"
|
|
|
|
|
default ARC_DSP_NONE
|
|
|
|
|
help
|
|
|
|
|
Depending on the configuration, CPU can contain DSP registers
|
|
|
|
|
(ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
|
|
|
|
|
Bellow is options describing how to handle these registers in
|
|
|
|
|
interrupt entry / exit and in context switch.
|
|
|
|
|
|
|
|
|
|
config ARC_DSP_NONE
|
|
|
|
|
bool "No DSP extension presence in HW"
|
|
|
|
|
help
|
|
|
|
|
No DSP extension presence in HW
|
|
|
|
|
|
|
|
|
|
config ARC_DSP_KERNEL
|
|
|
|
|
bool "DSP extension in HW, no support for userspace"
|
|
|
|
|
select ARC_HAS_ACCL_REGS
|
|
|
|
|
select ARC_DSP_HANDLED
|
|
|
|
|
help
|
|
|
|
|
DSP extension presence in HW, no support for DSP-enabled userspace
|
|
|
|
|
applications. We don't save / restore DSP registers and only do
|
|
|
|
|
some minimal preparations so userspace won't be able to break kernel
|
2020-03-06 04:02:51 +08:00
|
|
|
|
|
|
|
|
config ARC_DSP_USERSPACE
|
|
|
|
|
bool "Support DSP for userspace apps"
|
|
|
|
|
select ARC_HAS_ACCL_REGS
|
|
|
|
|
select ARC_DSP_HANDLED
|
|
|
|
|
select ARC_DSP_SAVE_RESTORE_REGS
|
|
|
|
|
help
|
|
|
|
|
DSP extension presence in HW, support save / restore DSP registers to
|
|
|
|
|
run DSP-enabled userspace applications
|
2020-03-06 04:02:52 +08:00
|
|
|
|
|
|
|
|
config ARC_DSP_AGU_USERSPACE
|
|
|
|
|
bool "Support DSP with AGU for userspace apps"
|
|
|
|
|
select ARC_HAS_ACCL_REGS
|
|
|
|
|
select ARC_DSP_HANDLED
|
|
|
|
|
select ARC_DSP_SAVE_RESTORE_REGS
|
|
|
|
|
help
|
|
|
|
|
DSP and AGU extensions presence in HW, support save / restore DSP
|
|
|
|
|
and AGU registers to run DSP-enabled userspace applications
|
2020-03-06 04:02:50 +08:00
|
|
|
endchoice
|
|
|
|
|
|
2018-06-07 01:20:37 +08:00
|
|
|
config ARC_IRQ_NO_AUTOSAVE
|
|
|
|
|
bool "Disable hardware autosave regfile on interrupts"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
On HS cores, taken interrupt auto saves the regfile on stack.
|
|
|
|
|
This is programmable and can be optionally disabled in which case
|
|
|
|
|
software INTERRUPT_PROLOGUE/EPILGUE do the needed work
|
|
|
|
|
|
2020-06-05 01:39:25 +08:00
|
|
|
config ARC_LPB_DISABLE
|
|
|
|
|
bool "Disable loop buffer (LPB)"
|
|
|
|
|
help
|
|
|
|
|
On HS cores, loop buffer (LPB) is programmable in runtime and can
|
|
|
|
|
be optionally disabled.
|
|
|
|
|
|
2019-03-11 21:57:59 +08:00
|
|
|
endif # ISA_ARCV2
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
endmenu # "ARC CPU Configuration"
|
|
|
|
|
|
|
|
|
|
config LINUX_LINK_BASE
|
2017-08-16 02:13:54 +08:00
|
|
|
hex "Kernel link address"
|
2013-01-18 17:42:20 +08:00
|
|
|
default "0x80000000"
|
|
|
|
|
help
|
|
|
|
|
ARC700 divides the 32 bit phy address space into two equal halves
|
|
|
|
|
-Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
|
|
|
|
|
-Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
|
|
|
|
|
Typically Linux kernel is linked at the start of untransalted addr,
|
|
|
|
|
hence the default value of 0x8zs.
|
|
|
|
|
However some customers have peripherals mapped at this addr, so
|
|
|
|
|
Linux needs to be scooted a bit.
|
|
|
|
|
If you don't know what the above means, leave this setting alone.
|
2015-12-15 16:27:16 +08:00
|
|
|
This needs to match memory start address specified in Device Tree
|
2013-01-18 17:42:20 +08:00
|
|
|
|
2017-08-16 02:13:54 +08:00
|
|
|
config LINUX_RAM_BASE
|
|
|
|
|
hex "RAM base address"
|
|
|
|
|
default LINUX_LINK_BASE
|
|
|
|
|
help
|
|
|
|
|
By default Linux is linked at base of RAM. However in some special
|
|
|
|
|
cases (such as HSDK), Linux can't be linked at start of DDR, hence
|
|
|
|
|
this option.
|
|
|
|
|
|
2015-03-09 21:23:49 +08:00
|
|
|
config HIGHMEM
|
|
|
|
|
bool "High Memory Support"
|
2016-05-31 14:16:47 +08:00
|
|
|
select ARCH_DISCONTIGMEM_ENABLE
|
2015-03-09 21:23:49 +08:00
|
|
|
help
|
|
|
|
|
With ARC 2G:2G address split, only upper 2G is directly addressable by
|
|
|
|
|
kernel. Enable this to potentially allow access to rest of 2G and PAE
|
|
|
|
|
in future
|
|
|
|
|
|
2015-02-06 23:44:57 +08:00
|
|
|
config ARC_HAS_PAE40
|
|
|
|
|
bool "Support for the 40-bit Physical Address Extension"
|
|
|
|
|
depends on ISA_ARCV2
|
2017-05-06 04:20:29 +08:00
|
|
|
select HIGHMEM
|
2018-04-03 22:24:20 +08:00
|
|
|
select PHYS_ADDR_T_64BIT
|
2015-02-06 23:44:57 +08:00
|
|
|
help
|
|
|
|
|
Enable access to physical memory beyond 4G, only supported on
|
|
|
|
|
ARC cores with 40 bit Physical Addressing support
|
|
|
|
|
|
2014-09-08 03:52:33 +08:00
|
|
|
config ARC_KVADDR_SIZE
|
2017-09-26 11:47:59 +08:00
|
|
|
int "Kernel Virtual Address Space size (MB)"
|
2014-09-08 03:52:33 +08:00
|
|
|
range 0 512
|
|
|
|
|
default "256"
|
|
|
|
|
help
|
|
|
|
|
The kernel address space is carved out of 256MB of translated address
|
|
|
|
|
space for catering to vmalloc, modules, pkmap, fixmap. This however may
|
|
|
|
|
not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
|
|
|
|
|
this to be stretched to 512 MB (by extending into the reserved
|
|
|
|
|
kernel-user gutter)
|
|
|
|
|
|
2013-02-11 22:22:57 +08:00
|
|
|
config ARC_CURR_IN_REG
|
|
|
|
|
bool "Dedicate Register r25 for current_task pointer"
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
This reserved Register R25 to point to Current Task in
|
|
|
|
|
kernel mode. This saves memory access for each such access
|
|
|
|
|
|
2013-01-23 19:00:36 +08:00
|
|
|
|
2014-09-08 13:48:15 +08:00
|
|
|
config ARC_EMUL_UNALIGNED
|
2013-01-23 19:00:36 +08:00
|
|
|
bool "Emulate unaligned memory access (userspace only)"
|
|
|
|
|
select SYSCTL_ARCH_UNALIGN_NO_WARN
|
|
|
|
|
select SYSCTL_ARCH_UNALIGN_ALLOW
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
|
|
depends on ISA_ARCOMPACT
|
2013-01-23 19:00:36 +08:00
|
|
|
help
|
|
|
|
|
This enables misaligned 16 & 32 bit memory access from user space.
|
|
|
|
|
Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
|
|
|
|
|
potential bugs in code
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
config HZ
|
|
|
|
|
int "Timer Frequency"
|
|
|
|
|
default 100
|
|
|
|
|
|
2013-01-18 17:42:25 +08:00
|
|
|
config ARC_METAWARE_HLINK
|
|
|
|
|
bool "Support for Metaware debugger assisted Host access"
|
|
|
|
|
help
|
|
|
|
|
This options allows a Linux userland apps to directly access
|
|
|
|
|
host file system (open/creat/read/write etc) with help from
|
|
|
|
|
Metaware Debugger. This can come in handy for Linux-host communication
|
|
|
|
|
when there is no real usable peripheral such as EMAC.
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
menuconfig ARC_DBG
|
|
|
|
|
bool "ARC debugging"
|
|
|
|
|
default y
|
|
|
|
|
|
2014-11-07 13:15:28 +08:00
|
|
|
if ARC_DBG
|
|
|
|
|
|
2013-01-22 19:33:19 +08:00
|
|
|
config ARC_DW2_UNWIND
|
|
|
|
|
bool "Enable DWARF specific kernel stack unwind"
|
|
|
|
|
default y
|
|
|
|
|
select KALLSYMS
|
|
|
|
|
help
|
|
|
|
|
Compiles the kernel with DWARF unwind information and can be used
|
|
|
|
|
to get stack backtraces.
|
|
|
|
|
|
|
|
|
|
If you say Y here the resulting kernel image will be slightly larger
|
|
|
|
|
but not slower, and it will give very useful debugging information.
|
|
|
|
|
If you don't debug the kernel, you can say N, but we may not be able
|
|
|
|
|
to solve problems without frame unwind information
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
config ARC_DBG_TLB_PARANOIA
|
|
|
|
|
bool "Paranoia Checks in Low Level TLB Handlers"
|
|
|
|
|
|
2019-11-09 00:20:22 +08:00
|
|
|
config ARC_DBG_JUMP_LABEL
|
|
|
|
|
bool "Paranoid checks in Static Keys (jump labels) code"
|
|
|
|
|
depends on JUMP_LABEL
|
|
|
|
|
default y if STATIC_KEYS_SELFTEST
|
|
|
|
|
help
|
|
|
|
|
Enable paranoid checks and self-test of both ARC-specific and generic
|
|
|
|
|
part of static keys (jump labels) related code.
|
2014-11-07 13:15:28 +08:00
|
|
|
endif
|
|
|
|
|
|
2013-01-22 19:30:52 +08:00
|
|
|
config ARC_BUILTIN_DTB_NAME
|
|
|
|
|
string "Built in DTB"
|
|
|
|
|
help
|
|
|
|
|
Set the name of the DTB to embed in the vmlinux binary
|
|
|
|
|
Leaving it blank selects the minimal "skeleton" dtb
|
|
|
|
|
|
2013-01-18 17:42:20 +08:00
|
|
|
endmenu # "ARC Architecture Configuration"
|
|
|
|
|
|
2016-02-10 09:22:07 +08:00
|
|
|
config FORCE_MAX_ZONEORDER
|
|
|
|
|
int "Maximum zone order"
|
|
|
|
|
default "12" if ARC_HUGEPAGE_16M
|
|
|
|
|
default "11"
|
|
|
|
|
|
2014-10-29 20:26:25 +08:00
|
|
|
source "kernel/power/Kconfig"
|