ARC: Fundamental ARCH data-types/defines
* L1_CACHE_SHIFT
* PAGE_SIZE, PAGE_OFFSET
* struct pt_regs, struct user_regs_struct
* struct thread_struct, cpu_relax(), task_pt_regs(), start_thread(), ...
* struct thread_info, THREAD_SIZE, INIT_THREAD_INFO(), TIF_*, ...
* BUG()
* ELF_*
* Elf_*
To disallow user-space visibility into some of the core kernel data-types
such as struct pt_regs, #ifdef __KERNEL__ which also makes the UAPI header
spit (further patch in the series) to NOT export it to asm/uapi/ptrace.h
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Jonas Bonn <jonas.bonn@gmail.com>
Cc: Al Viro <viro@ZenIV.linux.org.uk>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2013-01-18 17:42:17 +08:00
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARC_ASM_CACHE_H
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#define __ARC_ASM_CACHE_H
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/* In case $$ not config, setup a dummy number for rest of kernel */
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#ifndef CONFIG_ARC_CACHE_LINE_SHIFT
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#define L1_CACHE_SHIFT 6
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#else
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#define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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2013-09-05 15:47:49 +08:00
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#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))
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2013-01-18 17:42:19 +08:00
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2013-05-14 15:58:17 +08:00
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/*
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2014-09-19 03:58:24 +08:00
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* ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
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2013-05-14 15:58:17 +08:00
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* Ideal for wiring memory mapped peripherals as we don't need to do
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* explicit uncached accesses (LD.di/ST.di) hence more portable drivers
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*/
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#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
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2013-01-18 17:42:19 +08:00
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#ifndef __ASSEMBLY__
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/* Uncached access macros */
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#define arc_read_uncached_32(ptr) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__( \
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" ld.di %0, [%1] \n" \
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: "=r"(__ret) \
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: "r"(ptr)); \
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__ret; \
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})
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#define arc_write_uncached_32(ptr, data)\
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({ \
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__asm__ __volatile__( \
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" st.di %0, [%1] \n" \
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: \
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: "r"(data), "r"(ptr)); \
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})
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2017-07-18 22:31:24 +08:00
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/* Largest line length for either L1 or L2 is 128 bytes */
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2018-07-26 21:15:43 +08:00
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#define SMP_CACHE_BYTES 128
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#define cache_line_size() SMP_CACHE_BYTES
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#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES
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2013-01-18 17:42:19 +08:00
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2019-02-08 18:55:19 +08:00
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/*
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* Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
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* ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
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* alignment for any atomic64_t embedded in buffer.
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* Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
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* value of 4 (and not 8) in ARC ABI.
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*/
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#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
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#define ARCH_SLAB_MINALIGN 8
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#endif
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2013-01-18 17:42:19 +08:00
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extern void arc_cache_init(void);
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extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
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2013-09-05 21:49:06 +08:00
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extern void read_decode_cache_bcr(void);
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2013-05-14 15:58:17 +08:00
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2016-10-14 06:58:59 +08:00
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extern int ioc_enable;
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2016-08-27 06:41:29 +08:00
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extern unsigned long perip_base, perip_end;
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2015-05-26 00:54:28 +08:00
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2013-05-14 15:58:17 +08:00
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#endif /* !__ASSEMBLY__ */
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2013-01-18 17:42:19 +08:00
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2014-03-07 20:38:11 +08:00
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/* Instruction cache related Auxiliary registers */
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#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
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#define ARC_REG_IC_IVIC 0x10
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#define ARC_REG_IC_CTRL 0x11
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2014-08-29 13:25:15 +08:00
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#define ARC_REG_IC_IVIR 0x16
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#define ARC_REG_IC_ENDR 0x17
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2014-03-07 20:38:11 +08:00
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#define ARC_REG_IC_IVIL 0x19
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#define ARC_REG_IC_PTAG 0x1E
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2015-02-06 23:44:57 +08:00
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#define ARC_REG_IC_PTAG_HI 0x1F
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2014-03-07 20:38:11 +08:00
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/* Bit val in IC_CTRL */
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2016-06-22 18:31:19 +08:00
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#define IC_CTRL_DIS 0x1
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2014-03-07 20:38:11 +08:00
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/* Data cache related Auxiliary registers */
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#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
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#define ARC_REG_DC_IVDC 0x47
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#define ARC_REG_DC_CTRL 0x48
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#define ARC_REG_DC_IVDL 0x4A
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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2014-08-29 13:25:15 +08:00
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#define ARC_REG_DC_STARTR 0x4D
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#define ARC_REG_DC_ENDR 0x4E
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2014-03-07 20:38:11 +08:00
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#define ARC_REG_DC_PTAG 0x5C
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2015-02-06 23:44:57 +08:00
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#define ARC_REG_DC_PTAG_HI 0x5F
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2014-03-07 20:38:11 +08:00
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/* Bit val in DC_CTRL */
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2016-06-22 18:31:19 +08:00
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#define DC_CTRL_DIS 0x001
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#define DC_CTRL_INV_MODE_FLUSH 0x040
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#define DC_CTRL_FLUSH_STATUS 0x100
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2014-08-29 13:25:15 +08:00
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#define DC_CTRL_RGN_OP_INV 0x200
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ARCv2: mm: micro-optimize region flush generated code
DC_CTRL.RGN_OP is 3 bits wide, however only 1 bit is used in current
programming model (0: flush, 1: invalidate)
The current code targetting 3 bits leads to additional 8 byte AND
operation which can be elided given that only 1 bit is ever set by
software and/or looked at by hardware
before
------
| 80b63324 <__dma_cache_wback_inv_l1>:
| 80b63324: clri r3
| 80b63328: lr r2,[dc_ctrl]
| 80b6332c: and r2,r2,0xfffff1ff <--- 8 bytes insn
| 80b63334: or r2,r2,576
| 80b63338: sr r2,[dc_ctrl]
| ...
| ...
| 80b63360 <__dma_cache_inv_l1>:
| 80b63360: clri r3
| 80b63364: lr r2,[dc_ctrl]
| 80b63368: and r2,r2,0xfffff1ff <--- 8 bytes insn
| 80b63370: bset_s r2,r2,0x9
| 80b63372: sr r2,[dc_ctrl]
| ...
| ...
| 80b6338c <__dma_cache_wback_l1>:
| 80b6338c: clri r3
| 80b63390: lr r2,[dc_ctrl]
| 80b63394: and r2,r2,0xfffff1ff <--- 8 bytes insn
| 80b6339c: sr r2,[dc_ctrl]
after (AND elided totally in 2 cases, replaced with 2 byte BCLR in 3rd)
-----
| 80b63324 <__dma_cache_wback_inv_l1>:
| 80b63324: clri r3
| 80b63328: lr r2,[dc_ctrl]
| 80b6332c: or r2,r2,576
| 80b63330: sr r2,[dc_ctrl]
| ...
| ...
| 80b63358 <__dma_cache_inv_l1>:
| 80b63358: clri r3
| 80b6335c: lr r2,[dc_ctrl]
| 80b63360: bset_s r2,r2,0x9
| 80b63362: sr r2,[dc_ctrl]
| ...
| ...
| 80b6337c <__dma_cache_wback_l1>:
| 80b6337c: clri r3
| 80b63380: lr r2,[dc_ctrl]
| 80b63384: bclr_s r2,r2,0x9
| 80b63386: sr r2,[dc_ctrl]
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-05-03 07:23:57 +08:00
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#define DC_CTRL_RGN_OP_MSK 0x200
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2014-03-07 20:38:11 +08:00
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2015-04-06 19:53:57 +08:00
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/*System-level cache (L2 cache) related Auxiliary registers */
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#define ARC_REG_SLC_CFG 0x901
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2015-04-03 17:37:07 +08:00
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#define ARC_REG_SLC_CTRL 0x903
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#define ARC_REG_SLC_FLUSH 0x904
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#define ARC_REG_SLC_INVALIDATE 0x905
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2017-08-01 12:53:27 +08:00
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#define ARC_AUX_SLC_IVDL 0x910
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#define ARC_AUX_SLC_FLDL 0x912
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2015-04-03 17:37:07 +08:00
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#define ARC_REG_SLC_RGN_START 0x914
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2017-08-01 17:58:47 +08:00
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#define ARC_REG_SLC_RGN_START1 0x915
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2015-04-03 17:37:07 +08:00
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#define ARC_REG_SLC_RGN_END 0x916
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2017-08-01 17:58:47 +08:00
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#define ARC_REG_SLC_RGN_END1 0x917
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2015-04-03 17:37:07 +08:00
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/* Bit val in SLC_CONTROL */
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2016-06-22 18:13:22 +08:00
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#define SLC_CTRL_DIS 0x001
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2015-04-03 17:37:07 +08:00
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#define SLC_CTRL_IM 0x040
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#define SLC_CTRL_BUSY 0x100
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#define SLC_CTRL_RGN_OP_INV 0x200
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2015-04-06 19:53:57 +08:00
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2015-05-26 00:54:28 +08:00
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/* IO coherency related Auxiliary registers */
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#define ARC_REG_IO_COH_ENABLE 0x500
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2018-10-04 21:12:12 +08:00
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#define ARC_IO_COH_ENABLE_BIT BIT(0)
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2015-05-26 00:54:28 +08:00
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#define ARC_REG_IO_COH_PARTIAL 0x501
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2018-10-04 21:12:12 +08:00
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#define ARC_IO_COH_PARTIAL_BIT BIT(0)
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2015-05-26 00:54:28 +08:00
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#define ARC_REG_IO_COH_AP0_BASE 0x508
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#define ARC_REG_IO_COH_AP0_SIZE 0x509
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ARC: Fundamental ARCH data-types/defines
* L1_CACHE_SHIFT
* PAGE_SIZE, PAGE_OFFSET
* struct pt_regs, struct user_regs_struct
* struct thread_struct, cpu_relax(), task_pt_regs(), start_thread(), ...
* struct thread_info, THREAD_SIZE, INIT_THREAD_INFO(), TIF_*, ...
* BUG()
* ELF_*
* Elf_*
To disallow user-space visibility into some of the core kernel data-types
such as struct pt_regs, #ifdef __KERNEL__ which also makes the UAPI header
spit (further patch in the series) to NOT export it to asm/uapi/ptrace.h
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Jonas Bonn <jonas.bonn@gmail.com>
Cc: Al Viro <viro@ZenIV.linux.org.uk>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2013-01-18 17:42:17 +08:00
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#endif /* _ASM_CACHE_H */
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