2006-01-15 06:57:39 +08:00
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#
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# Makefile for the PowerPC 85xx linux kernel.
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#
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2008-11-19 23:35:56 +08:00
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obj-$(CONFIG_SMP) += smp.o
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2011-11-24 15:07:08 +08:00
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obj-y += common.o
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2011-11-18 01:56:16 +08:00
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powerpc/85xx: Add BSC9131 RDB Support
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The
BSC9131 is integrated SoC that targets Femto base station market. It
combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte
shared L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel
Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE
UP/DL Channel processing, and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix
Inversion operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit
with ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network
acceleration including IEEE 1588. v2 hardware support and
virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single
port) and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD
support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
BSC9131RDB Overview
----------------------
BSC9131 SoC
1Gbyte DDR3 (on board DDR)
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
USB-ULPI
eTSEC1: Connected to RGMII PHY
eTSEC2: Connected to RGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
Linux runs on e500v2 core and access some DSP peripherals like AIC
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-22 12:54:15 +08:00
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obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
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2006-02-11 07:01:06 +08:00
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obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
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2006-09-22 02:31:26 +08:00
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obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
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2006-04-03 06:42:40 +08:00
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obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
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2008-07-02 14:36:15 +08:00
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obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
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2007-08-17 22:22:09 +08:00
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obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
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2007-02-18 06:29:36 +08:00
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obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
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2009-08-07 23:35:16 +08:00
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obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
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2011-06-03 04:28:08 +08:00
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obj-$(CONFIG_P1010_RDB) += p1010rdb.o
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2010-07-03 06:25:03 +08:00
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obj-$(CONFIG_P1022_DS) += p1022_ds.o
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2011-05-20 09:20:13 +08:00
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obj-$(CONFIG_P1023_RDS) += p1023_rds.o
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2011-08-26 18:45:03 +08:00
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obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
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2010-10-08 03:47:10 +08:00
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obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
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2009-10-23 05:35:07 +08:00
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obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
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2010-10-08 03:05:47 +08:00
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obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
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powerpc/85xx: Add support for P5040DS board
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-26 23:08:54 +08:00
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obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
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2008-01-24 13:42:44 +08:00
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obj-$(CONFIG_STX_GP3) += stx_gp3.o
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2008-01-25 13:53:03 +08:00
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obj-$(CONFIG_TQM85xx) += tqm85xx.o
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2008-01-25 07:41:27 +08:00
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obj-$(CONFIG_SBC8548) += sbc8548.o
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powerpc/85xx: Add support for the "socrates" board (MPC8544).
Supported are Ethernet, serial console, I2C, I2C-based RTC and
temperature sensors, NOR and NAND flash, PCI, USB, CAN and Lime
display controller.
The multiplexing of FPGA interrupts onto PowerPC interrupt lines is
supported through our own fpga_pic interrupt controller driver.
For example the SJA1000 controller is level low sensitive connected to
fpga_pic line 2 and is routed to the second (of three) irq lines to
the CPU:
can@3,100 {
compatible = "philips,sja1000";
reg = <3 0x100 0x80>;
interrupts = <2 2>;
interrupts = <2 8 1>; // number, type, routing
interrupt-parent = <&fpga_pic>;
};
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-22 21:58:43 +08:00
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obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
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2008-03-06 23:17:16 +08:00
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obj-$(CONFIG_KSI8560) += ksi8560.o
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2009-08-07 23:35:16 +08:00
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obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
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2012-03-13 01:13:00 +08:00
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obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
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2012-07-11 08:26:48 +08:00
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obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
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