2019-01-12 01:54:06 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Panel driver for the TPO TPG110 400CH LTPS TFT LCD Single Chip
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* Digital Driver.
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*
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* This chip drives a TFT LCD, so it does not know what kind of
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* display is actually connected to it, so the width and height of that
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* display needs to be supplied from the machine configuration.
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*
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* Author:
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* Linus Walleij <linus.walleij@linaro.org>
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*/
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_print.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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2019-12-07 22:03:53 +08:00
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#include <linux/of.h>
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2019-01-12 01:54:06 +08:00
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#define TPG110_TEST 0x00
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#define TPG110_CHIPID 0x01
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#define TPG110_CTRL1 0x02
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#define TPG110_RES_MASK GENMASK(2, 0)
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#define TPG110_RES_800X480 0x07
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#define TPG110_RES_640X480 0x06
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#define TPG110_RES_480X272 0x05
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#define TPG110_RES_480X640 0x04
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#define TPG110_RES_480X272_D 0x01 /* Dual scan: outputs 800x480 */
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#define TPG110_RES_400X240_D 0x00 /* Dual scan: outputs 800x480 */
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#define TPG110_CTRL2 0x03
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#define TPG110_CTRL2_PM BIT(0)
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#define TPG110_CTRL2_RES_PM_CTRL BIT(7)
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/**
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* struct tpg110_panel_mode - lookup struct for the supported modes
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*/
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struct tpg110_panel_mode {
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/**
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* @name: the name of this panel
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*/
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const char *name;
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/**
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* @magic: the magic value from the detection register
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*/
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u32 magic;
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/**
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* @mode: the DRM display mode for this panel
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*/
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struct drm_display_mode mode;
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/**
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* @bus_flags: the DRM bus flags for this panel e.g. inverted clock
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*/
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u32 bus_flags;
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};
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/**
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* struct tpg110 - state container for the TPG110 panel
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*/
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struct tpg110 {
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/**
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* @dev: the container device
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*/
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struct device *dev;
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/**
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* @spi: the corresponding SPI device
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*/
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struct spi_device *spi;
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/**
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* @panel: the DRM panel instance for this device
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*/
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struct drm_panel panel;
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/**
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* @panel_type: the panel mode as detected
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*/
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const struct tpg110_panel_mode *panel_mode;
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/**
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* @width: the width of this panel in mm
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*/
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u32 width;
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/**
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* @height: the height of this panel in mm
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*/
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u32 height;
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/**
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* @grestb: reset GPIO line
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*/
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struct gpio_desc *grestb;
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};
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/*
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* TPG110 modes, these are the simple modes, the dualscan modes that
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* take 400x240 or 480x272 in and display as 800x480 are not listed.
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*/
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static const struct tpg110_panel_mode tpg110_modes[] = {
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{
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.name = "800x480 RGB",
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.magic = TPG110_RES_800X480,
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.mode = {
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.clock = 33200,
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.hdisplay = 800,
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.hsync_start = 800 + 40,
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.hsync_end = 800 + 40 + 1,
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.htotal = 800 + 40 + 1 + 216,
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.vdisplay = 480,
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.vsync_start = 480 + 10,
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.vsync_end = 480 + 10 + 1,
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.vtotal = 480 + 10 + 1 + 35,
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.vrefresh = 60,
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},
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2018-09-22 20:02:42 +08:00
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.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
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2019-01-12 01:54:06 +08:00
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},
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{
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.name = "640x480 RGB",
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.magic = TPG110_RES_640X480,
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.mode = {
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.clock = 25200,
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.hdisplay = 640,
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.hsync_start = 640 + 24,
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.hsync_end = 640 + 24 + 1,
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.htotal = 640 + 24 + 1 + 136,
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.vdisplay = 480,
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.vsync_start = 480 + 18,
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.vsync_end = 480 + 18 + 1,
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.vtotal = 480 + 18 + 1 + 27,
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.vrefresh = 60,
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},
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2018-09-22 20:02:42 +08:00
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.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
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2019-01-12 01:54:06 +08:00
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},
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{
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.name = "480x272 RGB",
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.magic = TPG110_RES_480X272,
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.mode = {
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.clock = 9000,
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.hdisplay = 480,
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.hsync_start = 480 + 2,
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.hsync_end = 480 + 2 + 1,
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.htotal = 480 + 2 + 1 + 43,
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.vdisplay = 272,
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.vsync_start = 272 + 2,
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.vsync_end = 272 + 2 + 1,
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.vtotal = 272 + 2 + 1 + 12,
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.vrefresh = 60,
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},
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2018-09-22 20:02:42 +08:00
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.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
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2019-01-12 01:54:06 +08:00
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},
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{
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.name = "480x640 RGB",
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.magic = TPG110_RES_480X640,
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.mode = {
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.clock = 20500,
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.hdisplay = 480,
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.hsync_start = 480 + 2,
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.hsync_end = 480 + 2 + 1,
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.htotal = 480 + 2 + 1 + 43,
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.vdisplay = 640,
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.vsync_start = 640 + 4,
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.vsync_end = 640 + 4 + 1,
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.vtotal = 640 + 4 + 1 + 8,
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.vrefresh = 60,
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},
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2018-09-22 20:02:42 +08:00
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.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
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2019-01-12 01:54:06 +08:00
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},
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{
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.name = "400x240 RGB",
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.magic = TPG110_RES_400X240_D,
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.mode = {
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.clock = 8300,
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.hdisplay = 400,
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.hsync_start = 400 + 20,
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.hsync_end = 400 + 20 + 1,
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.htotal = 400 + 20 + 1 + 108,
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.vdisplay = 240,
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.vsync_start = 240 + 2,
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.vsync_end = 240 + 2 + 1,
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.vtotal = 240 + 2 + 1 + 20,
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.vrefresh = 60,
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},
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2018-09-22 20:02:42 +08:00
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.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
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2019-01-12 01:54:06 +08:00
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},
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};
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static inline struct tpg110 *
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to_tpg110(struct drm_panel *panel)
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{
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return container_of(panel, struct tpg110, panel);
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}
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static u8 tpg110_readwrite_reg(struct tpg110 *tpg, bool write,
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u8 address, u8 outval)
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{
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struct spi_message m;
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struct spi_transfer t[2];
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u8 buf[2];
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int ret;
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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if (write) {
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/*
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* Clear address bit 0, 1 when writing, just to be sure
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* The actual bit indicating a write here is bit 1, bit
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* 0 is just surplus to pad it up to 8 bits.
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*/
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buf[0] = address << 2;
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buf[0] &= ~0x03;
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buf[1] = outval;
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t[0].bits_per_word = 8;
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t[0].tx_buf = &buf[0];
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t[0].len = 1;
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t[1].tx_buf = &buf[1];
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t[1].len = 1;
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t[1].bits_per_word = 8;
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} else {
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/* Set address bit 0 to 1 to read */
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buf[0] = address << 1;
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buf[0] |= 0x01;
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/*
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* The last bit/clock is Hi-Z turnaround cycle, so we need
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* to send only 7 bits here. The 8th bit is the high impedance
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* turn-around cycle.
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*/
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t[0].bits_per_word = 7;
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t[0].tx_buf = &buf[0];
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t[0].len = 1;
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t[1].rx_buf = &buf[1];
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t[1].len = 1;
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t[1].bits_per_word = 8;
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}
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spi_message_add_tail(&t[0], &m);
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spi_message_add_tail(&t[1], &m);
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ret = spi_sync(tpg->spi, &m);
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if (ret) {
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DRM_DEV_ERROR(tpg->dev, "SPI message error %d\n", ret);
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return ret;
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}
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if (write)
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return 0;
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/* Read */
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return buf[1];
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}
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static u8 tpg110_read_reg(struct tpg110 *tpg, u8 address)
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{
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return tpg110_readwrite_reg(tpg, false, address, 0);
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}
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static void tpg110_write_reg(struct tpg110 *tpg, u8 address, u8 outval)
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{
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tpg110_readwrite_reg(tpg, true, address, outval);
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}
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static int tpg110_startup(struct tpg110 *tpg)
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{
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u8 val;
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int i;
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/* De-assert the reset signal */
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gpiod_set_value_cansleep(tpg->grestb, 0);
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usleep_range(1000, 2000);
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DRM_DEV_DEBUG(tpg->dev, "de-asserted GRESTB\n");
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/* Test display communication */
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tpg110_write_reg(tpg, TPG110_TEST, 0x55);
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val = tpg110_read_reg(tpg, TPG110_TEST);
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if (val != 0x55) {
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DRM_DEV_ERROR(tpg->dev, "failed communication test\n");
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return -ENODEV;
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}
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val = tpg110_read_reg(tpg, TPG110_CHIPID);
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DRM_DEV_INFO(tpg->dev, "TPG110 chip ID: %d version: %d\n",
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val >> 4, val & 0x0f);
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/* Show display resolution */
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val = tpg110_read_reg(tpg, TPG110_CTRL1);
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val &= TPG110_RES_MASK;
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switch (val) {
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case TPG110_RES_400X240_D:
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DRM_DEV_INFO(tpg->dev,
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"IN 400x240 RGB -> OUT 800x480 RGB (dual scan)\n");
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break;
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case TPG110_RES_480X272_D:
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DRM_DEV_INFO(tpg->dev,
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"IN 480x272 RGB -> OUT 800x480 RGB (dual scan)\n");
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break;
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case TPG110_RES_480X640:
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DRM_DEV_INFO(tpg->dev, "480x640 RGB\n");
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break;
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case TPG110_RES_480X272:
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DRM_DEV_INFO(tpg->dev, "480x272 RGB\n");
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break;
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case TPG110_RES_640X480:
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DRM_DEV_INFO(tpg->dev, "640x480 RGB\n");
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break;
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case TPG110_RES_800X480:
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DRM_DEV_INFO(tpg->dev, "800x480 RGB\n");
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break;
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default:
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DRM_DEV_ERROR(tpg->dev, "ILLEGAL RESOLUTION 0x%02x\n", val);
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break;
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}
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/* From the producer side, this is the same resolution */
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if (val == TPG110_RES_480X272_D)
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val = TPG110_RES_480X272;
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for (i = 0; i < ARRAY_SIZE(tpg110_modes); i++) {
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const struct tpg110_panel_mode *pm;
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pm = &tpg110_modes[i];
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if (pm->magic == val) {
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tpg->panel_mode = pm;
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break;
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}
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}
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if (i == ARRAY_SIZE(tpg110_modes)) {
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DRM_DEV_ERROR(tpg->dev, "unsupported mode (%02x) detected\n",
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val);
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return -ENODEV;
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}
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val = tpg110_read_reg(tpg, TPG110_CTRL2);
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DRM_DEV_INFO(tpg->dev, "resolution and standby is controlled by %s\n",
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(val & TPG110_CTRL2_RES_PM_CTRL) ? "software" : "hardware");
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/* Take control over resolution and standby */
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val |= TPG110_CTRL2_RES_PM_CTRL;
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tpg110_write_reg(tpg, TPG110_CTRL2, val);
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return 0;
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}
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static int tpg110_disable(struct drm_panel *panel)
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{
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struct tpg110 *tpg = to_tpg110(panel);
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u8 val;
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/* Put chip into standby */
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val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
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val &= ~TPG110_CTRL2_PM;
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tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
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return 0;
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}
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static int tpg110_enable(struct drm_panel *panel)
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{
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struct tpg110 *tpg = to_tpg110(panel);
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u8 val;
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|
/* Take chip out of standby */
|
|
|
|
val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
|
|
|
|
val |= TPG110_CTRL2_PM;
|
|
|
|
tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* tpg110_get_modes() - return the appropriate mode
|
|
|
|
* @panel: the panel to get the mode for
|
|
|
|
*
|
|
|
|
* This currently does not present a forest of modes, instead it
|
|
|
|
* presents the mode that is configured for the system under use,
|
|
|
|
* and which is detected by reading the registers of the display.
|
|
|
|
*/
|
2019-12-07 22:03:33 +08:00
|
|
|
static int tpg110_get_modes(struct drm_panel *panel,
|
|
|
|
struct drm_connector *connector)
|
2019-01-12 01:54:06 +08:00
|
|
|
{
|
|
|
|
struct tpg110 *tpg = to_tpg110(panel);
|
|
|
|
struct drm_display_mode *mode;
|
|
|
|
|
|
|
|
connector->display_info.width_mm = tpg->width;
|
|
|
|
connector->display_info.height_mm = tpg->height;
|
|
|
|
connector->display_info.bus_flags = tpg->panel_mode->bus_flags;
|
|
|
|
|
2019-12-07 22:03:35 +08:00
|
|
|
mode = drm_mode_duplicate(connector->dev, &tpg->panel_mode->mode);
|
2019-01-12 01:54:06 +08:00
|
|
|
drm_mode_set_name(mode);
|
|
|
|
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
|
|
|
|
|
|
|
|
mode->width_mm = tpg->width;
|
|
|
|
mode->height_mm = tpg->height;
|
|
|
|
|
|
|
|
drm_mode_probed_add(connector, mode);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_panel_funcs tpg110_drm_funcs = {
|
|
|
|
.disable = tpg110_disable,
|
|
|
|
.enable = tpg110_enable,
|
|
|
|
.get_modes = tpg110_get_modes,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int tpg110_probe(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct device *dev = &spi->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
struct tpg110 *tpg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
tpg = devm_kzalloc(dev, sizeof(*tpg), GFP_KERNEL);
|
|
|
|
if (!tpg)
|
|
|
|
return -ENOMEM;
|
|
|
|
tpg->dev = dev;
|
|
|
|
|
|
|
|
/* We get the physical display dimensions from the DT */
|
|
|
|
ret = of_property_read_u32(np, "width-mm", &tpg->width);
|
|
|
|
if (ret)
|
|
|
|
DRM_DEV_ERROR(dev, "no panel width specified\n");
|
|
|
|
ret = of_property_read_u32(np, "height-mm", &tpg->height);
|
|
|
|
if (ret)
|
|
|
|
DRM_DEV_ERROR(dev, "no panel height specified\n");
|
|
|
|
|
|
|
|
/* This asserts the GRESTB signal, putting the display into reset */
|
|
|
|
tpg->grestb = devm_gpiod_get(dev, "grestb", GPIOD_OUT_HIGH);
|
|
|
|
if (IS_ERR(tpg->grestb)) {
|
|
|
|
DRM_DEV_ERROR(dev, "no GRESTB GPIO\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
spi->bits_per_word = 8;
|
|
|
|
spi->mode |= SPI_3WIRE_HIZ;
|
|
|
|
ret = spi_setup(spi);
|
|
|
|
if (ret < 0) {
|
|
|
|
DRM_DEV_ERROR(dev, "spi setup failed.\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
tpg->spi = spi;
|
|
|
|
|
|
|
|
ret = tpg110_startup(tpg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2019-09-04 21:28:03 +08:00
|
|
|
drm_panel_init(&tpg->panel, dev, &tpg110_drm_funcs,
|
|
|
|
DRM_MODE_CONNECTOR_DPI);
|
2019-12-07 22:03:53 +08:00
|
|
|
|
|
|
|
ret = drm_panel_of_backlight(&tpg->panel);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2019-01-12 01:54:06 +08:00
|
|
|
spi_set_drvdata(spi, tpg);
|
|
|
|
|
|
|
|
return drm_panel_add(&tpg->panel);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tpg110_remove(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct tpg110 *tpg = spi_get_drvdata(spi);
|
|
|
|
|
|
|
|
drm_panel_remove(&tpg->panel);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id tpg110_match[] = {
|
|
|
|
{ .compatible = "tpo,tpg110", },
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, tpg110_match);
|
|
|
|
|
|
|
|
static struct spi_driver tpg110_driver = {
|
|
|
|
.probe = tpg110_probe,
|
|
|
|
.remove = tpg110_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "tpo-tpg110-panel",
|
|
|
|
.of_match_table = tpg110_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_spi_driver(tpg110_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
|
|
|
|
MODULE_DESCRIPTION("TPO TPG110 panel driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|