2005-09-24 03:08:58 +08:00
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#ifndef __ASM_POWERPC_CPUTABLE_H
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#define __ASM_POWERPC_CPUTABLE_H
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2008-06-24 01:48:21 +08:00
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2016-07-27 11:35:15 +08:00
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#include <linux/types.h>
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2008-06-24 01:48:21 +08:00
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#include <asm/asm-compat.h>
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2008-06-24 09:32:39 +08:00
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#include <asm/feature-fixups.h>
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2012-10-09 16:47:26 +08:00
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#include <uapi/asm/cputable.h>
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2008-06-24 01:48:21 +08:00
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2005-09-24 03:08:58 +08:00
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#ifndef __ASSEMBLY__
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/* This structure can grow, it's real size is used by head.S code
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* via the mkdefs mechanism.
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*/
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struct cpu_spec;
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typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
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2006-08-11 13:07:08 +08:00
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typedef void (*cpu_restore_t)(void);
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2005-09-24 03:08:58 +08:00
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2006-01-09 12:41:31 +08:00
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enum powerpc_oprofile_type {
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2006-01-13 20:35:49 +08:00
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PPC_OPROFILE_INVALID = 0,
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PPC_OPROFILE_RS64 = 1,
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PPC_OPROFILE_POWER4 = 2,
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PPC_OPROFILE_G4 = 3,
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2008-02-05 08:27:55 +08:00
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PPC_OPROFILE_FSL_EMB = 4,
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[POWERPC] cell: Add oprofile support
Add PPU event-based and cycle-based profiling support to Oprofile for Cell.
Oprofile is expected to collect data on all CPUs simultaneously.
However, there is one set of performance counters per node. There are
two hardware threads or virtual CPUs on each node. Hence, OProfile must
multiplex in time the performance counter collection on the two virtual
CPUs.
The multiplexing of the performance counters is done by a virtual
counter routine. Initially, the counters are configured to collect data
on the even CPUs in the system, one CPU per node. In order to capture
the PC for the virtual CPU when the performance counter interrupt occurs
(the specified number of events between samples has occurred), the even
processors are configured to handle the performance counter interrupts
for their node. The virtual counter routine is called via a kernel
timer after the virtual sample time. The routine stops the counters,
saves the current counts, loads the last counts for the other virtual
CPU on the node, sets interrupts to be handled by the other virtual CPU
and restarts the counters, the virtual timer routine is scheduled to run
again. The virtual sample time is kept relatively small to make sure
sampling occurs on both CPUs on the node with a relatively small
granularity. Whenever the counters overflow, the performance counter
interrupt is called to collect the PC for the CPU where data is being
collected.
The oprofile driver relies on a firmware RTAS call to setup the debug bus
to route the desired signals to the performance counter hardware to be
counted. The RTAS call must set the routing registers appropriately in
each of the islands to pass the signals down the debug bus as well as
routing the signals from a particular island onto the bus. There is a
second firmware RTAS call to reset the debug bus to the non pass thru
state when the counters are not in use.
Signed-off-by: Carl Love <carll@us.ibm.com>
Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-21 01:45:16 +08:00
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PPC_OPROFILE_CELL = 5,
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2007-04-18 14:38:21 +08:00
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PPC_OPROFILE_PA6T = 6,
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2006-01-09 12:41:31 +08:00
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};
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2007-01-29 11:23:54 +08:00
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enum powerpc_pmc_type {
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PPC_PMC_DEFAULT = 0,
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PPC_PMC_IBM = 1,
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PPC_PMC_PA6T = 2,
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2008-08-18 12:23:51 +08:00
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PPC_PMC_G4 = 3,
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2007-01-29 11:23:54 +08:00
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};
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2007-12-21 12:39:21 +08:00
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struct pt_regs;
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extern int machine_check_generic(struct pt_regs *regs);
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extern int machine_check_4xx(struct pt_regs *regs);
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extern int machine_check_440A(struct pt_regs *regs);
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2010-04-08 13:38:22 +08:00
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extern int machine_check_e500mc(struct pt_regs *regs);
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2007-12-21 12:39:21 +08:00
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extern int machine_check_e500(struct pt_regs *regs);
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extern int machine_check_e200(struct pt_regs *regs);
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2010-03-05 11:43:18 +08:00
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extern int machine_check_47x(struct pt_regs *regs);
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2016-09-16 16:23:11 +08:00
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int machine_check_8xx(struct pt_regs *regs);
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2007-12-21 12:39:21 +08:00
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2015-11-20 17:13:58 +08:00
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extern void cpu_down_flush_e500v2(void);
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extern void cpu_down_flush_e500mc(void);
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extern void cpu_down_flush_e5500(void);
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extern void cpu_down_flush_e6500(void);
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[POWERPC] Fix performance monitor on machines with logical PVR
Some IBM machines supply a "logical" PVR (processor version register)
value in the device tree in the cpu nodes rather than the real PVR.
This is used for instance to indicate that the processors in a POWER6
partition have been configured by the hypervisor to run in POWER5+
mode rather than POWER6 mode. To cope with this, we call identify_cpu
a second time with the logical PVR value (the first call is with the
real PVR value in the very early setup code).
However, POWER5+ machines can also supply a logical PVR value, and use
the same value (the value that indicates a v2.04 architecture
compliant processor). This causes problems for code that uses the
performance monitor (such as oprofile), because the PMU registers are
different in POWER6 (even in POWER5+ mode) from the real POWER5+.
This change works around this problem by taking out the PMU
information from the cputable entries for the logical PVR values, and
changing identify_cpu so that the second call to it won't overwrite
the PMU information that was established by the first call (the one
with the real PVR), but does update the other fields. Specifically,
if the cputable entry for the logical PVR value has num_pmcs == 0,
none of the PMU-related fields get used.
So that we can create a mixed cputable entry, we now make cur_cpu_spec
point to a single static struct cpu_spec, and copy stuff from
cpu_specs[i] into it. This has the side-effect that we can now make
cpu_specs[] be initdata.
Ultimately it would be good to move the PMU-related fields out to a
separate structure, pointed to by the cputable entries, and change
identify_cpu so that it saves the PMU info pointer, copies the whole
structure, and restores the PMU info pointer, rather than identify_cpu
having to list all the fields that are *not* PMU-related.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2007-10-04 12:18:01 +08:00
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/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
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2005-09-24 03:08:58 +08:00
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struct cpu_spec {
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/* CPU is matched via (PVR & pvr_mask) == pvr_value */
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unsigned int pvr_mask;
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unsigned int pvr_value;
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char *cpu_name;
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unsigned long cpu_features; /* Kernel features */
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unsigned int cpu_user_features; /* Userland features */
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2013-04-18 01:33:11 +08:00
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unsigned int cpu_user_features2; /* Userland features v2 */
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2008-12-19 03:13:32 +08:00
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unsigned int mmu_features; /* MMU features */
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2005-09-24 03:08:58 +08:00
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/* cache line sizes */
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unsigned int icache_bsize;
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unsigned int dcache_bsize;
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2015-11-20 17:13:58 +08:00
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/* flush caches inside the current cpu */
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void (*cpu_down_flush)(void);
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2005-09-24 03:08:58 +08:00
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/* number of performance monitor counters */
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unsigned int num_pmcs;
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2007-01-29 11:23:54 +08:00
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enum powerpc_pmc_type pmc_type;
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2005-09-24 03:08:58 +08:00
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/* this is called to initialize various CPU bits like L1 cache,
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* BHT, SPD, etc... from head.S before branching to identify_machine
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*/
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cpu_setup_t cpu_setup;
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2006-08-11 13:07:08 +08:00
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/* Used to restore cpu setup on secondary processors and at resume */
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cpu_restore_t cpu_restore;
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2005-09-24 03:08:58 +08:00
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/* Used by oprofile userspace to select the right counters */
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char *oprofile_cpu_type;
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/* Processor specific oprofile operations */
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2006-01-09 12:41:31 +08:00
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enum powerpc_oprofile_type oprofile_type;
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2006-01-14 07:11:39 +08:00
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2006-06-08 12:42:34 +08:00
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/* Bit locations inside the mmcra change */
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unsigned long oprofile_mmcra_sihv;
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unsigned long oprofile_mmcra_sipr;
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/* Bits to clear during an oprofile exception */
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unsigned long oprofile_mmcra_clear;
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2006-01-14 07:11:39 +08:00
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/* Name of processor class, for the ELF AT_PLATFORM entry */
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char *platform;
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2007-12-21 12:39:21 +08:00
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/* Processor specific machine check handling. Return negative
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* if the error is fatal, 1 if it was fully recovered and 0 to
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* pass up (not CPU originated) */
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int (*machine_check)(struct pt_regs *regs);
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2013-10-30 22:34:40 +08:00
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/*
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* Processor specific early machine check handler which is
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* called in real mode to handle SLB and TLB errors.
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*/
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long (*machine_check_early)(struct pt_regs *regs);
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2013-10-30 22:34:56 +08:00
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/*
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* Processor specific routine to flush tlbs.
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*/
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2014-12-19 11:11:05 +08:00
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void (*flush_tlb)(unsigned int action);
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2013-10-30 22:34:56 +08:00
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2005-09-24 03:08:58 +08:00
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};
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extern struct cpu_spec *cur_cpu_spec;
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2006-10-24 14:42:40 +08:00
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extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
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2017-05-09 11:16:52 +08:00
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extern void set_cur_cpu_spec(struct cpu_spec *s);
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2006-11-10 17:38:53 +08:00
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extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
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2017-05-09 11:16:52 +08:00
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extern void identify_cpu_name(unsigned int pvr);
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2006-10-20 09:47:18 +08:00
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extern void do_feature_fixups(unsigned long value, void *fixup_start,
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void *fixup_end);
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2005-10-06 10:06:20 +08:00
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2008-07-16 07:58:51 +08:00
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extern const char *powerpc_base_platform;
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powerpc: Add option to use jump label for cpu_has_feature()
We do binary patching of asm code using CPU features, which is a
one-time operation, done during early boot. However checks of CPU
features in C code are currently done at run time, even though the set
of CPU features can never change after boot.
We can optimise this by using jump labels to implement cpu_has_feature(),
meaning checks in C code are binary patched into a single nop or branch.
For a C sequence along the lines of:
if (cpu_has_feature(FOO))
return 2;
The generated code before is roughly:
ld r9,-27640(r2)
ld r9,0(r9)
lwz r9,32(r9)
cmpwi cr7,r9,0
bge cr7, 1f
li r3,2
blr
1: ...
After (true):
nop
li r3,2
blr
After (false):
b 1f
li r3,2
blr
1: ...
mpe: Rename MAX_CPU_FEATURES as we already have a #define with that
name, and define it simply as a constant, rather than doing tricks with
sizeof and NULL pointers. Rename the array to cpu_feature_keys. Use the
kconfig we added to guard it. Add BUILD_BUG_ON() if the feature is not a
compile time constant. Rewrite the change log.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-07-23 17:12:41 +08:00
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#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
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extern void cpu_feature_keys_init(void);
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#else
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static inline void cpu_feature_keys_init(void) { }
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#endif
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2014-12-19 11:11:05 +08:00
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/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
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enum {
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TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
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TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
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};
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2005-09-24 03:08:58 +08:00
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#endif /* __ASSEMBLY__ */
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/* CPU kernel features */
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/* Retain the 32b definitions all use bottom half of word */
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2012-12-20 22:06:39 +08:00
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
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#define CPU_FTR_L2CR ASM_CONST(0x00000002)
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#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
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#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
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#define CPU_FTR_TAU ASM_CONST(0x00000010)
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#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
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#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
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#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
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#define CPU_FTR_601 ASM_CONST(0x00000100)
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#define CPU_FTR_DBELL ASM_CONST(0x00000200)
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#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
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#define CPU_FTR_L3CR ASM_CONST(0x00000800)
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#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
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#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
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#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
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#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
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#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
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#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
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#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
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#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
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#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
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#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
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#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
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#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
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#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
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#define CPU_FTR_SPE ASM_CONST(0x02000000)
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#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
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#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
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#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
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#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
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#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
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2005-09-24 03:08:58 +08:00
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2006-06-28 11:50:39 +08:00
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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* on 32-bit, make the names available but defined to be 0.
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*/
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2005-09-24 03:08:58 +08:00
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#ifdef __powerpc64__
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2006-06-28 11:50:39 +08:00
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#define LONG_ASM_CONST(x) ASM_CONST(x)
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2005-09-24 03:08:58 +08:00
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#else
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2006-06-28 11:50:39 +08:00
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#define LONG_ASM_CONST(x) 0
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2005-09-24 03:08:58 +08:00
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#endif
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2012-12-20 22:06:40 +08:00
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#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
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#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
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#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
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2013-05-01 04:17:02 +08:00
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#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
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2016-02-19 08:16:24 +08:00
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#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
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2012-12-20 22:06:40 +08:00
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#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
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#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
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#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
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#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
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#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
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#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
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#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
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#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
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#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
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#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
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#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
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#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
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|
|
|
|
#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
|
|
|
|
|
#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
|
|
|
|
|
#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
|
|
|
|
|
#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
|
2017-10-19 12:08:19 +08:00
|
|
|
/* Free LONG_ASM_CONST(0x0020000000000000) */
|
2012-12-20 22:06:40 +08:00
|
|
|
#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
|
|
|
|
|
#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
|
2013-05-01 04:17:02 +08:00
|
|
|
#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
|
2012-12-20 22:06:40 +08:00
|
|
|
#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
|
2012-12-20 22:06:42 +08:00
|
|
|
#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
|
2013-05-17 04:27:31 +08:00
|
|
|
#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
|
2014-03-14 13:00:28 +08:00
|
|
|
#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
|
2016-08-24 17:33:36 +08:00
|
|
|
#define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000)
|
2017-11-03 12:13:19 +08:00
|
|
|
#define CPU_FTR_POWER9_DD20 LONG_ASM_CONST(0x8000000000000000)
|
2006-06-28 11:50:39 +08:00
|
|
|
|
2005-09-24 03:08:58 +08:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
2011-04-07 03:48:50 +08:00
|
|
|
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
|
|
|
|
|
|
2014-07-10 10:29:20 +08:00
|
|
|
#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
|
2005-09-24 03:08:58 +08:00
|
|
|
|
|
|
|
|
/* We only set the altivec features if the kernel was compiled with altivec
|
|
|
|
|
* support
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
|
|
|
|
|
#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
|
|
|
|
|
#else
|
|
|
|
|
#define CPU_FTR_ALTIVEC_COMP 0
|
|
|
|
|
#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-06-25 12:07:18 +08:00
|
|
|
/* We only set the VSX features if the kernel was compiled with VSX
|
|
|
|
|
* support
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
#define CPU_FTR_VSX_COMP CPU_FTR_VSX
|
|
|
|
|
#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
|
|
|
|
|
#else
|
|
|
|
|
#define CPU_FTR_VSX_COMP 0
|
|
|
|
|
#define PPC_FEATURE_HAS_VSX_COMP 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2007-09-13 14:44:20 +08:00
|
|
|
/* We only set the spe features if the kernel was compiled with spe
|
|
|
|
|
* support
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
|
#define CPU_FTR_SPE_COMP CPU_FTR_SPE
|
|
|
|
|
#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
|
|
|
|
|
#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
|
|
|
|
|
#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
|
|
|
|
|
#else
|
|
|
|
|
#define CPU_FTR_SPE_COMP 0
|
|
|
|
|
#define PPC_FEATURE_HAS_SPE_COMP 0
|
|
|
|
|
#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
|
|
|
|
|
#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-02-14 00:21:29 +08:00
|
|
|
/* We only set the TM feature if the kernel was compiled with TM supprt */
|
|
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
2015-06-12 09:06:32 +08:00
|
|
|
#define CPU_FTR_TM_COMP CPU_FTR_TM
|
|
|
|
|
#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
|
|
|
|
|
#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
|
2013-02-14 00:21:29 +08:00
|
|
|
#else
|
2015-06-12 09:06:32 +08:00
|
|
|
#define CPU_FTR_TM_COMP 0
|
|
|
|
|
#define PPC_FEATURE2_HTM_COMP 0
|
|
|
|
|
#define PPC_FEATURE2_HTM_NOSC_COMP 0
|
2013-02-14 00:21:29 +08:00
|
|
|
#endif
|
|
|
|
|
|
2007-09-15 04:32:14 +08:00
|
|
|
/* We need to mark all pages as being coherent if we're SMP or we have a
|
|
|
|
|
* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
|
|
|
|
|
* require it for PCI "streaming/prefetch" to work properly.
|
2009-03-17 23:17:50 +08:00
|
|
|
* This is also required by 52xx family.
|
2005-09-24 03:08:58 +08:00
|
|
|
*/
|
2006-02-22 23:46:02 +08:00
|
|
|
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
|
2009-03-17 23:17:50 +08:00
|
|
|
|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
|
|
|
|
|
|| defined(CONFIG_PPC_MPC52xx)
|
2005-09-24 03:08:58 +08:00
|
|
|
#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
|
|
|
|
|
#else
|
|
|
|
|
#define CPU_FTR_COMMON 0
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* The powersave features NAP & DOZE seems to confuse BDI when
|
|
|
|
|
debugging. So if a BDI is used, disable theses
|
|
|
|
|
*/
|
|
|
|
|
#ifndef CONFIG_BDI_SWITCH
|
|
|
|
|
#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
|
|
|
|
|
#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
|
|
|
|
|
#else
|
|
|
|
|
#define CPU_FTR_MAYBE_CAN_DOZE 0
|
|
|
|
|
#define CPU_FTR_MAYBE_CAN_NAP 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-12-19 03:13:32 +08:00
|
|
|
#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
|
|
|
|
|
#define CPU_FTRS_603 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
|
2006-06-07 14:14:40 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_604 (CPU_FTR_COMMON | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_740 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
|
2006-06-07 14:14:40 +08:00
|
|
|
CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_750 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
|
2006-06-07 14:14:40 +08:00
|
|
|
CPU_FTR_PPC_LE)
|
2008-12-19 03:13:32 +08:00
|
|
|
#define CPU_FTRS_750CL (CPU_FTRS_750)
|
2007-07-03 00:06:53 +08:00
|
|
|
#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
|
|
|
|
|
#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
|
2008-12-19 03:13:32 +08:00
|
|
|
#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
|
2007-07-03 00:06:53 +08:00
|
|
|
#define CPU_FTRS_750GX (CPU_FTRS_750FX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_ALTIVEC_COMP | \
|
2006-06-07 14:14:40 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
|
2006-06-07 14:14:40 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
|
2006-06-07 14:14:40 +08:00
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
|
|
|
|
|
CPU_FTR_NEED_PAIRED_STWCX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
|
2007-05-03 05:34:43 +08:00
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
|
2007-11-10 06:17:49 +08:00
|
|
|
CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
|
2007-09-15 04:32:14 +08:00
|
|
|
#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_COMMON)
|
[POWERPC] Merge CPU features pertaining to icache coherency
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This tries to clarify the situation a little. The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified. We check this, instead of
SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
|
|
|
#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
|
2006-12-08 16:43:30 +08:00
|
|
|
CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
|
2008-12-19 03:13:32 +08:00
|
|
|
#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
|
2015-04-22 18:06:45 +08:00
|
|
|
#define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
|
2008-12-12 14:33:25 +08:00
|
|
|
#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
|
|
|
|
#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
2008-12-19 03:13:22 +08:00
|
|
|
#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
|
|
|
|
|
CPU_FTR_INDEXED_DCR)
|
2010-03-05 18:43:12 +08:00
|
|
|
#define CPU_FTRS_47X (CPU_FTRS_440x6)
|
2007-09-13 14:44:20 +08:00
|
|
|
#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
|
|
|
|
|
CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
|
2011-12-20 23:34:12 +08:00
|
|
|
CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
|
|
|
|
|
CPU_FTR_DEBUG_LVL_EXC)
|
2008-06-19 05:26:52 +08:00
|
|
|
#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
|
2008-12-12 14:33:25 +08:00
|
|
|
CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
|
|
|
|
|
CPU_FTR_NOEXECUTE)
|
2008-06-19 05:26:52 +08:00
|
|
|
#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
|
2008-12-12 14:33:25 +08:00
|
|
|
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
2010-05-28 06:35:12 +08:00
|
|
|
#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
|
2009-02-12 21:54:53 +08:00
|
|
|
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
|
2011-12-20 23:34:47 +08:00
|
|
|
CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
|
2013-07-24 09:21:11 +08:00
|
|
|
/*
|
|
|
|
|
* e5500/e6500 erratum A-006958 is a timebase bug that can use the
|
|
|
|
|
* same workaround as CPU_FTR_CELL_TB_BUG.
|
|
|
|
|
*/
|
2011-04-06 13:11:06 +08:00
|
|
|
#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
|
|
|
|
|
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
|
2011-04-06 13:18:48 +08:00
|
|
|
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
2013-07-24 09:21:11 +08:00
|
|
|
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
|
2011-11-07 01:51:07 +08:00
|
|
|
#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
|
|
|
|
|
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
|
|
|
|
|
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
2013-07-24 09:21:11 +08:00
|
|
|
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
|
2011-12-08 15:20:27 +08:00
|
|
|
CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
|
2006-03-23 14:36:59 +08:00
|
|
|
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
2006-11-23 07:46:46 +08:00
|
|
|
|
|
|
|
|
/* 64-bit CPUs */
|
2008-07-01 23:16:40 +08:00
|
|
|
#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2010-08-11 09:40:27 +08:00
|
|
|
CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
|
|
|
|
|
CPU_FTR_STCX_CHECKS_ADDRESS)
|
2008-07-01 23:16:40 +08:00
|
|
|
#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 08:26:11 +08:00
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
|
2008-08-22 12:36:19 +08:00
|
|
|
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
|
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 08:26:11 +08:00
|
|
|
CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
|
2013-05-17 04:27:31 +08:00
|
|
|
CPU_FTR_HVMODE | CPU_FTR_DABRX)
|
2008-07-01 23:16:40 +08:00
|
|
|
#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
2011-04-07 03:48:50 +08:00
|
|
|
CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
|
2013-05-17 04:27:31 +08:00
|
|
|
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
|
2008-07-01 23:16:40 +08:00
|
|
|
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2006-04-29 07:51:06 +08:00
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
2011-04-07 03:48:50 +08:00
|
|
|
CPU_FTR_COHERENT_ICACHE | \
|
2006-12-08 14:46:58 +08:00
|
|
|
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
2010-08-11 09:40:27 +08:00
|
|
|
CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
|
2013-05-17 04:27:31 +08:00
|
|
|
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
|
|
|
|
|
CPU_FTR_DABRX)
|
2008-07-01 23:16:40 +08:00
|
|
|
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 08:26:11 +08:00
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
|
2008-06-18 08:47:26 +08:00
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
2011-04-07 03:48:50 +08:00
|
|
|
CPU_FTR_COHERENT_ICACHE | \
|
2008-06-18 08:47:26 +08:00
|
|
|
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
2010-08-11 09:40:27 +08:00
|
|
|
CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
|
2011-05-03 04:43:04 +08:00
|
|
|
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
2017-10-19 12:08:19 +08:00
|
|
|
CPU_FTR_CFAR | CPU_FTR_HVMODE | \
|
2013-05-17 04:27:31 +08:00
|
|
|
CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
|
2012-10-31 03:34:15 +08:00
|
|
|
#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
|
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
|
|
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
|
|
|
|
CPU_FTR_COHERENT_ICACHE | \
|
|
|
|
|
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
|
|
|
|
CPU_FTR_DSCR | CPU_FTR_SAO | \
|
|
|
|
|
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
2017-10-19 12:08:19 +08:00
|
|
|
CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
|
2013-05-01 04:17:02 +08:00
|
|
|
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
|
2017-05-25 14:33:52 +08:00
|
|
|
CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
|
2014-03-14 13:00:28 +08:00
|
|
|
#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
|
2014-07-18 10:11:37 +08:00
|
|
|
#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
|
2016-02-19 08:16:24 +08:00
|
|
|
#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
|
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
|
|
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
|
|
|
|
CPU_FTR_COHERENT_ICACHE | \
|
|
|
|
|
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
|
|
|
|
CPU_FTR_DSCR | CPU_FTR_SAO | \
|
|
|
|
|
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
2017-04-19 10:27:37 +08:00
|
|
|
CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
|
2016-02-19 08:16:24 +08:00
|
|
|
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
|
|
|
|
|
CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300)
|
2017-04-19 10:27:38 +08:00
|
|
|
#define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
|
|
|
|
|
(~CPU_FTR_SAO))
|
2017-11-03 12:13:19 +08:00
|
|
|
#define CPU_FTRS_POWER9_DD20 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD20)
|
2008-07-01 23:16:40 +08:00
|
|
|
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
2008-12-19 03:13:32 +08:00
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2006-03-23 14:36:59 +08:00
|
|
|
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
2011-04-07 03:48:50 +08:00
|
|
|
CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
|
2013-05-17 04:27:31 +08:00
|
|
|
CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
|
2008-07-01 23:16:40 +08:00
|
|
|
#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
2011-04-07 03:48:50 +08:00
|
|
|
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
|
2013-05-17 04:27:31 +08:00
|
|
|
CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
|
2008-12-19 03:13:32 +08:00
|
|
|
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
|
2005-09-24 03:08:58 +08:00
|
|
|
|
2005-12-13 04:45:33 +08:00
|
|
|
#ifdef __powerpc64__
|
2011-04-06 13:11:06 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
2014-08-06 16:26:28 +08:00
|
|
|
#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
|
2011-04-06 13:11:06 +08:00
|
|
|
#else
|
2006-03-23 14:36:59 +08:00
|
|
|
#define CPU_FTRS_POSSIBLE \
|
2014-07-10 10:29:18 +08:00
|
|
|
(CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
|
|
|
|
|
CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
|
2014-08-06 13:42:17 +08:00
|
|
|
CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
|
2017-11-03 12:13:19 +08:00
|
|
|
CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | \
|
|
|
|
|
CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD20)
|
2011-04-06 13:11:06 +08:00
|
|
|
#endif
|
2005-12-13 04:45:33 +08:00
|
|
|
#else
|
2006-03-23 14:36:59 +08:00
|
|
|
enum {
|
|
|
|
|
CPU_FTRS_POSSIBLE =
|
2014-07-10 10:29:26 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_32
|
2005-09-24 03:08:58 +08:00
|
|
|
CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
|
|
|
|
|
CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
|
|
|
|
|
CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
|
|
|
|
|
CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
|
|
|
|
|
CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
|
|
|
|
|
CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
|
|
|
|
|
CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
|
2006-12-08 16:43:30 +08:00
|
|
|
CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
|
|
|
|
|
CPU_FTRS_CLASSIC32 |
|
2005-09-24 03:08:58 +08:00
|
|
|
#else
|
|
|
|
|
CPU_FTRS_GENERIC_32 |
|
|
|
|
|
#endif
|
2017-08-08 19:58:54 +08:00
|
|
|
#ifdef CONFIG_PPC_8xx
|
2005-09-24 03:08:58 +08:00
|
|
|
CPU_FTRS_8XX |
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
|
CPU_FTRS_40X |
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_44x
|
2008-12-19 03:13:22 +08:00
|
|
|
CPU_FTRS_44X | CPU_FTRS_440x6 |
|
2005-09-24 03:08:58 +08:00
|
|
|
#endif
|
2010-03-05 18:43:12 +08:00
|
|
|
#ifdef CONFIG_PPC_47x
|
2011-01-26 14:17:58 +08:00
|
|
|
CPU_FTRS_47X | CPU_FTR_476_DD2 |
|
2010-03-05 18:43:12 +08:00
|
|
|
#endif
|
2005-09-24 03:08:58 +08:00
|
|
|
#ifdef CONFIG_E200
|
|
|
|
|
CPU_FTRS_E200 |
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_E500
|
2011-12-20 23:34:14 +08:00
|
|
|
CPU_FTRS_E500 | CPU_FTRS_E500_2 |
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_PPC_E500MC
|
|
|
|
|
CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
|
2005-09-24 03:08:58 +08:00
|
|
|
#endif
|
|
|
|
|
0,
|
2006-03-23 14:36:59 +08:00
|
|
|
};
|
|
|
|
|
#endif /* __powerpc64__ */
|
2005-09-24 03:08:58 +08:00
|
|
|
|
2005-12-13 04:45:33 +08:00
|
|
|
#ifdef __powerpc64__
|
2011-04-06 13:11:06 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
2014-08-06 16:26:28 +08:00
|
|
|
#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
|
2011-04-06 13:11:06 +08:00
|
|
|
#else
|
2006-03-23 14:36:59 +08:00
|
|
|
#define CPU_FTRS_ALWAYS \
|
2014-07-10 10:29:18 +08:00
|
|
|
(CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
|
|
|
|
|
CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
|
2014-08-06 13:42:17 +08:00
|
|
|
CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
|
2016-02-19 08:16:24 +08:00
|
|
|
CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
|
|
|
|
|
CPU_FTRS_POWER9)
|
2011-04-06 13:11:06 +08:00
|
|
|
#endif
|
2005-12-13 04:45:33 +08:00
|
|
|
#else
|
2006-03-23 14:36:59 +08:00
|
|
|
enum {
|
|
|
|
|
CPU_FTRS_ALWAYS =
|
2014-07-10 10:29:26 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_32
|
2005-09-24 03:08:58 +08:00
|
|
|
CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
|
|
|
|
|
CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
|
|
|
|
|
CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
|
|
|
|
|
CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
|
|
|
|
|
CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
|
|
|
|
|
CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
|
|
|
|
|
CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
|
2006-12-08 16:43:30 +08:00
|
|
|
CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
|
|
|
|
|
CPU_FTRS_CLASSIC32 &
|
2005-09-24 03:08:58 +08:00
|
|
|
#else
|
|
|
|
|
CPU_FTRS_GENERIC_32 &
|
|
|
|
|
#endif
|
2017-08-08 19:58:54 +08:00
|
|
|
#ifdef CONFIG_PPC_8xx
|
2005-09-24 03:08:58 +08:00
|
|
|
CPU_FTRS_8XX &
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
|
CPU_FTRS_40X &
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_44x
|
2008-12-19 03:13:22 +08:00
|
|
|
CPU_FTRS_44X & CPU_FTRS_440x6 &
|
2005-09-24 03:08:58 +08:00
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_E200
|
|
|
|
|
CPU_FTRS_E200 &
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_E500
|
2011-12-20 23:34:14 +08:00
|
|
|
CPU_FTRS_E500 & CPU_FTRS_E500_2 &
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_PPC_E500MC
|
|
|
|
|
CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
|
2005-09-24 03:08:58 +08:00
|
|
|
#endif
|
2011-12-20 23:34:47 +08:00
|
|
|
~CPU_FTR_EMB_HV & /* can be removed at runtime */
|
2005-09-24 03:08:58 +08:00
|
|
|
CPU_FTRS_POSSIBLE,
|
|
|
|
|
};
|
2006-03-23 14:36:59 +08:00
|
|
|
#endif /* __powerpc64__ */
|
2005-09-24 03:08:58 +08:00
|
|
|
|
2010-06-15 14:05:19 +08:00
|
|
|
#define HBP_NUM 1
|
|
|
|
|
|
2005-09-24 03:08:58 +08:00
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
|
|
|
|
|
|
#endif /* __ASM_POWERPC_CPUTABLE_H */
|