2006-09-27 16:15:32 +08:00
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/*
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* arch/sh/math-emu/math.c
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*
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* Copyright (C) 2006 Takashi YOSHII <takasi-y@ops.dti.ne.jp>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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2017-02-09 01:51:30 +08:00
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#include <linux/sched/signal.h>
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2006-09-27 16:15:32 +08:00
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#include <linux/signal.h>
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2010-10-13 05:55:26 +08:00
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#include <linux/perf_event.h>
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2006-09-27 16:15:32 +08:00
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2016-12-25 03:46:01 +08:00
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#include <linux/uaccess.h>
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2006-09-27 16:15:32 +08:00
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "sfp-util.h"
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#include <math-emu/soft-fp.h>
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#include <math-emu/single.h>
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#include <math-emu/double.h>
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#define FPUL (fregs->fpul)
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#define FPSCR (fregs->fpscr)
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#define FPSCR_RM (FPSCR&3)
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#define FPSCR_DN ((FPSCR>>18)&1)
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#define FPSCR_PR ((FPSCR>>19)&1)
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#define FPSCR_SZ ((FPSCR>>20)&1)
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#define FPSCR_FR ((FPSCR>>21)&1)
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#define FPSCR_MASK 0x003fffffUL
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#define BANK(n) (n^(FPSCR_FR?16:0))
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#define FR ((unsigned long*)(fregs->fp_regs))
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#define FR0 (FR[BANK(0)])
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#define FRn (FR[BANK(n)])
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#define FRm (FR[BANK(m)])
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#define DR ((unsigned long long*)(fregs->fp_regs))
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#define DRn (DR[BANK(n)/2])
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#define DRm (DR[BANK(m)/2])
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#define XREG(n) (n^16)
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#define XFn (FR[BANK(XREG(n))])
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#define XFm (FR[BANK(XREG(m))])
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#define XDn (DR[BANK(XREG(n))/2])
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#define XDm (DR[BANK(XREG(m))/2])
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#define R0 (regs->regs[0])
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#define Rn (regs->regs[n])
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#define Rm (regs->regs[m])
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2021-10-05 08:19:14 +08:00
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#define MWRITE(d,a) ({if(put_user(d, (typeof (d) __user *)a)) return -EFAULT;})
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#define MREAD(d,a) ({if(get_user(d, (typeof (d) __user *)a)) return -EFAULT;})
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2006-09-27 16:15:32 +08:00
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#define PACK_S(r,f) FP_PACK_SP(&r,f)
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#define UNPACK_S(f,r) FP_UNPACK_SP(f,&r)
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#define PACK_D(r,f) \
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{u32 t[2]; FP_PACK_DP(t,f); ((u32*)&r)[0]=t[1]; ((u32*)&r)[1]=t[0];}
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#define UNPACK_D(f,r) \
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{u32 t[2]; t[0]=((u32*)&r)[1]; t[1]=((u32*)&r)[0]; FP_UNPACK_DP(f,t);}
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// 2 args instructions.
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#define BOTH_PRmn(op,x) \
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FP_DECL_EX; if(FPSCR_PR) op(D,x,DRm,DRn); else op(S,x,FRm,FRn);
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#define CMP_X(SZ,R,M,N) do{ \
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FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
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UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
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FP_CMP_##SZ(R, Fn, Fm, 2); }while(0)
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#define EQ_X(SZ,R,M,N) do{ \
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FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
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UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
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FP_CMP_EQ_##SZ(R, Fn, Fm); }while(0)
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#define CMP(OP) ({ int r; BOTH_PRmn(OP##_X,r); r; })
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static int
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fcmp_gt(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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if (CMP(CMP) > 0)
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regs->sr |= 1;
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else
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regs->sr &= ~1;
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return 0;
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}
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static int
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fcmp_eq(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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if (CMP(CMP /*EQ*/) == 0)
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regs->sr |= 1;
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else
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regs->sr &= ~1;
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return 0;
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}
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#define ARITH_X(SZ,OP,M,N) do{ \
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FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); FP_DECL_##SZ(Fr); \
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UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
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FP_##OP##_##SZ(Fr, Fn, Fm); \
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PACK_##SZ(N, Fr); }while(0)
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static int
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fadd(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, ADD);
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return 0;
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}
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static int
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fsub(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, SUB);
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return 0;
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}
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static int
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fmul(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, MUL);
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return 0;
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}
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static int
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fdiv(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, DIV);
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return 0;
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}
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static int
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fmac(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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FP_DECL_EX;
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FP_DECL_S(Fr);
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FP_DECL_S(Ft);
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FP_DECL_S(F0);
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FP_DECL_S(Fm);
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FP_DECL_S(Fn);
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UNPACK_S(F0, FR0);
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UNPACK_S(Fm, FRm);
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UNPACK_S(Fn, FRn);
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FP_MUL_S(Ft, Fm, F0);
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FP_ADD_S(Fr, Fn, Ft);
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PACK_S(FRn, Fr);
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return 0;
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}
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2007-05-14 07:15:10 +08:00
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// to process fmov's extension (odd n for DR access XD).
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2006-09-27 16:15:32 +08:00
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#define FMOV_EXT(x) if(x&1) x+=16-1
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static int
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fmov_idx_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(n);
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm + R0 + 4);
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2006-09-27 16:15:32 +08:00
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n++;
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm + R0);
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2006-09-27 16:15:32 +08:00
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} else {
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm + R0);
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2006-09-27 16:15:32 +08:00
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}
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return 0;
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}
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static int
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fmov_mem_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(n);
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm + 4);
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2006-09-27 16:15:32 +08:00
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n++;
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm);
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2006-09-27 16:15:32 +08:00
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} else {
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm);
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2006-09-27 16:15:32 +08:00
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}
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return 0;
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}
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static int
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fmov_inc_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(n);
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm + 4);
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2006-09-27 16:15:32 +08:00
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n++;
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm);
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2006-09-27 16:15:32 +08:00
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Rm += 8;
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} else {
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2021-10-05 08:19:14 +08:00
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MREAD(FRn, Rm);
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2006-09-27 16:15:32 +08:00
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Rm += 4;
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}
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return 0;
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}
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static int
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fmov_reg_idx(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(m);
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn + R0 + 4);
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2006-09-27 16:15:32 +08:00
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m++;
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn + R0);
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2006-09-27 16:15:32 +08:00
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} else {
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn + R0);
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2006-09-27 16:15:32 +08:00
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}
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return 0;
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}
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static int
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fmov_reg_mem(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(m);
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn + 4);
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2006-09-27 16:15:32 +08:00
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m++;
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn);
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2006-09-27 16:15:32 +08:00
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} else {
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn);
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2006-09-27 16:15:32 +08:00
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}
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return 0;
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}
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static int
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fmov_reg_dec(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(m);
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Rn -= 8;
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn + 4);
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2006-09-27 16:15:32 +08:00
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m++;
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn);
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2006-09-27 16:15:32 +08:00
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} else {
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Rn -= 4;
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2021-10-05 08:19:14 +08:00
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MWRITE(FRm, Rn);
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2006-09-27 16:15:32 +08:00
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}
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return 0;
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}
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static int
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fmov_reg_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(m);
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FMOV_EXT(n);
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DRn = DRm;
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} else {
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FRn = FRm;
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}
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return 0;
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}
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static int
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fnop_mn(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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return -EINVAL;
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}
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// 1 arg instructions.
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#define NOTYETn(i) static int i(struct sh_fpu_soft_struct *fregs, int n) \
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{ printk( #i " not yet done.\n"); return 0; }
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NOTYETn(ftrv)
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NOTYETn(fsqrt)
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NOTYETn(fipr)
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NOTYETn(fsca)
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NOTYETn(fsrra)
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#define EMU_FLOAT_X(SZ,N) do { \
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FP_DECL_##SZ(Fn); \
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FP_FROM_INT_##SZ(Fn, FPUL, 32, int); \
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PACK_##SZ(N, Fn); }while(0)
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static int ffloat(struct sh_fpu_soft_struct *fregs, int n)
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{
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FP_DECL_EX;
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if (FPSCR_PR)
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EMU_FLOAT_X(D, DRn);
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else
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EMU_FLOAT_X(S, FRn);
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return 0;
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}
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#define EMU_FTRC_X(SZ,N) do { \
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FP_DECL_##SZ(Fn); \
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UNPACK_##SZ(Fn, N); \
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FP_TO_INT_##SZ(FPUL, Fn, 32, 1); }while(0)
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static int ftrc(struct sh_fpu_soft_struct *fregs, int n)
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{
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FP_DECL_EX;
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if (FPSCR_PR)
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EMU_FTRC_X(D, DRn);
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else
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EMU_FTRC_X(S, FRn);
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return 0;
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}
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static int fcnvsd(struct sh_fpu_soft_struct *fregs, int n)
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{
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FP_DECL_EX;
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FP_DECL_S(Fn);
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FP_DECL_D(Fr);
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UNPACK_S(Fn, FPUL);
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FP_CONV(D, S, 2, 1, Fr, Fn);
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PACK_D(DRn, Fr);
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return 0;
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}
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static int fcnvds(struct sh_fpu_soft_struct *fregs, int n)
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{
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FP_DECL_EX;
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FP_DECL_D(Fn);
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FP_DECL_S(Fr);
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|
UNPACK_D(Fn, DRn);
|
|
|
|
FP_CONV(S, D, 1, 2, Fr, Fn);
|
|
|
|
PACK_S(FPUL, Fr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fxchg(struct sh_fpu_soft_struct *fregs, int flag)
|
|
|
|
{
|
|
|
|
FPSCR ^= flag;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsts(struct sh_fpu_soft_struct *fregs, int n)
|
|
|
|
{
|
|
|
|
FRn = FPUL;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int flds(struct sh_fpu_soft_struct *fregs, int n)
|
|
|
|
{
|
|
|
|
FPUL = FRn;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fneg(struct sh_fpu_soft_struct *fregs, int n)
|
|
|
|
{
|
|
|
|
FRn ^= (1 << (_FP_W_TYPE_SIZE - 1));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fabs(struct sh_fpu_soft_struct *fregs, int n)
|
|
|
|
{
|
|
|
|
FRn &= ~(1 << (_FP_W_TYPE_SIZE - 1));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fld0(struct sh_fpu_soft_struct *fregs, int n)
|
|
|
|
{
|
|
|
|
FRn = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fld1(struct sh_fpu_soft_struct *fregs, int n)
|
|
|
|
{
|
|
|
|
FRn = (_FP_EXPBIAS_S << (_FP_FRACBITS_S - 1));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fnop_n(struct sh_fpu_soft_struct *fregs, int n)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Instruction decoders.
|
|
|
|
|
|
|
|
static int id_fxfd(struct sh_fpu_soft_struct *, int);
|
|
|
|
static int id_fnxd(struct sh_fpu_soft_struct *, struct pt_regs *, int, int);
|
|
|
|
|
|
|
|
static int (*fnxd[])(struct sh_fpu_soft_struct *, int) = {
|
|
|
|
fsts, flds, ffloat, ftrc, fneg, fabs, fsqrt, fsrra,
|
|
|
|
fld0, fld1, fcnvsd, fcnvds, fnop_n, fnop_n, fipr, id_fxfd
|
|
|
|
};
|
|
|
|
|
|
|
|
static int (*fnmx[])(struct sh_fpu_soft_struct *, struct pt_regs *, int, int) = {
|
|
|
|
fadd, fsub, fmul, fdiv, fcmp_eq, fcmp_gt, fmov_idx_reg, fmov_reg_idx,
|
|
|
|
fmov_mem_reg, fmov_inc_reg, fmov_reg_mem, fmov_reg_dec,
|
|
|
|
fmov_reg_reg, id_fnxd, fmac, fnop_mn};
|
|
|
|
|
|
|
|
static int id_fxfd(struct sh_fpu_soft_struct *fregs, int x)
|
|
|
|
{
|
|
|
|
const int flag[] = { FPSCR_SZ, FPSCR_PR, FPSCR_FR, 0 };
|
|
|
|
switch (x & 3) {
|
|
|
|
case 3:
|
|
|
|
fxchg(fregs, flag[x >> 2]);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
ftrv(fregs, x - 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fsca(fregs, x);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
id_fnxd(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int x, int n)
|
|
|
|
{
|
|
|
|
return (fnxd[x])(fregs, n);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
id_fnmx(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, u16 code)
|
|
|
|
{
|
|
|
|
int n = (code >> 8) & 0xf, m = (code >> 4) & 0xf, x = code & 0xf;
|
|
|
|
return (fnmx[x])(fregs, regs, m, n);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
id_sys(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, u16 code)
|
|
|
|
{
|
|
|
|
int n = ((code >> 8) & 0xf);
|
|
|
|
unsigned long *reg = (code & 0x0010) ? &FPUL : &FPSCR;
|
|
|
|
|
|
|
|
switch (code & 0xf0ff) {
|
|
|
|
case 0x005a:
|
|
|
|
case 0x006a:
|
|
|
|
Rn = *reg;
|
|
|
|
break;
|
|
|
|
case 0x405a:
|
|
|
|
case 0x406a:
|
|
|
|
*reg = Rn;
|
|
|
|
break;
|
|
|
|
case 0x4052:
|
|
|
|
case 0x4062:
|
|
|
|
Rn -= 4;
|
2021-10-05 08:19:14 +08:00
|
|
|
MWRITE(*reg, Rn);
|
2006-09-27 16:15:32 +08:00
|
|
|
break;
|
|
|
|
case 0x4056:
|
|
|
|
case 0x4066:
|
2021-10-05 08:19:14 +08:00
|
|
|
MREAD(*reg, Rn);
|
2006-09-27 16:15:32 +08:00
|
|
|
Rn += 4;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fpu_emulate(u16 code, struct sh_fpu_soft_struct *fregs, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
if ((code & 0xf000) == 0xf000)
|
|
|
|
return id_fnmx(fregs, regs, code);
|
|
|
|
else
|
|
|
|
return id_sys(fregs, regs, code);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* fpu_init - Initialize FPU registers
|
|
|
|
* @fpu: Pointer to software emulated FPU registers.
|
|
|
|
*/
|
|
|
|
static void fpu_init(struct sh_fpu_soft_struct *fpu)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
fpu->fpscr = FPSCR_INIT;
|
|
|
|
fpu->fpul = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
fpu->fp_regs[i] = 0;
|
|
|
|
fpu->xfp_regs[i]= 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* do_fpu_inst - Handle reserved instructions for FPU emulation
|
|
|
|
* @inst: instruction code.
|
|
|
|
* @regs: registers on stack.
|
|
|
|
*/
|
|
|
|
int do_fpu_inst(unsigned short inst, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct task_struct *tsk = current;
|
2010-01-13 11:51:40 +08:00
|
|
|
struct sh_fpu_soft_struct *fpu = &(tsk->thread.xstate->softfpu);
|
2006-09-27 16:15:32 +08:00
|
|
|
|
2011-06-27 20:41:57 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
|
2010-10-13 05:55:26 +08:00
|
|
|
|
sh: Minor optimisations to FPU handling
A number of small optimisations to FPU handling, in particular:
- move the task USEDFPU flag from the thread_info flags field (which
is accessed asynchronously to the thread) to a new status field,
which is only accessed by the thread itself. This allows locking to
be removed in most cases, or can be reduced to a preempt_lock().
This mimics the i386 behaviour.
- move the modification of regs->sr and thread_info->status flags out
of save_fpu() to __unlazy_fpu(). This gives the compiler a better
chance to optimise things, as well as making save_fpu() symmetrical
with restore_fpu() and init_fpu().
- implement prepare_to_copy(), so that when creating a thread, we can
unlazy the FPU prior to copying the thread data structures.
Also make sure that the FPU is disabled while in the kernel, in
particular while booting, and for newly created kernel threads,
In a very artificial benchmark, the execution time for 2500000
context switches was reduced from 50 to 45 seconds.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-09-26 01:25:10 +08:00
|
|
|
if (!(task_thread_info(tsk)->status & TS_USEDFPU)) {
|
2006-09-27 16:15:32 +08:00
|
|
|
/* initialize once. */
|
|
|
|
fpu_init(fpu);
|
sh: Minor optimisations to FPU handling
A number of small optimisations to FPU handling, in particular:
- move the task USEDFPU flag from the thread_info flags field (which
is accessed asynchronously to the thread) to a new status field,
which is only accessed by the thread itself. This allows locking to
be removed in most cases, or can be reduced to a preempt_lock().
This mimics the i386 behaviour.
- move the modification of regs->sr and thread_info->status flags out
of save_fpu() to __unlazy_fpu(). This gives the compiler a better
chance to optimise things, as well as making save_fpu() symmetrical
with restore_fpu() and init_fpu().
- implement prepare_to_copy(), so that when creating a thread, we can
unlazy the FPU prior to copying the thread data structures.
Also make sure that the FPU is disabled while in the kernel, in
particular while booting, and for newly created kernel threads,
In a very artificial benchmark, the execution time for 2500000
context switches was reduced from 50 to 45 seconds.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-09-26 01:25:10 +08:00
|
|
|
task_thread_info(tsk)->status |= TS_USEDFPU;
|
2006-09-27 16:15:32 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return fpu_emulate(inst, fpu, regs);
|
|
|
|
}
|