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OpenCloudOS-Kernel/drivers/clk/renesas/r9a07g044-cpg.c

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clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G2L CPG driver
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
#include <dt-bindings/clock/r9a07g054-cpg.h>
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] Rename renesas-rzg2l-cpg.c and renesas-rzg2l-cpg.h to rzg2l-cpg.c resp. rzg2l-cpg.h, for consistency with other (sub)drivers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/edc442daaedffcf10e835ff479d906fcae0e59db.1626268821.git.geert+renesas@glider.be
2021-07-14 21:26:01 +08:00
#include "rzg2l-cpg.h"
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
enum clk_ids {
/* Core Clock Outputs exported to DT */
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_OSC_DIV1000,
CLK_PLL1,
CLK_PLL2,
CLK_PLL2_DIV2,
clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match the clock tree mentioned in the hardware manual(Rev.1.00 Sep, 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211110082019.28554-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-10 16:20:18 +08:00
CLK_PLL2_DIV2_8,
CLK_PLL2_DIV2_10,
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
CLK_PLL3,
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-28 21:01:32 +08:00
CLK_PLL3_400,
CLK_PLL3_533,
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
CLK_PLL3_DIV2,
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree mentioned in the hardware manual(Rev.1.00 Sep, 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-03 19:51:49 +08:00
CLK_PLL3_DIV2_2,
clk: renesas: r9a07g044: Fix P1 Clock As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4. So fix the clock definitions for P1. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:37 +08:00
CLK_PLL3_DIV2_4,
clk: renesas: r9a07g044: Add P2 Clock support Add support for P2 clock which is sourced from pll3_div2_4_2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:38 +08:00
CLK_PLL3_DIV2_4_2,
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-28 21:01:32 +08:00
CLK_SEL_PLL3_3,
CLK_DIV_PLL3_C,
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
CLK_PLL4,
CLK_PLL5,
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
CLK_PLL5_FOUT3,
CLK_PLL5_250,
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
CLK_PLL6,
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
CLK_PLL6_250,
clk: renesas: r9a07g044: Add DMAC clocks/resets Add DMAC clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:43 +08:00
CLK_P1_DIV2,
clk: renesas: r9a07g044: Add SDHI clock and reset entries Add SDHI{0,1} mux, clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-07 19:14:34 +08:00
CLK_PLL2_800,
CLK_PLL2_SDHI_533,
CLK_PLL2_SDHI_400,
CLK_PLL2_SDHI_266,
CLK_SD0_DIV4,
CLK_SD1_DIV4,
clk: renesas: r9a07g044: Add mux and divider for G clock G clock is sourced from PLL3 and PLL6. The output of the mux is connected to divider. This patch adds a mux and divider for getting different rates from this clock sources. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-03 19:51:50 +08:00
CLK_SEL_GPU2,
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
/* Module Clocks */
MOD_CLK_BASE,
};
/* Divider tables */
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual Rev.1.00. This patch adds clock divider table "dtable_1_8" and switches to DEF_DIV for "I" clock. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211112081003.15453-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-12 16:10:01 +08:00
static const struct clk_div_table dtable_1_8[] = {
{0, 1},
{1, 2},
{2, 4},
{3, 8},
{0, 0},
};
clk: renesas: r9a07g044: Rename divider table As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it can be reused. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:36 +08:00
static const struct clk_div_table dtable_1_32[] = {
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
{0, 1},
{1, 2},
{2, 4},
{3, 8},
{4, 32},
clk: renesas: r9a07g044: Rename divider table As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it can be reused. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:36 +08:00
{0, 0},
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
};
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
/* Mux clock tables */
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-28 21:01:32 +08:00
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
clk: renesas: r9a07g044: Add SDHI clock and reset entries Add SDHI{0,1} mux, clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-07 19:14:34 +08:00
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
clk: renesas: r9a07g044: Add mux and divider for G clock G clock is sourced from PLL3 and PLL6. The output of the mux is connected to divider. This patch adds a mux and divider for getting different rates from this clock sources. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-03 19:51:50 +08:00
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
static const struct {
struct cpg_core_clk common[44];
#ifdef CONFIG_CLK_R9A07G054
struct cpg_core_clk drp[0];
#endif
} core_clks __initconst = {
.common = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
/* Internal Core Clocks */
DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
clk: renesas: r9a07g044: Add SDHI clock and reset entries Add SDHI{0,1} mux, clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-07 19:14:34 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
clk: renesas: r9a07g044: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:43 +08:00
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
/* Core output clk */
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
CLK_DIVIDER_HIWORD_MASK),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
sel_shdi, ARRAY_SIZE(sel_shdi)),
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
sel_shdi, ARRAY_SIZE(sel_shdi)),
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
CLK_DIVIDER_HIWORD_MASK),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
},
#endif
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
};
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
static const struct {
struct rzg2l_mod_clk common[62];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
} mod_clks = {
.common = {
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
0x514, 0),
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
0x518, 0),
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
0x518, 1),
DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
0x52c, 0),
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
0x52c, 1),
DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
0x534, 0),
DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
0x534, 1),
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
0x534, 2),
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
0x548, 1),
DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
0x548, 2),
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
0x548, 3),
DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
0x548, 4),
DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
0x548, 5),
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
0x550, 0),
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
0x550, 1),
DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
0x554, 0),
DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
0x554, 1),
DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
0x554, 2),
DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
0x554, 3),
DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
0x554, 4),
DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
0x554, 5),
DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
0x554, 6),
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
0x554, 7),
DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
0x558, 0),
DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
0x558, 1),
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
0x558, 2),
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
0x570, 0),
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 1),
DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
0x570, 2),
DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 3),
DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
0x570, 4),
DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 5),
DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
0x570, 6),
DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 7),
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
0x578, 0),
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
0x578, 1),
DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
0x578, 2),
DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
0x578, 3),
DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
0x57c, 0),
DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
0x57c, 0),
DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
0x57c, 1),
DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
0x57c, 1),
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
0x580, 0),
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
0x580, 1),
DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
0x580, 2),
DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
0x580, 3),
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
0x584, 0),
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
0x584, 1),
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
0x584, 2),
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
0x584, 3),
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
0x584, 4),
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
0x588, 0),
DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
0x588, 1),
DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
0x590, 0),
DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
0x590, 1),
DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
0x590, 2),
DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
0x594, 0),
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
0x598, 0),
DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
0x5a8, 0),
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
0x5a8, 1),
DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
0x5ac, 0),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
},
#endif
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx and RZ/G2L HW(Rev.0.50) manual. Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and separate reset from module clocks in order to handle them efficiently. Update the SCIF0 clock and reset index in the SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com [geert: Squashed 3 commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:39 +08:00
};
static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
clk: renesas: r9a07g044: Add DMAC clocks/resets Add DMAC clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:43 +08:00
DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
clk: renesas: r9a07g044: Add OSTM clock and reset entries Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211110082019.28554-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-10 16:20:19 +08:00
DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
clk: renesas: r9a07g044: Add WDT clock and reset entries Add WDT{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211104160858.15550-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-05 00:08:57 +08:00
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-28 21:01:32 +08:00
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
clk: renesas: r9a07g044: Add SDHI clock and reset entries Add SDHI{0,1} mux, clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-07 19:14:34 +08:00
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
clk: renesas: r9a07g044: Add GPU clock and reset entries Add GPU clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-03 19:51:51 +08:00
DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries Add SSIF-2 clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210702135010.5937-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-02 21:50:03 +08:00
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
clk: renesas: r9a07g044: Add USB clocks/resets Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210630073013.22415-5-biju.das.jz@bp.renesas.com [geert: s/usb0_device/usb0_func] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-30 15:30:06 +08:00
DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
clk: renesas: r9a07g044: Add GbEthernet clock/reset Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 23:51:45 +08:00
DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
clk: renesas: r9a07g044: Add I2C clocks/resets Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:42 +08:00
DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx and RZ/G2L HW(Rev.0.50) manual. Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and separate reset from module clocks in order to handle them efficiently. Update the SCIF0 clock and reset index in the SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com [geert: Squashed 3 commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:39 +08:00
DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
clk: renesas: r9a07g044: Add clock and reset entry for SCI1 Add clock and reset entry for SCI1 interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-04 00:05:37 +08:00
DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
clk: renesas: r9a07g044: Add RSPI clock and reset entries Add RSPI{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211117002601.17971-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-17 08:26:01 +08:00
DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
clk: renesas: r9a07g044: Add clock and reset entries for CANFD Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210715182123.23372-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-16 02:21:22 +08:00
DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
clk: renesas: r9a07g044: Add GPIO clock and reset entries Add GPIO clock and reset entries in CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210712194422.12405-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-13 03:44:20 +08:00
DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
clk: renesas: r9a07g044: Add clock and reset entries for ADC Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210719085840.21842-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-19 16:58:39 +08:00
DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
clk: renesas: r9a07g044: Add TSU clock and reset entry Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211120180438.8351-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-21 02:04:38 +08:00
DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
};
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx and RZ/G2L HW(Rev.0.50) manual. Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and separate reset from module clocks in order to handle them efficiently. Update the SCIF0 clock and reset index in the SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com [geert: Squashed 3 commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:39 +08:00
MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical Add IA55_CLK and DMAC_ACLK as critical clocks. Previously it worked ok, because of a bug in clock status function and the following patch in this series fixes the original bug. Fixes: c3e67ad6f5a2 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions") Fixes: eb829e549ba6 ("clk: renesas: r9a07g044: Add DMAC clocks/resets") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922112405.26413-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-22 19:24:04 +08:00
MOD_CLK_BASE + R9A07G044_IA55_CLK,
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
};
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
/* Core Clocks */
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
.core_clks = core_clks.common,
.num_core_clks = ARRAY_SIZE(core_clks.common),
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Critical Module Clocks */
.crit_mod_clks = r9a07g044_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
/* Module Clocks */
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
.mod_clks = mod_clks.common,
.num_mod_clks = ARRAY_SIZE(mod_clks.common),
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx and RZ/G2L HW(Rev.0.50) manual. Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and separate reset from module clocks in order to handle them efficiently. Update the SCIF0 clock and reset index in the SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com [geert: Squashed 3 commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-26 16:13:39 +08:00
.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
/* Resets */
.resets = r9a07g044_resets,
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
};
#ifdef CONFIG_CLK_R9A07G054
const struct rzg2l_cpg_info r9a07g054_cpg_info = {
/* Core Clocks */
.core_clks = core_clks.common,
.num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Critical Module Clocks */
.crit_mod_clks = r9a07g044_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
/* Module Clocks */
.mod_clks = mod_clks.common,
.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
/* Resets */
.resets = r9a07g044_resets,
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
clk: renesas: Add support for R9A07G044 SoC Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-09 23:32:28 +08:00
};
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-05 16:40:06 +08:00
#endif