2005-04-17 06:20:36 +08:00
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/*
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2005-08-29 08:18:39 +08:00
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* ata_piix.c - Intel PATA/SATA controllers
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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*
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* Copyright 2003-2005 Red Hat Inc
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* Copyright 2003-2005 Jeff Garzik
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*
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*
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* Copyright header from piix.c:
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*
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* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available at http://developer.intel.com/
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*
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2005-12-09 03:19:50 +08:00
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* Documentation
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* Publically available from Intel web site. Errata documentation
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* is also publically available. As an aide to anyone hacking on this
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2006-12-05 00:33:20 +08:00
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* driver the list of errata that are relevant is below, going back to
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2005-12-09 03:19:50 +08:00
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* PIIX4. Older device documentation is now a bit tricky to find.
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*
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* The chipsets all follow very much the same design. The orginal Triton
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* series chipsets do _not_ support independant device timings, but this
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* is fixed in Triton II. With the odd mobile exception the chips then
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* change little except in gaining more modes until SATA arrives. This
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* driver supports only the chips with independant timing (that is those
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* with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
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* for the early chip drivers.
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*
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* Errata of note:
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*
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* Unfixable
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* PIIX4 errata #9 - Only on ultra obscure hw
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* ICH3 errata #13 - Not observed to affect real hw
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* by Intel
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*
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* Things we must deal with
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* PIIX4 errata #10 - BM IDE hang with non UDMA
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* (must stop/start dma to recover)
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* 440MX errata #15 - As PIIX4 errata #10
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* PIIX4 errata #15 - Must not read control registers
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* during a PIO transfer
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* 440MX errata #13 - As PIIX4 errata #15
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* ICH2 errata #21 - DMA mode 0 doesn't work right
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* ICH0/1 errata #55 - As ICH2 errata #21
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* ICH2 spec c #9 - Extra operations needed to handle
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* drive hotswap [NOT YET SUPPORTED]
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* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
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* and must be dword aligned
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* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
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*
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* Should have been BIOS fixed:
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* 450NX: errata #19 - DMA hangs on old 450NX
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* 450NX: errata #20 - DMA hangs on old 450NX
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* 450NX: errata #25 - Corruption with DMA on old 450NX
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* ICH3 errata #15 - IDE deadlock under high load
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* (BIOS must set dev 31 fn 0 bit 23)
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* ICH3 errata #18 - Don't use native mode
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2005-04-17 06:20:36 +08:00
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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2005-10-30 19:42:18 +08:00
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#include <linux/device.h>
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2005-04-17 06:20:36 +08:00
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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2007-07-10 14:55:43 +08:00
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#include <linux/dmi.h>
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2005-04-17 06:20:36 +08:00
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#define DRV_NAME "ata_piix"
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2007-08-31 16:54:06 +08:00
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#define DRV_VERSION "2.12"
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2005-04-17 06:20:36 +08:00
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enum {
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PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
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ICH5_PMR = 0x90, /* port mapping register */
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ICH5_PCS = 0x92, /* port control and status */
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2005-07-29 03:54:15 +08:00
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PIIX_SCC = 0x0A, /* sub-class code register */
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2005-04-17 06:20:36 +08:00
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2006-03-01 00:25:39 +08:00
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PIIX_FLAG_SCR = (1 << 26), /* SCR available */
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[PATCH] ata_piix: fix MAP VALUE interpretation for for ICH6/7
Unlike their older siblings, ICH6 and 7 use different scheme for MAP
VALUE. This patch makes ata_piix interpret MV properly on ICH6/7.
Pre-ICH6/7
The value of these bits indicate the address range the SATA port
responds to, and whether or not the SATA and IDE functions are
combined.
000 = Non-combined. P0 is primary master. P1 is secondary master.
001 = Non-combined. P0 is secondary master. P1 is primary master.
100 = Combined. P0 is primary master. P1 is primary slave. P-ATA is
2:0 Map Value secondary.
101 = Combined. P0 is primary slave. P1 is primary master. P-ATA is
secondary.
110 = Combined. P-ATA is primary. P0 is secondary master. P1 is
secondary slave.
111 = Combined. P-ATA is primary. P0 is secondary slave. P1 is
secondary master.
ICH6/7
Map Value - R/W. Map Value (MV): The value in the bits below indicate
the address range the SATA ports responds to, and whether or not the
PATA and SATA functions are combined. When in combined mode, the AHCI
memory space is not available and AHCI may not be used.
00 = Non-combined. P0 is primary master, P2 is the primary slave. P1
is secondary master, P3 is the 1:0 secondary slave (desktop
only). P0 is primary master, P2 is the primary slave (mobile
only).
01 = Combined. IDE is primary. P1 is secondary master, P3 is the
secondary slave. (desktop only)
10 = Combined. P0 is primary master. P2 is primary slave. IDE is secondary
11 = Reserved
Signed-off-by: Tejun Heo <htejun@gmail.com>
--
Jeff, without this patch, ata_piix misdetects my ICH7's combined mode,
ending up not applying bridge limits to PX-710SA and configuring IDE
drive on 40-c cable to UDMA/66.
Thanks.
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2005-12-18 16:17:07 +08:00
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PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
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PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
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2005-04-17 06:20:36 +08:00
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2006-12-03 20:34:13 +08:00
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PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
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PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
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2006-11-10 17:08:10 +08:00
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2005-04-17 06:20:36 +08:00
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/* combined mode. if set, PATA is channel 0.
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* if clear, PATA is channel 1.
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*/
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2005-06-29 08:30:38 +08:00
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PIIX_PORT_ENABLED = (1 << 0),
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PIIX_PORT_PRESENT = (1 << 4),
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2005-04-17 06:20:36 +08:00
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PIIX_80C_PRI = (1 << 5) | (1 << 4),
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PIIX_80C_SEC = (1 << 7) | (1 << 6),
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2006-03-01 00:25:39 +08:00
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/* controller IDs */
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2007-11-19 10:24:25 +08:00
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piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
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piix_pata_33, /* PIIX4 at 33Mhz */
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ich_pata_33, /* ICH up to UDMA 33 only */
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ich_pata_66, /* ICH up to 66 Mhz */
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ich_pata_100, /* ICH up to UDMA 100 */
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ich5_sata,
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ich6_sata,
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ich6_sata_ahci,
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ich6m_sata_ahci,
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ich8_sata_ahci,
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ich8_2port_sata,
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2007-11-19 10:54:24 +08:00
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ich8m_apple_sata_ahci, /* locks up on second port enable */
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2007-11-19 10:24:25 +08:00
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tolapai_sata_ahci,
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2008-01-07 18:38:53 +08:00
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piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
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2006-08-31 12:03:49 +08:00
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2006-03-01 00:25:39 +08:00
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/* constants for mapping table */
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P0 = 0, /* port 0 */
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P1 = 1, /* port 1 */
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P2 = 2, /* port 2 */
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P3 = 3, /* port 3 */
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IDE = -1, /* IDE */
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NA = -2, /* not avaliable */
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RV = -3, /* reserved */
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2005-07-29 03:54:15 +08:00
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PIIX_AHCI_DEVICE = 6,
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2007-07-10 14:55:43 +08:00
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/* host->flags bits */
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PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
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2005-04-17 06:20:36 +08:00
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};
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2006-03-01 00:25:39 +08:00
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struct piix_map_db {
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const u32 mask;
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2006-07-12 01:11:17 +08:00
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const u16 port_enable;
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2006-03-01 00:25:39 +08:00
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const int map[][4];
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};
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2006-06-29 00:58:28 +08:00
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struct piix_host_priv {
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const int *map;
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};
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2007-10-19 18:42:56 +08:00
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static int piix_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent);
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2006-05-31 17:28:14 +08:00
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static void piix_pata_error_handler(struct ata_port *ap);
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2007-10-19 18:42:56 +08:00
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static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
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static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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2007-04-11 07:04:20 +08:00
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static int ich_pata_cable_detect(struct ata_port *ap);
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2008-01-07 18:38:53 +08:00
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static u8 piix_vmw_bmdma_status(struct ata_port *ap);
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2007-07-10 14:55:43 +08:00
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#ifdef CONFIG_PM
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static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
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static int piix_pci_device_resume(struct pci_dev *pdev);
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#endif
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2005-04-17 06:20:36 +08:00
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static unsigned int in_module_init = 1;
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2005-11-11 00:04:11 +08:00
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static const struct pci_device_id piix_pci_tbl[] = {
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2007-01-11 01:13:38 +08:00
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/* Intel PIIX3 for the 430HX etc */
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{ 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
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2008-01-07 18:38:53 +08:00
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/* VMware ICH4 */
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{ 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
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2006-08-30 06:12:40 +08:00
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/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
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/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
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{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
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/* Intel PIIX4 */
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{ 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
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/* Intel PIIX4 */
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{ 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
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/* Intel PIIX */
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{ 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
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/* Intel ICH (i810, i815, i840) UDMA 66*/
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{ 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
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/* Intel ICH0 : UDMA 33*/
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{ 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
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/* Intel ICH2M */
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{ 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
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{ 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* Intel ICH3M */
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{ 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* Intel ICH3 (E7500/1) UDMA 100 */
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{ 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
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{ 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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{ 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* Intel ICH5 */
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2007-08-11 04:59:51 +08:00
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{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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2006-08-30 06:12:40 +08:00
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/* C-ICH (i810E2) */
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{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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2006-08-31 12:03:49 +08:00
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/* ESB (855GME/875P + 6300ESB) UDMA 100 */
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2006-08-30 06:12:40 +08:00
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{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* ICH6 (and 6) (i915) UDMA 100 */
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{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* ICH7/7-R (i945, i975) UDMA 100*/
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2007-08-11 04:59:51 +08:00
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{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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2006-08-30 06:12:40 +08:00
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{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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2007-07-03 22:19:20 +08:00
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/* ICH8 Mobile PATA Controller */
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{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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2005-04-17 06:20:36 +08:00
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/* NOTE: The following PCI ids must be kept in sync with the
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* list in drivers/pci/quirks.c.
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*/
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2006-03-01 00:25:39 +08:00
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/* 82801EB (ICH5) */
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2005-04-17 06:20:36 +08:00
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{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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2006-03-01 00:25:39 +08:00
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/* 82801EB (ICH5) */
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2005-04-17 06:20:36 +08:00
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{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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2006-03-01 00:25:39 +08:00
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/* 6300ESB (ICH5 variant with broken PCS present bits) */
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2006-11-10 17:08:10 +08:00
|
|
|
{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 6300ESB pretending RAID */
|
2006-11-10 17:08:10 +08:00
|
|
|
{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801FB/FW (ICH6/ICH6W) */
|
2005-04-17 06:20:36 +08:00
|
|
|
{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801FR/FRW (ICH6R/ICH6RW) */
|
2005-11-15 07:20:23 +08:00
|
|
|
{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
|
|
|
|
|
{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
|
|
|
|
|
/* 82801GB/GR/GH (ICH7, identical to ICH6) */
|
2005-11-15 07:20:23 +08:00
|
|
|
{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
|
2006-10-09 12:23:58 +08:00
|
|
|
{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* Enterprise Southbridge 2 (631xESB/632xESB) */
|
2005-11-15 07:20:23 +08:00
|
|
|
{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller 1 IDE (ICH8) */
|
2006-07-11 23:57:44 +08:00
|
|
|
{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller 2 IDE (ICH8) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* Mobile SATA Controller IDE (ICH8M) */
|
2006-07-11 23:57:44 +08:00
|
|
|
{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
|
2007-11-19 10:54:24 +08:00
|
|
|
/* Mobile SATA Controller IDE (ICH8M), Apple */
|
|
|
|
|
{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9) */
|
|
|
|
|
{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
|
|
|
|
|
/* SATA Controller IDE (ICH9) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9M) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9M) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9M) */
|
|
|
|
|
{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
|
2007-08-31 12:36:56 +08:00
|
|
|
/* SATA Controller IDE (Tolapai) */
|
|
|
|
|
{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
{ } /* terminate list */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct pci_driver piix_pci_driver = {
|
|
|
|
|
.name = DRV_NAME,
|
|
|
|
|
.id_table = piix_pci_tbl,
|
|
|
|
|
.probe = piix_init_one,
|
|
|
|
|
.remove = ata_pci_remove_one,
|
2007-03-02 16:31:26 +08:00
|
|
|
#ifdef CONFIG_PM
|
2007-07-10 14:55:43 +08:00
|
|
|
.suspend = piix_pci_device_suspend,
|
|
|
|
|
.resume = piix_pci_device_resume,
|
2007-03-02 16:31:26 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
|
2005-11-07 13:59:37 +08:00
|
|
|
static struct scsi_host_template piix_sht = {
|
2005-04-17 06:20:36 +08:00
|
|
|
.module = THIS_MODULE,
|
|
|
|
|
.name = DRV_NAME,
|
|
|
|
|
.ioctl = ata_scsi_ioctl,
|
|
|
|
|
.queuecommand = ata_scsi_queuecmd,
|
|
|
|
|
.can_queue = ATA_DEF_QUEUE,
|
|
|
|
|
.this_id = ATA_SHT_THIS_ID,
|
|
|
|
|
.sg_tablesize = LIBATA_MAX_PRD,
|
|
|
|
|
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
|
|
|
|
.emulated = ATA_SHT_EMULATED,
|
|
|
|
|
.use_clustering = ATA_SHT_USE_CLUSTERING,
|
|
|
|
|
.proc_name = DRV_NAME,
|
|
|
|
|
.dma_boundary = ATA_DMA_BOUNDARY,
|
|
|
|
|
.slave_configure = ata_scsi_slave_config,
|
2006-05-31 17:28:09 +08:00
|
|
|
.slave_destroy = ata_scsi_slave_destroy,
|
2005-04-17 06:20:36 +08:00
|
|
|
.bios_param = ata_std_bios_param,
|
|
|
|
|
};
|
|
|
|
|
|
2005-10-23 02:27:05 +08:00
|
|
|
static const struct ata_port_operations piix_pata_ops = {
|
2005-04-17 06:20:36 +08:00
|
|
|
.set_piomode = piix_set_piomode,
|
|
|
|
|
.set_dmamode = piix_set_dmamode,
|
2006-05-26 13:49:18 +08:00
|
|
|
.mode_filter = ata_pci_default_filter,
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
.tf_load = ata_tf_load,
|
|
|
|
|
.tf_read = ata_tf_read,
|
|
|
|
|
.check_status = ata_check_status,
|
|
|
|
|
.exec_command = ata_exec_command,
|
|
|
|
|
.dev_select = ata_std_dev_select,
|
|
|
|
|
|
|
|
|
|
.bmdma_setup = ata_bmdma_setup,
|
|
|
|
|
.bmdma_start = ata_bmdma_start,
|
|
|
|
|
.bmdma_stop = ata_bmdma_stop,
|
|
|
|
|
.bmdma_status = ata_bmdma_status,
|
|
|
|
|
.qc_prep = ata_qc_prep,
|
|
|
|
|
.qc_issue = ata_qc_issue_prot,
|
2007-02-01 14:06:36 +08:00
|
|
|
.data_xfer = ata_data_xfer,
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-05-15 19:58:25 +08:00
|
|
|
.freeze = ata_bmdma_freeze,
|
|
|
|
|
.thaw = ata_bmdma_thaw,
|
2006-05-31 17:28:14 +08:00
|
|
|
.error_handler = piix_pata_error_handler,
|
2006-05-15 19:58:25 +08:00
|
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
2007-04-11 07:04:20 +08:00
|
|
|
.cable_detect = ata_cable_40wire,
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
.irq_handler = ata_interrupt,
|
|
|
|
|
.irq_clear = ata_bmdma_irq_clear,
|
2007-01-26 15:27:58 +08:00
|
|
|
.irq_on = ata_irq_on,
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
.port_start = ata_port_start,
|
|
|
|
|
};
|
|
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
static const struct ata_port_operations ich_pata_ops = {
|
|
|
|
|
.set_piomode = piix_set_piomode,
|
|
|
|
|
.set_dmamode = ich_set_dmamode,
|
|
|
|
|
.mode_filter = ata_pci_default_filter,
|
|
|
|
|
|
|
|
|
|
.tf_load = ata_tf_load,
|
|
|
|
|
.tf_read = ata_tf_read,
|
|
|
|
|
.check_status = ata_check_status,
|
|
|
|
|
.exec_command = ata_exec_command,
|
|
|
|
|
.dev_select = ata_std_dev_select,
|
|
|
|
|
|
|
|
|
|
.bmdma_setup = ata_bmdma_setup,
|
|
|
|
|
.bmdma_start = ata_bmdma_start,
|
|
|
|
|
.bmdma_stop = ata_bmdma_stop,
|
|
|
|
|
.bmdma_status = ata_bmdma_status,
|
|
|
|
|
.qc_prep = ata_qc_prep,
|
|
|
|
|
.qc_issue = ata_qc_issue_prot,
|
2007-02-01 14:06:36 +08:00
|
|
|
.data_xfer = ata_data_xfer,
|
2006-08-30 06:12:40 +08:00
|
|
|
|
|
|
|
|
.freeze = ata_bmdma_freeze,
|
|
|
|
|
.thaw = ata_bmdma_thaw,
|
2007-04-11 07:04:20 +08:00
|
|
|
.error_handler = piix_pata_error_handler,
|
2006-08-30 06:12:40 +08:00
|
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
2007-04-11 07:04:20 +08:00
|
|
|
.cable_detect = ich_pata_cable_detect,
|
2006-08-30 06:12:40 +08:00
|
|
|
|
|
|
|
|
.irq_handler = ata_interrupt,
|
|
|
|
|
.irq_clear = ata_bmdma_irq_clear,
|
2007-01-26 15:27:58 +08:00
|
|
|
.irq_on = ata_irq_on,
|
2006-08-30 06:12:40 +08:00
|
|
|
|
|
|
|
|
.port_start = ata_port_start,
|
|
|
|
|
};
|
|
|
|
|
|
2005-10-23 02:27:05 +08:00
|
|
|
static const struct ata_port_operations piix_sata_ops = {
|
2005-04-17 06:20:36 +08:00
|
|
|
.tf_load = ata_tf_load,
|
|
|
|
|
.tf_read = ata_tf_read,
|
|
|
|
|
.check_status = ata_check_status,
|
|
|
|
|
.exec_command = ata_exec_command,
|
|
|
|
|
.dev_select = ata_std_dev_select,
|
|
|
|
|
|
|
|
|
|
.bmdma_setup = ata_bmdma_setup,
|
|
|
|
|
.bmdma_start = ata_bmdma_start,
|
|
|
|
|
.bmdma_stop = ata_bmdma_stop,
|
|
|
|
|
.bmdma_status = ata_bmdma_status,
|
|
|
|
|
.qc_prep = ata_qc_prep,
|
|
|
|
|
.qc_issue = ata_qc_issue_prot,
|
2007-02-01 14:06:36 +08:00
|
|
|
.data_xfer = ata_data_xfer,
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-05-15 19:58:25 +08:00
|
|
|
.freeze = ata_bmdma_freeze,
|
|
|
|
|
.thaw = ata_bmdma_thaw,
|
2007-05-21 22:15:51 +08:00
|
|
|
.error_handler = ata_bmdma_error_handler,
|
2006-05-15 19:58:25 +08:00
|
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
.irq_handler = ata_interrupt,
|
|
|
|
|
.irq_clear = ata_bmdma_irq_clear,
|
2007-01-26 15:27:58 +08:00
|
|
|
.irq_on = ata_irq_on,
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
.port_start = ata_port_start,
|
|
|
|
|
};
|
|
|
|
|
|
2008-01-07 18:38:53 +08:00
|
|
|
static const struct ata_port_operations piix_vmw_ops = {
|
|
|
|
|
.set_piomode = piix_set_piomode,
|
|
|
|
|
.set_dmamode = piix_set_dmamode,
|
|
|
|
|
.mode_filter = ata_pci_default_filter,
|
|
|
|
|
|
|
|
|
|
.tf_load = ata_tf_load,
|
|
|
|
|
.tf_read = ata_tf_read,
|
|
|
|
|
.check_status = ata_check_status,
|
|
|
|
|
.exec_command = ata_exec_command,
|
|
|
|
|
.dev_select = ata_std_dev_select,
|
|
|
|
|
|
|
|
|
|
.bmdma_setup = ata_bmdma_setup,
|
|
|
|
|
.bmdma_start = ata_bmdma_start,
|
|
|
|
|
.bmdma_stop = ata_bmdma_stop,
|
|
|
|
|
.bmdma_status = piix_vmw_bmdma_status,
|
|
|
|
|
.qc_prep = ata_qc_prep,
|
|
|
|
|
.qc_issue = ata_qc_issue_prot,
|
|
|
|
|
.data_xfer = ata_data_xfer,
|
|
|
|
|
|
|
|
|
|
.freeze = ata_bmdma_freeze,
|
|
|
|
|
.thaw = ata_bmdma_thaw,
|
|
|
|
|
.error_handler = piix_pata_error_handler,
|
|
|
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
|
|
|
|
.cable_detect = ata_cable_40wire,
|
|
|
|
|
|
|
|
|
|
.irq_handler = ata_interrupt,
|
|
|
|
|
.irq_clear = ata_bmdma_irq_clear,
|
|
|
|
|
.irq_on = ata_irq_on,
|
|
|
|
|
|
|
|
|
|
.port_start = ata_port_start,
|
|
|
|
|
};
|
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db ich5_map_db = {
|
2006-03-01 00:25:39 +08:00
|
|
|
.mask = 0x7,
|
2006-07-11 23:48:50 +08:00
|
|
|
.port_enable = 0x3,
|
2006-03-01 00:25:39 +08:00
|
|
|
.map = {
|
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
|
{ P0, NA, P1, NA }, /* 000b */
|
|
|
|
|
{ P1, NA, P0, NA }, /* 001b */
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
{ P0, P1, IDE, IDE }, /* 100b */
|
|
|
|
|
{ P1, P0, IDE, IDE }, /* 101b */
|
|
|
|
|
{ IDE, IDE, P0, P1 }, /* 110b */
|
|
|
|
|
{ IDE, IDE, P1, P0 }, /* 111b */
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db ich6_map_db = {
|
2006-03-01 00:25:39 +08:00
|
|
|
.mask = 0x3,
|
2006-07-11 23:48:50 +08:00
|
|
|
.port_enable = 0xf,
|
2006-03-01 00:25:39 +08:00
|
|
|
.map = {
|
|
|
|
|
/* PM PS SM SS MAP */
|
2006-03-31 19:01:50 +08:00
|
|
|
{ P0, P2, P1, P3 }, /* 00b */
|
2006-03-01 00:25:39 +08:00
|
|
|
{ IDE, IDE, P1, P3 }, /* 01b */
|
|
|
|
|
{ P0, P2, IDE, IDE }, /* 10b */
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db ich6m_map_db = {
|
2006-03-01 00:25:39 +08:00
|
|
|
.mask = 0x3,
|
2006-07-11 23:48:50 +08:00
|
|
|
.port_enable = 0x5,
|
2006-09-11 05:29:03 +08:00
|
|
|
|
|
|
|
|
/* Map 01b isn't specified in the doc but some notebooks use
|
2006-10-09 12:23:58 +08:00
|
|
|
* it anyway. MAP 01b have been spotted on both ICH6M and
|
|
|
|
|
* ICH7M.
|
2006-09-11 05:29:03 +08:00
|
|
|
*/
|
|
|
|
|
.map = {
|
|
|
|
|
/* PM PS SM SS MAP */
|
2007-07-10 16:58:21 +08:00
|
|
|
{ P0, P2, NA, NA }, /* 00b */
|
2006-09-11 05:29:03 +08:00
|
|
|
{ IDE, IDE, P1, P3 }, /* 01b */
|
|
|
|
|
{ P0, P2, IDE, IDE }, /* 10b */
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2006-07-11 23:57:44 +08:00
|
|
|
static const struct piix_map_db ich8_map_db = {
|
|
|
|
|
.mask = 0x3,
|
2007-11-19 11:06:37 +08:00
|
|
|
.port_enable = 0xf,
|
2006-07-11 23:57:44 +08:00
|
|
|
.map = {
|
|
|
|
|
/* PM PS SM SS MAP */
|
2006-10-20 04:27:39 +08:00
|
|
|
{ P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
|
2006-07-11 23:57:44 +08:00
|
|
|
{ RV, RV, RV, RV },
|
2007-08-07 01:43:27 +08:00
|
|
|
{ P0, P2, IDE, IDE }, /* 10b (IDE mode) */
|
2006-07-11 23:57:44 +08:00
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2007-11-19 10:24:25 +08:00
|
|
|
static const struct piix_map_db ich8_2port_map_db = {
|
2007-09-08 08:21:03 +08:00
|
|
|
.mask = 0x3,
|
|
|
|
|
.port_enable = 0x3,
|
|
|
|
|
.map = {
|
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
|
{ P0, NA, P1, NA }, /* 00b */
|
|
|
|
|
{ RV, RV, RV, RV }, /* 01b */
|
|
|
|
|
{ RV, RV, RV, RV }, /* 10b */
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
},
|
2007-08-31 12:36:56 +08:00
|
|
|
};
|
|
|
|
|
|
2007-11-19 10:54:24 +08:00
|
|
|
static const struct piix_map_db ich8m_apple_map_db = {
|
|
|
|
|
.mask = 0x3,
|
|
|
|
|
.port_enable = 0x1,
|
|
|
|
|
.map = {
|
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
|
{ P0, NA, NA, NA }, /* 00b */
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
{ P0, P2, IDE, IDE }, /* 10b */
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2007-11-19 10:24:25 +08:00
|
|
|
static const struct piix_map_db tolapai_map_db = {
|
2007-10-12 07:05:15 +08:00
|
|
|
.mask = 0x3,
|
|
|
|
|
.port_enable = 0x3,
|
|
|
|
|
.map = {
|
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
|
{ P0, NA, P1, NA }, /* 00b */
|
|
|
|
|
{ RV, RV, RV, RV }, /* 01b */
|
|
|
|
|
{ RV, RV, RV, RV }, /* 10b */
|
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db *piix_map_db_table[] = {
|
|
|
|
|
[ich5_sata] = &ich5_map_db,
|
|
|
|
|
[ich6_sata] = &ich6_map_db,
|
|
|
|
|
[ich6_sata_ahci] = &ich6_map_db,
|
|
|
|
|
[ich6m_sata_ahci] = &ich6m_map_db,
|
2006-07-11 23:57:44 +08:00
|
|
|
[ich8_sata_ahci] = &ich8_map_db,
|
2007-11-19 10:24:25 +08:00
|
|
|
[ich8_2port_sata] = &ich8_2port_map_db,
|
2007-11-19 10:54:24 +08:00
|
|
|
[ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
|
2007-08-31 12:36:56 +08:00
|
|
|
[tolapai_sata_ahci] = &tolapai_map_db,
|
2006-06-29 00:58:28 +08:00
|
|
|
};
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static struct ata_port_info piix_port_info[] = {
|
2007-11-19 10:24:25 +08:00
|
|
|
[piix_pata_mwdma] = /* PIIX3 MWDMA only */
|
|
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
|
|
|
|
.flags = PIIX_PATA_FLAGS,
|
|
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
|
|
|
|
|
.port_ops = &piix_pata_ops,
|
|
|
|
|
},
|
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[piix_pata_33] = /* PIIX4 at 33MHz */
|
2006-03-01 00:25:39 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2006-03-01 00:25:39 +08:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
2006-08-30 06:12:40 +08:00
|
|
|
.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
|
2006-03-01 00:25:39 +08:00
|
|
|
.udma_mask = ATA_UDMA_MASK_40C,
|
|
|
|
|
.port_ops = &piix_pata_ops,
|
|
|
|
|
},
|
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2006-08-30 06:12:40 +08:00
|
|
|
.pio_mask = 0x1f, /* pio 0-4 */
|
|
|
|
|
.mwdma_mask = 0x06, /* Check: maybe 0x07 */
|
|
|
|
|
.udma_mask = ATA_UDMA2, /* UDMA33 */
|
|
|
|
|
.port_ops = &ich_pata_ops,
|
|
|
|
|
},
|
2007-09-01 19:17:36 +08:00
|
|
|
|
|
|
|
|
[ich_pata_66] = /* ICH controllers up to 66MHz */
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2006-08-30 06:12:40 +08:00
|
|
|
.pio_mask = 0x1f, /* pio 0-4 */
|
|
|
|
|
.mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
|
|
|
|
|
.udma_mask = ATA_UDMA4,
|
|
|
|
|
.port_ops = &ich_pata_ops,
|
|
|
|
|
},
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich_pata_100] =
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
|
2005-04-17 06:20:36 +08:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x06, /* mwdma1-2 */
|
2006-08-30 06:12:40 +08:00
|
|
|
.udma_mask = ATA_UDMA5, /* udma0-5 */
|
|
|
|
|
.port_ops = &ich_pata_ops,
|
2005-04-17 06:20:36 +08:00
|
|
|
},
|
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich5_sata] =
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS,
|
2005-04-17 06:20:36 +08:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2005-04-17 06:20:36 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich6_sata] =
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
|
2005-04-17 06:20:36 +08:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2005-04-17 06:20:36 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich6_sata_ahci] =
|
2005-04-17 06:24:44 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
|
2006-03-01 00:25:39 +08:00
|
|
|
PIIX_FLAG_AHCI,
|
2005-04-17 06:24:44 +08:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2005-04-17 06:24:44 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
2006-03-01 00:25:39 +08:00
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich6m_sata_ahci] =
|
2006-03-01 00:25:39 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
|
2006-03-01 00:25:39 +08:00
|
|
|
PIIX_FLAG_AHCI,
|
2006-03-01 00:25:39 +08:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2006-03-01 00:25:39 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
2006-07-11 23:57:44 +08:00
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich8_sata_ahci] =
|
2006-07-11 23:57:44 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
|
2006-07-11 23:57:44 +08:00
|
|
|
PIIX_FLAG_AHCI,
|
|
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2006-07-11 23:57:44 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
2006-08-30 06:12:40 +08:00
|
|
|
|
2007-11-19 10:24:25 +08:00
|
|
|
[ich8_2port_sata] =
|
2007-08-31 12:36:56 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
|
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
|
|
|
|
|
PIIX_FLAG_AHCI,
|
|
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
2007-10-12 07:05:15 +08:00
|
|
|
|
2007-11-19 10:24:25 +08:00
|
|
|
[tolapai_sata_ahci] =
|
2007-10-12 07:05:15 +08:00
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
|
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
|
|
|
|
|
PIIX_FLAG_AHCI,
|
|
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
2007-11-19 10:54:24 +08:00
|
|
|
|
|
|
|
|
[ich8m_apple_sata_ahci] =
|
|
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
|
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
|
|
|
|
|
PIIX_FLAG_AHCI,
|
|
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
|
},
|
|
|
|
|
|
2008-01-07 18:38:53 +08:00
|
|
|
[piix_pata_vmw] =
|
|
|
|
|
{
|
|
|
|
|
.sht = &piix_sht,
|
|
|
|
|
.flags = PIIX_PATA_FLAGS,
|
|
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
|
.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
|
|
|
|
|
.udma_mask = ATA_UDMA_MASK_40C,
|
|
|
|
|
.port_ops = &piix_vmw_ops,
|
|
|
|
|
},
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct pci_bits piix_enable_bits[] = {
|
|
|
|
|
{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
|
|
|
|
|
{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
|
|
|
|
|
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
|
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
2006-10-11 05:28:11 +08:00
|
|
|
struct ich_laptop {
|
|
|
|
|
u16 device;
|
|
|
|
|
u16 subvendor;
|
|
|
|
|
u16 subdevice;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* List of laptops that use short cables rather than 80 wire
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static const struct ich_laptop ich_laptop[] = {
|
|
|
|
|
/* devid, subvendor, subdev */
|
|
|
|
|
{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
|
2007-11-06 06:51:09 +08:00
|
|
|
{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
|
2007-01-09 01:26:30 +08:00
|
|
|
{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
|
2007-03-29 09:02:07 +08:00
|
|
|
{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
|
2007-09-29 16:01:43 +08:00
|
|
|
{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
|
2007-05-22 17:34:22 +08:00
|
|
|
{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
|
2006-10-11 05:28:11 +08:00
|
|
|
/* end marker */
|
|
|
|
|
{ 0, }
|
|
|
|
|
};
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/**
|
2007-04-11 07:04:20 +08:00
|
|
|
* ich_pata_cable_detect - Probe host controller cable detect info
|
2005-04-17 06:20:36 +08:00
|
|
|
* @ap: Port for which cable detect info is desired
|
|
|
|
|
*
|
|
|
|
|
* Read 80c cable indicator from ATA PCI device's PCI config
|
|
|
|
|
* register. This register is normally set by firmware (BIOS).
|
|
|
|
|
*
|
|
|
|
|
* LOCKING:
|
|
|
|
|
* None (inherited from caller).
|
|
|
|
|
*/
|
2006-08-30 06:12:40 +08:00
|
|
|
|
2007-04-11 07:04:20 +08:00
|
|
|
static int ich_pata_cable_detect(struct ata_port *ap)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2006-10-11 05:28:11 +08:00
|
|
|
const struct ich_laptop *lap = &ich_laptop[0];
|
2005-04-17 06:20:36 +08:00
|
|
|
u8 tmp, mask;
|
|
|
|
|
|
2006-10-11 05:28:11 +08:00
|
|
|
/* Check for specials - Acer Aspire 5602WLMi */
|
|
|
|
|
while (lap->device) {
|
|
|
|
|
if (lap->device == pdev->device &&
|
|
|
|
|
lap->subvendor == pdev->subsystem_vendor &&
|
2007-10-19 18:42:56 +08:00
|
|
|
lap->subdevice == pdev->subsystem_device)
|
2007-04-11 07:04:20 +08:00
|
|
|
return ATA_CBL_PATA40_SHORT;
|
2007-10-19 18:42:56 +08:00
|
|
|
|
2006-10-11 05:28:11 +08:00
|
|
|
lap++;
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* check BIOS cable detect results */
|
2006-08-10 15:59:16 +08:00
|
|
|
mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
|
2005-04-17 06:20:36 +08:00
|
|
|
pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
|
|
|
|
|
if ((tmp & mask) == 0)
|
2007-04-11 07:04:20 +08:00
|
|
|
return ATA_CBL_PATA40;
|
|
|
|
|
return ATA_CBL_PATA80;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
2006-05-31 17:28:14 +08:00
|
|
|
* piix_pata_prereset - prereset for PATA host controller
|
2007-08-06 17:36:23 +08:00
|
|
|
* @link: Target link
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 15:50:52 +08:00
|
|
|
* @deadline: deadline jiffies for the operation
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
2006-02-15 14:01:42 +08:00
|
|
|
* LOCKING:
|
|
|
|
|
* None (inherited from caller).
|
|
|
|
|
*/
|
2007-08-06 17:36:23 +08:00
|
|
|
static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-08-06 17:36:23 +08:00
|
|
|
struct ata_port *ap = link->ap;
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-09-27 00:53:38 +08:00
|
|
|
if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
|
|
|
|
|
return -ENOENT;
|
2007-08-06 17:36:23 +08:00
|
|
|
return ata_std_prereset(link, deadline);
|
2006-05-31 17:28:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void piix_pata_error_handler(struct ata_port *ap)
|
|
|
|
|
{
|
|
|
|
|
ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
|
|
|
|
|
ata_std_postreset);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* piix_set_piomode - Initialize host controller PATA PIO timings
|
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
|
* @adev: um
|
|
|
|
|
*
|
|
|
|
|
* Set PIO mode for device, in host controller PCI config space.
|
|
|
|
|
*
|
|
|
|
|
* LOCKING:
|
|
|
|
|
* None (inherited from caller).
|
|
|
|
|
*/
|
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
unsigned int pio = adev->pio_mode - XFER_PIO_0;
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *dev = to_pci_dev(ap->host->dev);
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int is_slave = (adev->devno != 0);
|
2006-08-10 15:59:16 +08:00
|
|
|
unsigned int master_port= ap->port_no ? 0x42 : 0x40;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int slave_port = 0x44;
|
|
|
|
|
u16 master_data;
|
|
|
|
|
u8 slave_data;
|
2006-08-30 06:12:40 +08:00
|
|
|
u8 udma_enable;
|
|
|
|
|
int control = 0;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/*
|
|
|
|
|
* See Intel Document 298600-004 for the timing programing rules
|
|
|
|
|
* for ICH controllers.
|
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
static const /* ISP RTC */
|
|
|
|
|
u8 timings[][2] = { { 0, 0 },
|
|
|
|
|
{ 0, 0 },
|
|
|
|
|
{ 1, 0 },
|
|
|
|
|
{ 2, 1 },
|
|
|
|
|
{ 2, 3 }, };
|
|
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
if (pio >= 2)
|
|
|
|
|
control |= 1; /* TIME1 enable */
|
|
|
|
|
if (ata_pio_need_iordy(adev))
|
|
|
|
|
control |= 2; /* IE enable */
|
|
|
|
|
|
2006-08-31 12:03:49 +08:00
|
|
|
/* Intel specifies that the PPE functionality is for disk only */
|
2006-08-30 06:12:40 +08:00
|
|
|
if (adev->class == ATA_DEV_ATA)
|
|
|
|
|
control |= 4; /* PPE enable */
|
|
|
|
|
|
2007-05-26 01:16:58 +08:00
|
|
|
/* PIO configuration clears DTE unconditionally. It will be
|
|
|
|
|
* programmed in set_dmamode which is guaranteed to be called
|
|
|
|
|
* after set_piomode if any DMA mode is available.
|
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
pci_read_config_word(dev, master_port, &master_data);
|
|
|
|
|
if (is_slave) {
|
2007-05-26 01:16:58 +08:00
|
|
|
/* clear TIME1|IE1|PPE1|DTE1 */
|
|
|
|
|
master_data &= 0xff0f;
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Enable SITRE (seperate slave timing register) */
|
2005-04-17 06:20:36 +08:00
|
|
|
master_data |= 0x4000;
|
2006-08-30 06:12:40 +08:00
|
|
|
/* enable PPE1, IE1 and TIME1 as needed */
|
|
|
|
|
master_data |= (control << 4);
|
2005-04-17 06:20:36 +08:00
|
|
|
pci_read_config_byte(dev, slave_port, &slave_data);
|
2006-08-10 15:59:16 +08:00
|
|
|
slave_data &= (ap->port_no ? 0x0f : 0xf0);
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Load the timing nibble for this slave */
|
2007-05-26 01:16:58 +08:00
|
|
|
slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
|
|
|
|
|
<< (ap->port_no ? 4 : 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
2007-05-26 01:16:58 +08:00
|
|
|
/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
|
|
|
|
|
master_data &= 0xccf0;
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Enable PPE, IE and TIME as appropriate */
|
|
|
|
|
master_data |= control;
|
2007-05-26 01:16:58 +08:00
|
|
|
/* load ISP and RCT */
|
2005-04-17 06:20:36 +08:00
|
|
|
master_data |=
|
|
|
|
|
(timings[pio][0] << 12) |
|
|
|
|
|
(timings[pio][1] << 8);
|
|
|
|
|
}
|
|
|
|
|
pci_write_config_word(dev, master_port, master_data);
|
|
|
|
|
if (is_slave)
|
|
|
|
|
pci_write_config_byte(dev, slave_port, slave_data);
|
2006-08-30 06:12:40 +08:00
|
|
|
|
|
|
|
|
/* Ensure the UDMA bit is off - it will be turned back on if
|
|
|
|
|
UDMA is selected */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
if (ap->udma_mask) {
|
|
|
|
|
pci_read_config_byte(dev, 0x48, &udma_enable);
|
|
|
|
|
udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
|
|
|
|
|
pci_write_config_byte(dev, 0x48, udma_enable);
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
2006-08-30 06:12:40 +08:00
|
|
|
* do_pata_set_dmamode - Initialize host controller PATA PIO timings
|
2005-04-17 06:20:36 +08:00
|
|
|
* @ap: Port whose timings we are configuring
|
2006-08-30 06:12:40 +08:00
|
|
|
* @adev: Drive in question
|
2005-04-17 06:20:36 +08:00
|
|
|
* @udma: udma mode, 0 - 6
|
2006-09-26 04:00:46 +08:00
|
|
|
* @isich: set if the chip is an ICH device
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
|
* Set UDMA mode for device, in host controller PCI config space.
|
|
|
|
|
*
|
|
|
|
|
* LOCKING:
|
|
|
|
|
* None (inherited from caller).
|
|
|
|
|
*/
|
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *dev = to_pci_dev(ap->host->dev);
|
2006-08-30 06:12:40 +08:00
|
|
|
u8 master_port = ap->port_no ? 0x42 : 0x40;
|
|
|
|
|
u16 master_data;
|
|
|
|
|
u8 speed = adev->dma_mode;
|
|
|
|
|
int devid = adev->devno + 2 * ap->port_no;
|
2007-01-11 09:20:34 +08:00
|
|
|
u8 udma_enable = 0;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
static const /* ISP RTC */
|
|
|
|
|
u8 timings[][2] = { { 0, 0 },
|
|
|
|
|
{ 0, 0 },
|
|
|
|
|
{ 1, 0 },
|
|
|
|
|
{ 2, 1 },
|
|
|
|
|
{ 2, 3 }, };
|
|
|
|
|
|
|
|
|
|
pci_read_config_word(dev, master_port, &master_data);
|
2007-01-11 01:13:38 +08:00
|
|
|
if (ap->udma_mask)
|
|
|
|
|
pci_read_config_byte(dev, 0x48, &udma_enable);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
if (speed >= XFER_UDMA_0) {
|
2006-08-30 06:12:40 +08:00
|
|
|
unsigned int udma = adev->dma_mode - XFER_UDMA_0;
|
|
|
|
|
u16 udma_timing;
|
|
|
|
|
u16 ideconf;
|
|
|
|
|
int u_clock, u_speed;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/*
|
2007-10-19 18:42:56 +08:00
|
|
|
* UDMA is handled by a combination of clock switching and
|
2006-08-31 12:03:49 +08:00
|
|
|
* selection of dividers
|
|
|
|
|
*
|
2006-08-30 06:12:40 +08:00
|
|
|
* Handy rule: Odd modes are UDMATIMx 01, even are 02
|
2006-08-31 12:03:49 +08:00
|
|
|
* except UDMA0 which is 00
|
2006-08-30 06:12:40 +08:00
|
|
|
*/
|
|
|
|
|
u_speed = min(2 - (udma & 1), udma);
|
|
|
|
|
if (udma == 5)
|
|
|
|
|
u_clock = 0x1000; /* 100Mhz */
|
|
|
|
|
else if (udma > 2)
|
|
|
|
|
u_clock = 1; /* 66Mhz */
|
|
|
|
|
else
|
|
|
|
|
u_clock = 0; /* 33Mhz */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
udma_enable |= (1 << devid);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Load the CT/RP selection */
|
|
|
|
|
pci_read_config_word(dev, 0x4A, &udma_timing);
|
|
|
|
|
udma_timing &= ~(3 << (4 * devid));
|
|
|
|
|
udma_timing |= u_speed << (4 * devid);
|
|
|
|
|
pci_write_config_word(dev, 0x4A, udma_timing);
|
|
|
|
|
|
2006-08-31 12:03:49 +08:00
|
|
|
if (isich) {
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Select a 33/66/100Mhz clock */
|
|
|
|
|
pci_read_config_word(dev, 0x54, &ideconf);
|
|
|
|
|
ideconf &= ~(0x1001 << devid);
|
|
|
|
|
ideconf |= u_clock << devid;
|
|
|
|
|
/* For ICH or later we should set bit 10 for better
|
|
|
|
|
performance (WR_PingPong_En) */
|
|
|
|
|
pci_write_config_word(dev, 0x54, ideconf);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
} else {
|
2006-08-30 06:12:40 +08:00
|
|
|
/*
|
|
|
|
|
* MWDMA is driven by the PIO timings. We must also enable
|
|
|
|
|
* IORDY unconditionally along with TIME1. PPE has already
|
|
|
|
|
* been set when the PIO timing was set.
|
|
|
|
|
*/
|
|
|
|
|
unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
|
|
|
|
|
unsigned int control;
|
|
|
|
|
u8 slave_data;
|
|
|
|
|
const unsigned int needed_pio[3] = {
|
|
|
|
|
XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
|
|
|
|
|
};
|
|
|
|
|
int pio = needed_pio[mwdma] - XFER_PIO_0;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
control = 3; /* IORDY|TIME1 */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* If the drive MWDMA is faster than it can do PIO then
|
|
|
|
|
we must force PIO into PIO0 */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
if (adev->pio_mode < needed_pio[mwdma])
|
|
|
|
|
/* Enable DMA timing only */
|
|
|
|
|
control |= 8; /* PIO cycles in PIO0 */
|
|
|
|
|
|
|
|
|
|
if (adev->devno) { /* Slave */
|
|
|
|
|
master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
|
|
|
|
|
master_data |= control << 4;
|
|
|
|
|
pci_read_config_byte(dev, 0x44, &slave_data);
|
2007-05-26 01:16:58 +08:00
|
|
|
slave_data &= (ap->port_no ? 0x0f : 0xf0);
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Load the matching timing */
|
|
|
|
|
slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
|
|
|
|
|
pci_write_config_byte(dev, 0x44, slave_data);
|
|
|
|
|
} else { /* Master */
|
2006-08-31 12:03:49 +08:00
|
|
|
master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
|
2006-08-30 06:12:40 +08:00
|
|
|
and master timing bits */
|
|
|
|
|
master_data |= control;
|
|
|
|
|
master_data |=
|
|
|
|
|
(timings[pio][0] << 12) |
|
|
|
|
|
(timings[pio][1] << 8);
|
|
|
|
|
}
|
2007-05-26 01:16:58 +08:00
|
|
|
|
|
|
|
|
if (ap->udma_mask) {
|
|
|
|
|
udma_enable &= ~(1 << devid);
|
|
|
|
|
pci_write_config_word(dev, master_port, master_data);
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Don't scribble on 0x48 if the controller does not support UDMA */
|
|
|
|
|
if (ap->udma_mask)
|
|
|
|
|
pci_write_config_byte(dev, 0x48, udma_enable);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* piix_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
|
* @adev: um
|
|
|
|
|
*
|
|
|
|
|
* Set MW/UDMA mode for device, in host controller PCI config space.
|
|
|
|
|
*
|
|
|
|
|
* LOCKING:
|
|
|
|
|
* None (inherited from caller).
|
|
|
|
|
*/
|
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
|
do_pata_set_dmamode(ap, adev, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* ich_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
|
* @adev: um
|
|
|
|
|
*
|
|
|
|
|
* Set MW/UDMA mode for device, in host controller PCI config space.
|
|
|
|
|
*
|
|
|
|
|
* LOCKING:
|
|
|
|
|
* None (inherited from caller).
|
|
|
|
|
*/
|
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
|
do_pata_set_dmamode(ap, adev, 1);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2007-07-10 14:55:43 +08:00
|
|
|
#ifdef CONFIG_PM
|
2007-07-27 13:53:28 +08:00
|
|
|
static int piix_broken_suspend(void)
|
|
|
|
|
{
|
2007-10-04 03:15:40 +08:00
|
|
|
static const struct dmi_system_id sysids[] = {
|
2007-09-30 16:11:20 +08:00
|
|
|
{
|
|
|
|
|
.ident = "TECRA M3",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
|
.ident = "TECRA M3",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-12-05 09:39:49 +08:00
|
|
|
{
|
|
|
|
|
.ident = "TECRA M4",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-07-27 13:53:28 +08:00
|
|
|
{
|
|
|
|
|
.ident = "TECRA M5",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
|
|
|
|
|
},
|
2007-07-10 14:55:43 +08:00
|
|
|
},
|
2008-01-17 21:08:55 +08:00
|
|
|
{
|
|
|
|
|
.ident = "TECRA M6",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-08-14 18:56:04 +08:00
|
|
|
{
|
|
|
|
|
.ident = "TECRA M7",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
|
.ident = "TECRA A8",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2008-01-17 21:08:55 +08:00
|
|
|
{
|
|
|
|
|
.ident = "Satellite R20",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
|
.ident = "Satellite R25",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-08-25 07:31:02 +08:00
|
|
|
{
|
|
|
|
|
.ident = "Satellite U200",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
|
.ident = "Satellite U200",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-11-07 11:02:27 +08:00
|
|
|
{
|
|
|
|
|
.ident = "Satellite Pro U200",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-07-27 13:53:28 +08:00
|
|
|
{
|
|
|
|
|
.ident = "Satellite U205",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
|
|
|
|
|
},
|
2007-07-10 14:55:43 +08:00
|
|
|
},
|
2007-11-12 16:56:24 +08:00
|
|
|
{
|
|
|
|
|
.ident = "SATELLITE U205",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-07-27 13:53:28 +08:00
|
|
|
{
|
|
|
|
|
.ident = "Portege M500",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
|
|
|
|
|
},
|
2007-07-10 14:55:43 +08:00
|
|
|
},
|
2007-09-01 18:48:52 +08:00
|
|
|
|
|
|
|
|
{ } /* terminate list */
|
2007-07-27 13:53:28 +08:00
|
|
|
};
|
2007-07-27 13:55:07 +08:00
|
|
|
static const char *oemstrs[] = {
|
|
|
|
|
"Tecra M3,",
|
|
|
|
|
};
|
|
|
|
|
int i;
|
2007-07-27 13:53:28 +08:00
|
|
|
|
|
|
|
|
if (dmi_check_system(sysids))
|
|
|
|
|
return 1;
|
|
|
|
|
|
2007-07-27 13:55:07 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
|
|
|
|
|
if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
|
|
|
|
|
return 1;
|
|
|
|
|
|
2007-07-27 13:53:28 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
2007-07-10 14:55:43 +08:00
|
|
|
|
|
|
|
|
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
|
|
|
|
|
{
|
|
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
|
|
rc = ata_host_suspend(host, mesg);
|
|
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
/* Some braindamaged ACPI suspend implementations expect the
|
|
|
|
|
* controller to be awake on entry; otherwise, it burns cpu
|
|
|
|
|
* cycles and power trying to do something to the sleeping
|
|
|
|
|
* beauty.
|
|
|
|
|
*/
|
2007-07-27 13:53:28 +08:00
|
|
|
if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
|
2007-07-10 14:55:43 +08:00
|
|
|
pci_save_state(pdev);
|
|
|
|
|
|
|
|
|
|
/* mark its power state as "unknown", since we don't
|
|
|
|
|
* know if e.g. the BIOS will change its device state
|
|
|
|
|
* when we suspend.
|
|
|
|
|
*/
|
|
|
|
|
if (pdev->current_state == PCI_D0)
|
|
|
|
|
pdev->current_state = PCI_UNKNOWN;
|
|
|
|
|
|
|
|
|
|
/* tell resume that it's waking up from broken suspend */
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
host->flags |= PIIX_HOST_BROKEN_SUSPEND;
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
} else
|
|
|
|
|
ata_pci_device_do_suspend(pdev, mesg);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int piix_pci_device_resume(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
|
|
if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
|
|
|
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
|
|
|
pci_restore_state(pdev);
|
|
|
|
|
|
|
|
|
|
/* PCI device wasn't disabled during suspend. Use
|
2007-07-27 13:43:35 +08:00
|
|
|
* pci_reenable_device() to avoid affecting the enable
|
|
|
|
|
* count.
|
2007-07-10 14:55:43 +08:00
|
|
|
*/
|
2007-07-27 13:43:35 +08:00
|
|
|
rc = pci_reenable_device(pdev);
|
2007-07-10 14:55:43 +08:00
|
|
|
if (rc)
|
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
|
|
|
|
|
"device after resume (%d)\n", rc);
|
|
|
|
|
} else
|
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
|
|
|
|
|
|
|
|
if (rc == 0)
|
|
|
|
|
ata_host_resume(host);
|
|
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-01-07 18:38:53 +08:00
|
|
|
static u8 piix_vmw_bmdma_status(struct ata_port *ap)
|
|
|
|
|
{
|
|
|
|
|
return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#define AHCI_PCI_BAR 5
|
|
|
|
|
#define AHCI_GLOBAL_CTL 0x04
|
|
|
|
|
#define AHCI_ENABLE (1 << 31)
|
|
|
|
|
static int piix_disable_ahci(struct pci_dev *pdev)
|
|
|
|
|
{
|
2005-08-30 17:18:18 +08:00
|
|
|
void __iomem *mmio;
|
2005-04-17 06:20:36 +08:00
|
|
|
u32 tmp;
|
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
|
|
/* BUG: pci_enable_device has not yet been called. This
|
|
|
|
|
* works because this device is usually set up by BIOS.
|
|
|
|
|
*/
|
|
|
|
|
|
2005-08-30 17:42:52 +08:00
|
|
|
if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
|
|
|
|
|
!pci_resource_len(pdev, AHCI_PCI_BAR))
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
2005-07-29 03:54:15 +08:00
|
|
|
|
2005-08-30 17:42:52 +08:00
|
|
|
mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (!mmio)
|
|
|
|
|
return -ENOMEM;
|
2005-07-29 03:54:15 +08:00
|
|
|
|
2007-11-19 22:28:28 +08:00
|
|
|
tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (tmp & AHCI_ENABLE) {
|
|
|
|
|
tmp &= ~AHCI_ENABLE;
|
2007-11-19 22:28:28 +08:00
|
|
|
iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-11-19 22:28:28 +08:00
|
|
|
tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (tmp & AHCI_ENABLE)
|
|
|
|
|
rc = -EIO;
|
|
|
|
|
}
|
2005-07-29 03:54:15 +08:00
|
|
|
|
2005-08-30 17:42:52 +08:00
|
|
|
pci_iounmap(pdev, mmio);
|
2005-04-17 06:20:36 +08:00
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2005-12-09 03:22:28 +08:00
|
|
|
/**
|
|
|
|
|
* piix_check_450nx_errata - Check for problem 450NX setup
|
2006-01-29 02:15:32 +08:00
|
|
|
* @ata_dev: the PCI device to check
|
2006-03-24 22:56:57 +08:00
|
|
|
*
|
2005-12-09 03:22:28 +08:00
|
|
|
* Check for the present of 450NX errata #19 and errata #25. If
|
|
|
|
|
* they are found return an error code so we can turn off DMA
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
|
|
|
|
|
{
|
|
|
|
|
struct pci_dev *pdev = NULL;
|
|
|
|
|
u16 cfg;
|
|
|
|
|
int no_piix_dma = 0;
|
2006-03-24 22:56:57 +08:00
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
|
2005-12-09 03:22:28 +08:00
|
|
|
/* Look for 450NX PXB. Check for problem configurations
|
|
|
|
|
A PCI quirk checks bit 6 already */
|
|
|
|
|
pci_read_config_word(pdev, 0x41, &cfg);
|
|
|
|
|
/* Only on the original revision: IDE DMA can hang */
|
2007-06-09 06:46:36 +08:00
|
|
|
if (pdev->revision == 0x00)
|
2005-12-09 03:22:28 +08:00
|
|
|
no_piix_dma = 1;
|
|
|
|
|
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
|
2007-06-09 06:46:36 +08:00
|
|
|
else if (cfg & (1<<14) && pdev->revision < 5)
|
2005-12-09 03:22:28 +08:00
|
|
|
no_piix_dma = 2;
|
|
|
|
|
}
|
2006-05-23 05:58:14 +08:00
|
|
|
if (no_piix_dma)
|
2005-12-09 03:22:28 +08:00
|
|
|
dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
|
2006-05-23 05:58:14 +08:00
|
|
|
if (no_piix_dma == 2)
|
2005-12-09 03:22:28 +08:00
|
|
|
dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
|
|
|
|
|
return no_piix_dma;
|
2006-03-24 22:56:57 +08:00
|
|
|
}
|
2005-12-09 03:22:28 +08:00
|
|
|
|
2006-07-11 23:48:50 +08:00
|
|
|
static void __devinit piix_init_pcs(struct pci_dev *pdev,
|
2006-08-22 20:15:58 +08:00
|
|
|
struct ata_port_info *pinfo,
|
2006-07-11 23:48:50 +08:00
|
|
|
const struct piix_map_db *map_db)
|
|
|
|
|
{
|
|
|
|
|
u16 pcs, new_pcs;
|
|
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, ICH5_PCS, &pcs);
|
|
|
|
|
|
|
|
|
|
new_pcs = pcs | map_db->port_enable;
|
|
|
|
|
|
|
|
|
|
if (new_pcs != pcs) {
|
|
|
|
|
DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
|
|
|
|
|
pci_write_config_word(pdev, ICH5_PCS, new_pcs);
|
|
|
|
|
msleep(150);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-03-01 00:25:39 +08:00
|
|
|
static void __devinit piix_init_sata_map(struct pci_dev *pdev,
|
2006-06-29 00:58:28 +08:00
|
|
|
struct ata_port_info *pinfo,
|
|
|
|
|
const struct piix_map_db *map_db)
|
2006-03-01 00:25:39 +08:00
|
|
|
{
|
2006-06-29 00:58:28 +08:00
|
|
|
struct piix_host_priv *hpriv = pinfo[0].private_data;
|
2007-10-15 02:35:40 +08:00
|
|
|
const int *map;
|
2006-03-01 00:25:39 +08:00
|
|
|
int i, invalid_map = 0;
|
|
|
|
|
u8 map_value;
|
|
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, ICH5_PMR, &map_value);
|
|
|
|
|
|
|
|
|
|
map = map_db->map[map_value & map_db->mask];
|
|
|
|
|
|
|
|
|
|
dev_printk(KERN_INFO, &pdev->dev, "MAP [");
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
switch (map[i]) {
|
|
|
|
|
case RV:
|
|
|
|
|
invalid_map = 1;
|
|
|
|
|
printk(" XX");
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case NA:
|
|
|
|
|
printk(" --");
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case IDE:
|
|
|
|
|
WARN_ON((i & 1) || map[i + 1] != IDE);
|
2006-08-30 06:12:40 +08:00
|
|
|
pinfo[i / 2] = piix_port_info[ich_pata_100];
|
2006-08-05 02:59:13 +08:00
|
|
|
pinfo[i / 2].private_data = hpriv;
|
2006-03-01 00:25:39 +08:00
|
|
|
i++;
|
|
|
|
|
printk(" IDE IDE");
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
printk(" P%d", map[i]);
|
|
|
|
|
if (i & 1)
|
2006-08-24 15:19:22 +08:00
|
|
|
pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
|
2006-03-01 00:25:39 +08:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
printk(" ]\n");
|
|
|
|
|
|
|
|
|
|
if (invalid_map)
|
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
|
"invalid MAP value %u\n", map_value);
|
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
hpriv->map = map;
|
2006-03-01 00:25:39 +08:00
|
|
|
}
|
|
|
|
|
|
2007-08-23 09:15:18 +08:00
|
|
|
static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
|
|
|
|
|
{
|
2007-10-04 03:15:40 +08:00
|
|
|
static const struct dmi_system_id sysids[] = {
|
2007-08-23 09:15:18 +08:00
|
|
|
{
|
|
|
|
|
/* Clevo M570U sets IOCFG bit 18 if the cdrom
|
|
|
|
|
* isn't used to boot the system which
|
|
|
|
|
* disables the channel.
|
|
|
|
|
*/
|
|
|
|
|
.ident = "M570U",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2007-09-01 18:48:52 +08:00
|
|
|
|
|
|
|
|
{ } /* terminate list */
|
2007-08-23 09:15:18 +08:00
|
|
|
};
|
|
|
|
|
u32 iocfg;
|
|
|
|
|
|
|
|
|
|
if (!dmi_check_system(sysids))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* The datasheet says that bit 18 is NOOP but certain systems
|
|
|
|
|
* seem to use it to disable a channel. Clear the bit on the
|
|
|
|
|
* affected systems.
|
|
|
|
|
*/
|
|
|
|
|
pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
|
|
|
|
|
if (iocfg & (1 << 18)) {
|
|
|
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
|
|
|
|
"applying IOCFG bit18 quirk\n");
|
|
|
|
|
iocfg &= ~(1 << 18);
|
|
|
|
|
pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/**
|
|
|
|
|
* piix_init_one - Register PIIX ATA PCI device with kernel services
|
|
|
|
|
* @pdev: PCI device to register
|
|
|
|
|
* @ent: Entry in piix_pci_tbl matching with @pdev
|
|
|
|
|
*
|
|
|
|
|
* Called from kernel PCI layer. We probe for combined mode (sigh),
|
|
|
|
|
* and then hand over control to libata, for it to do the rest.
|
|
|
|
|
*
|
|
|
|
|
* LOCKING:
|
|
|
|
|
* Inherited from PCI layer (may sleep).
|
|
|
|
|
*
|
|
|
|
|
* RETURNS:
|
|
|
|
|
* Zero on success, or -ERRNO value.
|
|
|
|
|
*/
|
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
static int printed_version;
|
2007-01-20 15:00:28 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
2006-03-01 00:25:39 +08:00
|
|
|
struct ata_port_info port_info[2];
|
2007-05-04 18:43:58 +08:00
|
|
|
const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
|
2006-06-29 00:58:28 +08:00
|
|
|
struct piix_host_priv *hpriv;
|
2006-08-24 15:19:22 +08:00
|
|
|
unsigned long port_flags;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
if (!printed_version++)
|
2005-10-30 19:42:18 +08:00
|
|
|
dev_printk(KERN_DEBUG, &pdev->dev,
|
|
|
|
|
"version " DRV_VERSION "\n");
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* no hotplugging support (FIXME) */
|
|
|
|
|
if (!in_module_init)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
2007-01-20 15:00:28 +08:00
|
|
|
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
|
2006-06-29 00:58:28 +08:00
|
|
|
if (!hpriv)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2006-03-01 00:25:39 +08:00
|
|
|
port_info[0] = piix_port_info[ent->driver_data];
|
|
|
|
|
port_info[1] = piix_port_info[ent->driver_data];
|
2006-06-29 00:58:28 +08:00
|
|
|
port_info[0].private_data = hpriv;
|
|
|
|
|
port_info[1].private_data = hpriv;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-08-24 15:19:22 +08:00
|
|
|
port_flags = port_info[0].flags;
|
[PATCH] ata_piix: fix MAP VALUE interpretation for for ICH6/7
Unlike their older siblings, ICH6 and 7 use different scheme for MAP
VALUE. This patch makes ata_piix interpret MV properly on ICH6/7.
Pre-ICH6/7
The value of these bits indicate the address range the SATA port
responds to, and whether or not the SATA and IDE functions are
combined.
000 = Non-combined. P0 is primary master. P1 is secondary master.
001 = Non-combined. P0 is secondary master. P1 is primary master.
100 = Combined. P0 is primary master. P1 is primary slave. P-ATA is
2:0 Map Value secondary.
101 = Combined. P0 is primary slave. P1 is primary master. P-ATA is
secondary.
110 = Combined. P-ATA is primary. P0 is secondary master. P1 is
secondary slave.
111 = Combined. P-ATA is primary. P0 is secondary slave. P1 is
secondary master.
ICH6/7
Map Value - R/W. Map Value (MV): The value in the bits below indicate
the address range the SATA ports responds to, and whether or not the
PATA and SATA functions are combined. When in combined mode, the AHCI
memory space is not available and AHCI may not be used.
00 = Non-combined. P0 is primary master, P2 is the primary slave. P1
is secondary master, P3 is the 1:0 secondary slave (desktop
only). P0 is primary master, P2 is the primary slave (mobile
only).
01 = Combined. IDE is primary. P1 is secondary master, P3 is the
secondary slave. (desktop only)
10 = Combined. P0 is primary master. P2 is primary slave. IDE is secondary
11 = Reserved
Signed-off-by: Tejun Heo <htejun@gmail.com>
--
Jeff, without this patch, ata_piix misdetects my ICH7's combined mode,
ending up not applying bridge limits to PX-710SA and configuring IDE
drive on 40-c cable to UDMA/66.
Thanks.
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2005-12-18 16:17:07 +08:00
|
|
|
|
2006-08-24 15:19:22 +08:00
|
|
|
if (port_flags & PIIX_FLAG_AHCI) {
|
2005-08-01 01:13:24 +08:00
|
|
|
u8 tmp;
|
|
|
|
|
pci_read_config_byte(pdev, PIIX_SCC, &tmp);
|
|
|
|
|
if (tmp == PIIX_AHCI_DEVICE) {
|
|
|
|
|
int rc = piix_disable_ahci(pdev);
|
|
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2006-03-01 00:25:39 +08:00
|
|
|
/* Initialize SATA map */
|
2006-08-24 15:19:22 +08:00
|
|
|
if (port_flags & ATA_FLAG_SATA) {
|
2006-06-29 00:58:28 +08:00
|
|
|
piix_init_sata_map(pdev, port_info,
|
|
|
|
|
piix_map_db_table[ent->driver_data]);
|
2006-08-22 20:15:58 +08:00
|
|
|
piix_init_pcs(pdev, port_info,
|
|
|
|
|
piix_map_db_table[ent->driver_data]);
|
2006-07-11 23:48:50 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-08-23 09:15:18 +08:00
|
|
|
/* apply IOCFG bit18 quirk */
|
|
|
|
|
piix_iocfg_bit18_quirk(pdev);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* On ICH5, some BIOSen disable the interrupt using the
|
|
|
|
|
* PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
|
|
|
|
|
* On ICH6, this bit has the same effect, but only when
|
|
|
|
|
* MSI is disabled (and it is disabled, as we don't use
|
|
|
|
|
* message-signalled interrupts currently).
|
|
|
|
|
*/
|
2006-08-24 15:19:22 +08:00
|
|
|
if (port_flags & PIIX_FLAG_CHECKINTR)
|
2005-08-16 03:23:41 +08:00
|
|
|
pci_intx(pdev, 1);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-12-09 03:22:28 +08:00
|
|
|
if (piix_check_450nx_errata(pdev)) {
|
|
|
|
|
/* This writes into the master table but it does not
|
|
|
|
|
really matter for this errata as we will apply it to
|
|
|
|
|
all the PIIX devices on the board */
|
2006-03-01 00:25:39 +08:00
|
|
|
port_info[0].mwdma_mask = 0;
|
|
|
|
|
port_info[0].udma_mask = 0;
|
|
|
|
|
port_info[1].mwdma_mask = 0;
|
|
|
|
|
port_info[1].udma_mask = 0;
|
2005-12-09 03:22:28 +08:00
|
|
|
}
|
2007-05-04 18:43:58 +08:00
|
|
|
return ata_pci_init_one(pdev, ppi);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __init piix_init(void)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
|
2006-08-10 17:13:18 +08:00
|
|
|
DPRINTK("pci_register_driver\n");
|
|
|
|
|
rc = pci_register_driver(&piix_pci_driver);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
in_module_init = 0;
|
|
|
|
|
|
|
|
|
|
DPRINTK("done\n");
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __exit piix_exit(void)
|
|
|
|
|
{
|
|
|
|
|
pci_unregister_driver(&piix_pci_driver);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
module_init(piix_init);
|
|
|
|
|
module_exit(piix_exit);
|