License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2006-10-04 17:16:59 +08:00
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#ifndef LINUX_MSI_H
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#define LINUX_MSI_H
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2011-10-07 02:08:18 +08:00
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#include <linux/kobject.h>
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2007-04-05 15:19:10 +08:00
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#include <linux/list.h>
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2020-10-25 05:35:11 +08:00
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#include <asm/msi.h>
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/* Dummy shadow structures if an architecture does not define them */
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#ifndef arch_msi_msg_addr_lo
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typedef struct arch_msi_msg_addr_lo {
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u32 address_lo;
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} __attribute__ ((packed)) arch_msi_msg_addr_lo_t;
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#endif
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#ifndef arch_msi_msg_addr_hi
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typedef struct arch_msi_msg_addr_hi {
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u32 address_hi;
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} __attribute__ ((packed)) arch_msi_msg_addr_hi_t;
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#endif
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#ifndef arch_msi_msg_data
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typedef struct arch_msi_msg_data {
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u32 data;
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} __attribute__ ((packed)) arch_msi_msg_data_t;
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#endif
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2007-04-05 15:19:10 +08:00
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2020-10-25 05:35:11 +08:00
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/**
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* msi_msg - Representation of a MSI message
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* @address_lo: Low 32 bits of msi message address
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* @arch_addrlo: Architecture specific shadow of @address_lo
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* @address_hi: High 32 bits of msi message address
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* (only used when device supports it)
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* @arch_addrhi: Architecture specific shadow of @address_hi
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* @data: MSI message data (usually 16 bits)
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* @arch_data: Architecture specific shadow of @data
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*/
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2006-10-04 17:16:59 +08:00
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struct msi_msg {
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2020-10-25 05:35:11 +08:00
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union {
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u32 address_lo;
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arch_msi_msg_addr_lo_t arch_addr_lo;
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};
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union {
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u32 address_hi;
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arch_msi_msg_addr_hi_t arch_addr_hi;
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};
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union {
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u32 data;
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arch_msi_msg_data_t arch_data;
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};
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2006-10-04 17:16:59 +08:00
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};
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2014-10-27 10:44:36 +08:00
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extern int pci_msi_ignore_mask;
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2007-01-18 12:50:05 +08:00
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/* Helper functions */
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2010-09-28 22:46:51 +08:00
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struct irq_data;
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2010-09-29 01:09:51 +08:00
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struct msi_desc;
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2015-07-09 16:00:45 +08:00
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struct pci_dev;
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2015-07-28 21:46:16 +08:00
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struct platform_msi_priv_data;
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2013-04-19 00:55:46 +08:00
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void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
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2017-02-15 05:53:12 +08:00
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#ifdef CONFIG_GENERIC_MSI_IRQ
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2013-04-19 00:55:46 +08:00
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void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
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2017-02-15 05:53:12 +08:00
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#else
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static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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}
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#endif
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2014-11-09 23:10:33 +08:00
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2015-07-28 21:46:16 +08:00
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typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc,
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struct msi_msg *msg);
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/**
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* platform_msi_desc - Platform device specific msi descriptor data
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* @msi_priv_data: Pointer to platform private data
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* @msi_index: The index of the MSI descriptor for multi MSI
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*/
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struct platform_msi_desc {
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struct platform_msi_priv_data *msi_priv_data;
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u16 msi_index;
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};
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2016-01-07 06:03:20 +08:00
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/**
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* fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
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* @msi_index: The index of the MSI descriptor
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*/
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struct fsl_mc_msi_desc {
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u16 msi_index;
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};
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2019-04-30 18:12:28 +08:00
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/**
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* ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
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* @dev_index: TISCI device index
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*/
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struct ti_sci_inta_msi_desc {
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u16 dev_index;
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};
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2015-07-09 16:00:46 +08:00
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/**
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* struct msi_desc - Descriptor structure for MSI based interrupts
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* @list: List head for management
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* @irq: The base interrupt number
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* @nvec_used: The number of vectors used
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* @dev: Pointer to the device which uses this descriptor
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* @msg: The last set MSI message cached for reuse
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2016-07-04 16:39:26 +08:00
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* @affinity: Optional pointer to a cpu affinity mask for this descriptor
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2015-07-09 16:00:46 +08:00
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*
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2019-05-24 06:30:51 +08:00
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* @write_msi_msg: Callback that may be called when the MSI message
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* address or data changes
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* @write_msi_msg_data: Data parameter for the callback.
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*
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2015-07-09 16:00:46 +08:00
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* @masked: [PCI MSI/X] Mask bits
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* @is_msix: [PCI MSI/X] True if MSI-X
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* @multiple: [PCI MSI/X] log2 num of messages allocated
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* @multi_cap: [PCI MSI/X] log2 num of messages supported
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* @maskbit: [PCI MSI/X] Mask-Pending bit supported?
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* @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
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* @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
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* @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
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* @mask_pos: [PCI MSI] Mask register position
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* @mask_base: [PCI MSI-X] Mask register base address
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2015-07-28 21:46:16 +08:00
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* @platform: [platform] Platform device specific msi descriptor data
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2017-07-19 19:42:25 +08:00
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* @fsl_mc: [fsl-mc] FSL MC device specific msi descriptor data
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2019-04-30 18:12:28 +08:00
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* @inta: [INTA] TISCI based INTA specific msi descriptor data
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2015-07-09 16:00:46 +08:00
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*/
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2006-10-04 17:16:59 +08:00
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struct msi_desc {
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2015-07-09 16:00:46 +08:00
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/* Shared device/bus type independent data */
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struct list_head list;
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unsigned int irq;
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unsigned int nvec_used;
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struct device *dev;
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struct msi_msg msg;
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2018-12-04 23:51:20 +08:00
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struct irq_affinity_desc *affinity;
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2019-05-01 21:58:18 +08:00
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#ifdef CONFIG_IRQ_MSI_IOMMU
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const void *iommu_cookie;
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#endif
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2006-10-04 17:16:59 +08:00
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2019-05-24 06:30:51 +08:00
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void (*write_msi_msg)(struct msi_desc *entry, void *data);
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void *write_msi_msg_data;
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2009-03-17 20:54:08 +08:00
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union {
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2015-07-09 16:00:46 +08:00
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/* PCI MSI/X specific data */
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struct {
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u32 masked;
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struct {
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2019-02-09 00:54:38 +08:00
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u8 is_msix : 1;
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u8 multiple : 3;
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u8 multi_cap : 3;
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u8 maskbit : 1;
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u8 is_64 : 1;
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2019-05-24 06:30:51 +08:00
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u8 is_virtual : 1;
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2019-02-09 00:54:38 +08:00
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u16 entry_nr;
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2015-07-09 16:00:46 +08:00
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unsigned default_irq;
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} msi_attrib;
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union {
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u8 mask_pos;
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void __iomem *mask_base;
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};
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};
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2006-10-04 17:16:59 +08:00
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2015-07-09 16:00:46 +08:00
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/*
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* Non PCI variants add their data structure here. New
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* entries need to use a named structure. We want
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* proper name spaces for this. The PCI part is
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* anonymous for now as it would require an immediate
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* tree wide cleanup.
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*/
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2015-07-28 21:46:16 +08:00
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struct platform_msi_desc platform;
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2016-01-07 06:03:20 +08:00
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struct fsl_mc_msi_desc fsl_mc;
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2019-04-30 18:12:28 +08:00
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struct ti_sci_inta_msi_desc inta;
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2015-07-09 16:00:46 +08:00
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};
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2006-10-04 17:16:59 +08:00
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};
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2014-11-15 22:24:03 +08:00
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/* Helpers to hide struct msi_desc implementation details */
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2015-07-09 16:00:45 +08:00
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#define msi_desc_to_dev(desc) ((desc)->dev)
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2015-07-09 16:00:44 +08:00
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#define dev_to_msi_list(dev) (&(dev)->msi_list)
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2014-11-15 22:24:03 +08:00
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#define first_msi_entry(dev) \
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list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list)
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#define for_each_msi_entry(desc, dev) \
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list_for_each_entry((desc), dev_to_msi_list((dev)), list)
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2018-10-11 17:12:34 +08:00
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#define for_each_msi_entry_safe(desc, tmp, dev) \
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list_for_each_entry_safe((desc), (tmp), dev_to_msi_list((dev)), list)
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2021-01-23 20:27:59 +08:00
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#define for_each_msi_vector(desc, __irq, dev) \
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for_each_msi_entry((desc), (dev)) \
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if ((desc)->irq) \
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for (__irq = (desc)->irq; \
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__irq < ((desc)->irq + (desc)->nvec_used); \
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__irq++)
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2014-11-15 22:24:03 +08:00
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2019-05-01 21:58:18 +08:00
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#ifdef CONFIG_IRQ_MSI_IOMMU
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static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
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{
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return desc->iommu_cookie;
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}
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static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
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const void *iommu_cookie)
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{
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desc->iommu_cookie = iommu_cookie;
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}
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#else
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static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
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{
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return NULL;
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}
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static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
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const void *iommu_cookie)
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{
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}
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#endif
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2014-11-15 22:24:03 +08:00
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#ifdef CONFIG_PCI_MSI
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#define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev)
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#define for_each_pci_msi_entry(desc, pdev) \
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for_each_msi_entry((desc), &(pdev)->dev)
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2015-07-09 16:00:45 +08:00
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struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc);
|
2015-07-09 16:00:36 +08:00
|
|
|
void *msi_desc_to_pci_sysdata(struct msi_desc *desc);
|
2017-02-15 05:53:12 +08:00
|
|
|
void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg);
|
2015-07-09 16:00:36 +08:00
|
|
|
#else /* CONFIG_PCI_MSI */
|
|
|
|
|
static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
|
|
|
|
|
{
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
2017-02-15 05:53:12 +08:00
|
|
|
static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
|
|
|
|
|
{
|
|
|
|
|
}
|
2014-11-15 22:24:03 +08:00
|
|
|
#endif /* CONFIG_PCI_MSI */
|
|
|
|
|
|
2016-09-14 22:18:47 +08:00
|
|
|
struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
|
2018-12-04 23:51:20 +08:00
|
|
|
const struct irq_affinity_desc *affinity);
|
2015-07-09 16:00:47 +08:00
|
|
|
void free_msi_entry(struct msi_desc *entry);
|
2014-11-09 23:10:33 +08:00
|
|
|
void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
2014-11-09 23:10:34 +08:00
|
|
|
void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
|
|
|
|
|
2014-11-23 18:55:58 +08:00
|
|
|
u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag);
|
|
|
|
|
u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
|
|
|
|
|
void pci_msi_mask_irq(struct irq_data *data);
|
|
|
|
|
void pci_msi_unmask_irq(struct irq_data *data);
|
|
|
|
|
|
2006-10-04 17:16:59 +08:00
|
|
|
/*
|
2020-08-26 19:17:02 +08:00
|
|
|
* The arch hooks to setup up msi irqs. Default functions are implemented
|
|
|
|
|
* as weak symbols so that they /can/ be overriden by architecture specific
|
|
|
|
|
* code if needed. These hooks must be enabled by the architecture or by
|
|
|
|
|
* drivers which depend on them via msi_controller based MSI handling.
|
|
|
|
|
*
|
|
|
|
|
* If CONFIG_PCI_MSI_ARCH_FALLBACKS is not selected they are replaced by
|
|
|
|
|
* stubs with warnings.
|
2006-10-04 17:16:59 +08:00
|
|
|
*/
|
2020-08-26 19:17:02 +08:00
|
|
|
#ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
|
2007-01-29 03:56:37 +08:00
|
|
|
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
|
2006-10-04 17:16:59 +08:00
|
|
|
void arch_teardown_msi_irq(unsigned int irq);
|
2013-04-19 00:55:46 +08:00
|
|
|
int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
|
|
|
|
|
void arch_teardown_msi_irqs(struct pci_dev *dev);
|
2013-08-10 04:27:06 +08:00
|
|
|
void default_teardown_msi_irqs(struct pci_dev *dev);
|
2020-08-26 19:17:02 +08:00
|
|
|
#else
|
|
|
|
|
static inline int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
|
|
|
|
|
{
|
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void arch_teardown_msi_irqs(struct pci_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The restore hooks are still available as they are useful even
|
|
|
|
|
* for fully irq domain based setups. Courtesy to XEN/X86.
|
|
|
|
|
*/
|
|
|
|
|
void arch_restore_msi_irqs(struct pci_dev *dev);
|
2013-12-04 13:09:16 +08:00
|
|
|
void default_restore_msi_irqs(struct pci_dev *dev);
|
2006-10-04 17:16:59 +08:00
|
|
|
|
2014-11-12 08:45:45 +08:00
|
|
|
struct msi_controller {
|
2013-08-10 04:27:08 +08:00
|
|
|
struct module *owner;
|
|
|
|
|
struct device *dev;
|
2013-08-10 04:27:09 +08:00
|
|
|
struct device_node *of_node;
|
|
|
|
|
struct list_head list;
|
2013-08-10 04:27:08 +08:00
|
|
|
|
2014-11-12 08:45:45 +08:00
|
|
|
int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev,
|
2013-08-10 04:27:08 +08:00
|
|
|
struct msi_desc *desc);
|
2015-09-19 02:58:34 +08:00
|
|
|
int (*setup_irqs)(struct msi_controller *chip, struct pci_dev *dev,
|
|
|
|
|
int nvec, int type);
|
2014-11-12 08:45:45 +08:00
|
|
|
void (*teardown_irq)(struct msi_controller *chip, unsigned int irq);
|
2013-08-10 04:27:08 +08:00
|
|
|
};
|
|
|
|
|
|
2014-11-12 18:39:03 +08:00
|
|
|
#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
|
2014-11-15 22:24:04 +08:00
|
|
|
|
2014-11-15 22:24:05 +08:00
|
|
|
#include <linux/irqhandler.h>
|
2014-11-15 22:24:04 +08:00
|
|
|
|
2014-11-12 18:39:03 +08:00
|
|
|
struct irq_domain;
|
platform-msi: Allow creation of a MSI-based stacked irq domain
We almost have all the needed bits requiredable to create a irq domain
on top of a MSI domain.
For this, we enable a few things:
- the virq is stored in the msi_desc
- device, msi_alloc_info and domain-specific data
are stored in the platform_priv_data structure
- we introduce a new API for platform-msi:
/* Create a MSI-based domain */
struct irq_domain *
platform_msi_create_device_domain(struct device *dev,
unsigned int nvec,
irq_write_msi_msg_t write_msi_msg,
const struct irq_domain_ops *ops,
void *host_data);
/* Allocate MSIs in an MSI domain */
int platform_msi_domain_alloc(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs);
/* Free MSIs from an MSI domain */
void platform_msi_domain_free(struct irq_domain *domain,
unsigned int virq,
unsigned int nvec);
/* Obtain the host data passed to platform_msi_create_device_domain */
void *platform_msi_get_host_data(struct irq_domain *domain);
platform_msi_create_device_domain() is a hybrid of irqdomain creation
and interrupt allocation, creating a domain backed by the MSIs associated
to a device. IRQs can then be allocated in that domain using
platform_msi_domain_alloc().
This now allows a wired irq to MSI bridge to be created.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-11-23 16:26:07 +08:00
|
|
|
struct irq_domain_ops;
|
2014-11-12 18:39:03 +08:00
|
|
|
struct irq_chip;
|
|
|
|
|
struct device_node;
|
2015-10-13 19:51:44 +08:00
|
|
|
struct fwnode_handle;
|
2014-11-12 18:39:03 +08:00
|
|
|
struct msi_domain_info;
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* struct msi_domain_ops - MSI interrupt domain callbacks
|
|
|
|
|
* @get_hwirq: Retrieve the resulting hw irq number
|
|
|
|
|
* @msi_init: Domain specific init function for MSI interrupts
|
|
|
|
|
* @msi_free: Domain specific function to free a MSI interrupts
|
2014-11-15 22:24:04 +08:00
|
|
|
* @msi_check: Callback for verification of the domain/info/dev data
|
|
|
|
|
* @msi_prepare: Prepare the allocation of the interrupts in the domain
|
2015-12-21 21:13:08 +08:00
|
|
|
* @msi_finish: Optional callback to finalize the allocation
|
2014-11-15 22:24:04 +08:00
|
|
|
* @set_desc: Set the msi descriptor for an interrupt
|
|
|
|
|
* @handle_error: Optional error handler if the allocation fails
|
2020-08-26 19:16:57 +08:00
|
|
|
* @domain_alloc_irqs: Optional function to override the default allocation
|
|
|
|
|
* function.
|
|
|
|
|
* @domain_free_irqs: Optional function to override the default free
|
|
|
|
|
* function.
|
2014-11-15 22:24:04 +08:00
|
|
|
*
|
|
|
|
|
* @get_hwirq, @msi_init and @msi_free are callbacks used by
|
|
|
|
|
* msi_create_irq_domain() and related interfaces
|
|
|
|
|
*
|
|
|
|
|
* @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
|
2015-12-21 21:13:08 +08:00
|
|
|
* are callbacks used by msi_domain_alloc_irqs() and related
|
2014-11-15 22:24:04 +08:00
|
|
|
* interfaces which are based on msi_desc.
|
2020-08-26 19:16:57 +08:00
|
|
|
*
|
|
|
|
|
* @domain_alloc_irqs, @domain_free_irqs can be used to override the
|
|
|
|
|
* default allocation/free functions (__msi_domain_alloc/free_irqs). This
|
|
|
|
|
* is initially for a wrapper around XENs seperate MSI universe which can't
|
|
|
|
|
* be wrapped into the regular irq domains concepts by mere mortals. This
|
|
|
|
|
* allows to universally use msi_domain_alloc/free_irqs without having to
|
|
|
|
|
* special case XEN all over the place.
|
|
|
|
|
*
|
|
|
|
|
* Contrary to other operations @domain_alloc_irqs and @domain_free_irqs
|
|
|
|
|
* are set to the default implementation if NULL and even when
|
|
|
|
|
* MSI_FLAG_USE_DEF_DOM_OPS is not set to avoid breaking existing users and
|
|
|
|
|
* because these callbacks are obviously mandatory.
|
|
|
|
|
*
|
|
|
|
|
* This is NOT meant to be abused, but it can be useful to build wrappers
|
|
|
|
|
* for specialized MSI irq domains which need extra work before and after
|
|
|
|
|
* calling __msi_domain_alloc_irqs()/__msi_domain_free_irqs().
|
2014-11-12 18:39:03 +08:00
|
|
|
*/
|
|
|
|
|
struct msi_domain_ops {
|
2014-11-15 22:24:05 +08:00
|
|
|
irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info,
|
|
|
|
|
msi_alloc_info_t *arg);
|
2014-11-12 18:39:03 +08:00
|
|
|
int (*msi_init)(struct irq_domain *domain,
|
|
|
|
|
struct msi_domain_info *info,
|
|
|
|
|
unsigned int virq, irq_hw_number_t hwirq,
|
2014-11-15 22:24:05 +08:00
|
|
|
msi_alloc_info_t *arg);
|
2014-11-12 18:39:03 +08:00
|
|
|
void (*msi_free)(struct irq_domain *domain,
|
|
|
|
|
struct msi_domain_info *info,
|
|
|
|
|
unsigned int virq);
|
2014-11-15 22:24:04 +08:00
|
|
|
int (*msi_check)(struct irq_domain *domain,
|
|
|
|
|
struct msi_domain_info *info,
|
|
|
|
|
struct device *dev);
|
|
|
|
|
int (*msi_prepare)(struct irq_domain *domain,
|
|
|
|
|
struct device *dev, int nvec,
|
|
|
|
|
msi_alloc_info_t *arg);
|
|
|
|
|
void (*msi_finish)(msi_alloc_info_t *arg, int retval);
|
|
|
|
|
void (*set_desc)(msi_alloc_info_t *arg,
|
|
|
|
|
struct msi_desc *desc);
|
|
|
|
|
int (*handle_error)(struct irq_domain *domain,
|
|
|
|
|
struct msi_desc *desc, int error);
|
2020-08-26 19:16:57 +08:00
|
|
|
int (*domain_alloc_irqs)(struct irq_domain *domain,
|
|
|
|
|
struct device *dev, int nvec);
|
|
|
|
|
void (*domain_free_irqs)(struct irq_domain *domain,
|
|
|
|
|
struct device *dev);
|
2014-11-12 18:39:03 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* struct msi_domain_info - MSI interrupt domain data
|
2014-11-15 22:24:05 +08:00
|
|
|
* @flags: Flags to decribe features and capabilities
|
|
|
|
|
* @ops: The callback data structure
|
|
|
|
|
* @chip: Optional: associated interrupt chip
|
|
|
|
|
* @chip_data: Optional: associated interrupt chip data
|
|
|
|
|
* @handler: Optional: associated interrupt flow handler
|
|
|
|
|
* @handler_data: Optional: associated interrupt flow handler data
|
|
|
|
|
* @handler_name: Optional: associated interrupt flow handler name
|
|
|
|
|
* @data: Optional: domain specific data
|
2014-11-12 18:39:03 +08:00
|
|
|
*/
|
|
|
|
|
struct msi_domain_info {
|
2014-11-15 22:24:05 +08:00
|
|
|
u32 flags;
|
2014-11-12 18:39:03 +08:00
|
|
|
struct msi_domain_ops *ops;
|
|
|
|
|
struct irq_chip *chip;
|
2014-11-15 22:24:05 +08:00
|
|
|
void *chip_data;
|
|
|
|
|
irq_flow_handler_t handler;
|
|
|
|
|
void *handler_data;
|
|
|
|
|
const char *handler_name;
|
2014-11-12 18:39:03 +08:00
|
|
|
void *data;
|
|
|
|
|
};
|
|
|
|
|
|
2014-11-15 22:24:05 +08:00
|
|
|
/* Flags for msi_domain_info */
|
|
|
|
|
enum {
|
|
|
|
|
/*
|
|
|
|
|
* Init non implemented ops callbacks with default MSI domain
|
|
|
|
|
* callbacks.
|
|
|
|
|
*/
|
|
|
|
|
MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0),
|
|
|
|
|
/*
|
|
|
|
|
* Init non implemented chip callbacks with default MSI chip
|
|
|
|
|
* callbacks.
|
|
|
|
|
*/
|
|
|
|
|
MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1),
|
|
|
|
|
/* Support multiple PCI MSI interrupts */
|
2016-07-04 16:39:22 +08:00
|
|
|
MSI_FLAG_MULTI_PCI_MSI = (1 << 2),
|
2014-11-15 22:24:05 +08:00
|
|
|
/* Support PCI MSIX interrupts */
|
2016-07-04 16:39:22 +08:00
|
|
|
MSI_FLAG_PCI_MSIX = (1 << 3),
|
2016-07-14 00:18:33 +08:00
|
|
|
/* Needs early activate, required for PCI */
|
|
|
|
|
MSI_FLAG_ACTIVATE_EARLY = (1 << 4),
|
2017-09-14 05:29:13 +08:00
|
|
|
/*
|
|
|
|
|
* Must reactivate when irq is started even when
|
|
|
|
|
* MSI_FLAG_ACTIVATE_EARLY has been set.
|
|
|
|
|
*/
|
|
|
|
|
MSI_FLAG_MUST_REACTIVATE = (1 << 5),
|
genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
|
|
|
/* Is level-triggered capable, using two messages */
|
|
|
|
|
MSI_FLAG_LEVEL_CAPABLE = (1 << 6),
|
2014-11-15 22:24:05 +08:00
|
|
|
};
|
|
|
|
|
|
2014-11-12 18:39:03 +08:00
|
|
|
int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask,
|
|
|
|
|
bool force);
|
|
|
|
|
|
2015-10-13 19:51:44 +08:00
|
|
|
struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
|
2014-11-12 18:39:03 +08:00
|
|
|
struct msi_domain_info *info,
|
|
|
|
|
struct irq_domain *parent);
|
2020-08-26 19:16:57 +08:00
|
|
|
int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
|
|
|
|
|
int nvec);
|
2014-11-15 22:24:04 +08:00
|
|
|
int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
|
|
|
|
|
int nvec);
|
2020-08-26 19:16:57 +08:00
|
|
|
void __msi_domain_free_irqs(struct irq_domain *domain, struct device *dev);
|
2014-11-15 22:24:04 +08:00
|
|
|
void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev);
|
2014-11-12 18:39:03 +08:00
|
|
|
struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain);
|
|
|
|
|
|
2015-10-13 19:51:44 +08:00
|
|
|
struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode,
|
2015-07-28 21:46:16 +08:00
|
|
|
struct msi_domain_info *info,
|
|
|
|
|
struct irq_domain *parent);
|
|
|
|
|
int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
|
|
|
|
|
irq_write_msi_msg_t write_msi_msg);
|
|
|
|
|
void platform_msi_domain_free_irqs(struct device *dev);
|
2015-11-23 16:26:05 +08:00
|
|
|
|
|
|
|
|
/* When an MSI domain is used as an intermediate domain */
|
|
|
|
|
int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
|
|
|
|
|
int nvec, msi_alloc_info_t *args);
|
2015-11-23 16:26:06 +08:00
|
|
|
int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
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int virq, int nvec, msi_alloc_info_t *args);
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platform-msi: Allow creation of a MSI-based stacked irq domain
We almost have all the needed bits requiredable to create a irq domain
on top of a MSI domain.
For this, we enable a few things:
- the virq is stored in the msi_desc
- device, msi_alloc_info and domain-specific data
are stored in the platform_priv_data structure
- we introduce a new API for platform-msi:
/* Create a MSI-based domain */
struct irq_domain *
platform_msi_create_device_domain(struct device *dev,
unsigned int nvec,
irq_write_msi_msg_t write_msi_msg,
const struct irq_domain_ops *ops,
void *host_data);
/* Allocate MSIs in an MSI domain */
int platform_msi_domain_alloc(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs);
/* Free MSIs from an MSI domain */
void platform_msi_domain_free(struct irq_domain *domain,
unsigned int virq,
unsigned int nvec);
/* Obtain the host data passed to platform_msi_create_device_domain */
void *platform_msi_get_host_data(struct irq_domain *domain);
platform_msi_create_device_domain() is a hybrid of irqdomain creation
and interrupt allocation, creating a domain backed by the MSIs associated
to a device. IRQs can then be allocated in that domain using
platform_msi_domain_alloc().
This now allows a wired irq to MSI bridge to be created.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-11-23 16:26:07 +08:00
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struct irq_domain *
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2018-10-01 22:13:45 +08:00
|
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__platform_msi_create_device_domain(struct device *dev,
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unsigned int nvec,
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bool is_tree,
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irq_write_msi_msg_t write_msi_msg,
|
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|
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const struct irq_domain_ops *ops,
|
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|
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void *host_data);
|
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|
|
|
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#define platform_msi_create_device_domain(dev, nvec, write, ops, data) \
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|
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__platform_msi_create_device_domain(dev, nvec, false, write, ops, data)
|
|
|
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#define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \
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|
|
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__platform_msi_create_device_domain(dev, nvec, true, write, ops, data)
|
|
|
|
|
|
platform-msi: Allow creation of a MSI-based stacked irq domain
We almost have all the needed bits requiredable to create a irq domain
on top of a MSI domain.
For this, we enable a few things:
- the virq is stored in the msi_desc
- device, msi_alloc_info and domain-specific data
are stored in the platform_priv_data structure
- we introduce a new API for platform-msi:
/* Create a MSI-based domain */
struct irq_domain *
platform_msi_create_device_domain(struct device *dev,
unsigned int nvec,
irq_write_msi_msg_t write_msi_msg,
const struct irq_domain_ops *ops,
void *host_data);
/* Allocate MSIs in an MSI domain */
int platform_msi_domain_alloc(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs);
/* Free MSIs from an MSI domain */
void platform_msi_domain_free(struct irq_domain *domain,
unsigned int virq,
unsigned int nvec);
/* Obtain the host data passed to platform_msi_create_device_domain */
void *platform_msi_get_host_data(struct irq_domain *domain);
platform_msi_create_device_domain() is a hybrid of irqdomain creation
and interrupt allocation, creating a domain backed by the MSIs associated
to a device. IRQs can then be allocated in that domain using
platform_msi_domain_alloc().
This now allows a wired irq to MSI bridge to be created.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-11-23 16:26:07 +08:00
|
|
|
int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
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unsigned int nr_irqs);
|
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void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq,
|
|
|
|
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unsigned int nvec);
|
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void *platform_msi_get_host_data(struct irq_domain *domain);
|
2014-11-12 18:39:03 +08:00
|
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#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
|
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|
2014-11-11 21:02:18 +08:00
|
|
|
#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
|
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void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg);
|
2015-10-13 19:51:44 +08:00
|
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struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
|
2014-11-11 21:02:18 +08:00
|
|
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struct msi_domain_info *info,
|
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struct irq_domain *parent);
|
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int pci_msi_domain_check_cap(struct irq_domain *domain,
|
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|
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struct msi_domain_info *info, struct device *dev);
|
2015-10-09 06:10:49 +08:00
|
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u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev);
|
2015-10-02 21:43:06 +08:00
|
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|
struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev);
|
2020-08-26 19:16:53 +08:00
|
|
|
bool pci_dev_has_special_msi_domain(struct pci_dev *pdev);
|
2015-10-02 21:43:06 +08:00
|
|
|
#else
|
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|
|
static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
|
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|
|
{
|
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|
return NULL;
|
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}
|
2014-11-11 21:02:18 +08:00
|
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|
#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
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2006-10-04 17:16:59 +08:00
|
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#endif /* LINUX_MSI_H */
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