2019-05-27 14:55:22 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2008-11-13 05:25:38 +08:00
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/*
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2013-06-03 20:31:17 +08:00
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* Xilinx gpio driver for xps/axi_gpio IP.
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2008-11-13 05:25:38 +08:00
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*
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2013-06-03 20:31:17 +08:00
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* Copyright 2008 - 2013 Xilinx, Inc.
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2008-11-13 05:25:38 +08:00
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*/
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2013-06-03 20:31:17 +08:00
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#include <linux/bitops.h>
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2020-11-13 01:12:22 +08:00
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#include <linux/clk.h>
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2008-11-13 05:25:38 +08:00
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#include <linux/errno.h>
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2020-11-13 01:12:20 +08:00
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/io.h>
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2011-07-04 01:38:09 +08:00
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#include <linux/module.h>
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2008-11-13 05:25:38 +08:00
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2008-11-13 05:25:38 +08:00
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/* Register Offset Definitions */
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#define XGPIO_DATA_OFFSET (0x0) /* Data register */
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#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
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2013-06-03 20:31:17 +08:00
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#define XGPIO_CHANNEL_OFFSET 0x8
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/* Read/Write access to the GPIO registers */
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2014-12-17 23:51:10 +08:00
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#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
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2013-06-03 20:31:18 +08:00
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# define xgpio_readreg(offset) readl(offset)
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# define xgpio_writereg(offset, val) writel(val, offset)
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#else
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# define xgpio_readreg(offset) __raw_readl(offset)
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# define xgpio_writereg(offset, val) __raw_writel(val, offset)
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#endif
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2013-06-03 20:31:17 +08:00
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/**
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* struct xgpio_instance - Stores information about GPIO device
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2019-06-08 01:04:16 +08:00
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* @gc: GPIO chip
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* @regs: register block
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2015-05-04 22:37:16 +08:00
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* @gpio_width: GPIO width for every channel
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2014-12-17 23:51:11 +08:00
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* @gpio_state: GPIO state shadow register
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* @gpio_dir: GPIO direction shadow register
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* @gpio_lock: Lock used for synchronization
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2020-11-13 01:12:22 +08:00
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* @clk: clock resource for this driver
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2013-06-03 20:31:17 +08:00
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*/
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2008-11-13 05:25:38 +08:00
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struct xgpio_instance {
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2019-06-08 01:04:16 +08:00
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struct gpio_chip gc;
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void __iomem *regs;
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2014-12-17 23:51:12 +08:00
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unsigned int gpio_width[2];
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u32 gpio_state[2];
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u32 gpio_dir[2];
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spinlock_t gpio_lock[2];
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2020-11-13 01:12:22 +08:00
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struct clk *clk;
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2014-12-17 23:51:09 +08:00
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};
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2014-12-17 23:51:12 +08:00
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static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
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{
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if (gpio >= chip->gpio_width[0])
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return 1;
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return 0;
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}
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static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
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{
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if (xgpio_index(chip, gpio))
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return XGPIO_CHANNEL_OFFSET;
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return 0;
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}
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static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
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{
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if (xgpio_index(chip, gpio))
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return gpio - chip->gpio_width[0];
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return gpio;
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}
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2008-11-13 05:25:38 +08:00
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/**
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* xgpio_get - Read the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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2014-12-17 23:51:11 +08:00
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* This function reads the specified signal of the GPIO device.
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*
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* Return:
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* 0 if direction of GPIO signals is set as input otherwise it
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* returns negative error value.
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2008-11-13 05:25:38 +08:00
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*/
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static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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2015-12-07 22:20:17 +08:00
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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2014-12-17 23:51:12 +08:00
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u32 val;
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2008-11-13 05:25:38 +08:00
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2019-06-08 01:04:16 +08:00
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val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
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2014-12-17 23:51:12 +08:00
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xgpio_regoffset(chip, gpio));
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return !!(val & BIT(xgpio_offset(chip, gpio)));
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2008-11-13 05:25:38 +08:00
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}
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/**
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* xgpio_set - Write the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* This function writes the specified value in to the specified signal of the
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* GPIO device.
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*/
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static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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2015-12-07 22:20:17 +08:00
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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2014-12-17 23:51:12 +08:00
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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2008-11-13 05:25:38 +08:00
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2014-12-17 23:51:12 +08:00
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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2008-11-13 05:25:38 +08:00
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/* Write to GPIO signal and set its direction to output */
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if (val)
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2014-12-17 23:51:12 +08:00
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chip->gpio_state[index] |= BIT(offset);
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2008-11-13 05:25:38 +08:00
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else
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2014-12-17 23:51:12 +08:00
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chip->gpio_state[index] &= ~BIT(offset);
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2013-06-03 20:31:17 +08:00
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2019-06-08 01:04:16 +08:00
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
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2014-12-17 23:51:12 +08:00
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xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
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2008-11-13 05:25:38 +08:00
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2014-12-17 23:51:12 +08:00
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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2008-11-13 05:25:38 +08:00
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}
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2016-06-03 20:54:41 +08:00
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/**
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* xgpio_set_multiple - Write the specified signals of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @mask: Mask of the GPIOS to modify.
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* @bits: Value to be wrote on each GPIO
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*
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* This function writes the specified values into the specified signals of the
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* GPIO devices.
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*/
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static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, 0);
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int offset, i;
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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/* Write to GPIO signals */
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for (i = 0; i < gc->ngpio; i++) {
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if (*mask == 0)
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break;
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2020-01-26 06:14:10 +08:00
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/* Once finished with an index write it out to the register */
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2016-06-03 20:54:41 +08:00
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if (index != xgpio_index(chip, i)) {
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2019-06-08 01:04:16 +08:00
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
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2020-01-26 06:14:10 +08:00
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index * XGPIO_CHANNEL_OFFSET,
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2016-06-03 20:54:41 +08:00
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chip->gpio_state[index]);
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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index = xgpio_index(chip, i);
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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}
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if (__test_and_clear_bit(i, mask)) {
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offset = xgpio_offset(chip, i);
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if (test_bit(i, bits))
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chip->gpio_state[index] |= BIT(offset);
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else
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chip->gpio_state[index] &= ~BIT(offset);
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}
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}
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2019-06-08 01:04:16 +08:00
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
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2020-01-26 06:14:10 +08:00
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index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);
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2016-06-03 20:54:41 +08:00
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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}
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2008-11-13 05:25:38 +08:00
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/**
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* xgpio_dir_in - Set the direction of the specified GPIO signal as input.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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2014-12-17 23:51:11 +08:00
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* Return:
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* 0 - if direction of GPIO signals is set as input
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* otherwise it returns negative error value.
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2008-11-13 05:25:38 +08:00
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*/
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static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long flags;
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2015-12-07 22:20:17 +08:00
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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2014-12-17 23:51:12 +08:00
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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2008-11-13 05:25:38 +08:00
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2014-12-17 23:51:12 +08:00
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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2008-11-13 05:25:38 +08:00
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/* Set the GPIO bit in shadow register and set direction as input */
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2014-12-17 23:51:12 +08:00
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chip->gpio_dir[index] |= BIT(offset);
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2019-06-08 01:04:16 +08:00
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xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
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2014-12-17 23:51:12 +08:00
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xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
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2008-11-13 05:25:38 +08:00
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2014-12-17 23:51:12 +08:00
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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2008-11-13 05:25:38 +08:00
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return 0;
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}
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/**
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* xgpio_dir_out - Set the direction of the specified GPIO signal as output.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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2014-12-17 23:51:11 +08:00
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* This function sets the direction of specified GPIO signal as output.
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*
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* Return:
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* If all GPIO signals of GPIO chip is configured as input then it returns
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2008-11-13 05:25:38 +08:00
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* error otherwise it returns 0.
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*/
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static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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2015-12-07 22:20:17 +08:00
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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2014-12-17 23:51:12 +08:00
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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2008-11-13 05:25:38 +08:00
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2014-12-17 23:51:12 +08:00
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spin_lock_irqsave(&chip->gpio_lock[index], flags);
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2008-11-13 05:25:38 +08:00
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/* Write state of GPIO signal */
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if (val)
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2014-12-17 23:51:12 +08:00
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chip->gpio_state[index] |= BIT(offset);
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2008-11-13 05:25:38 +08:00
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else
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2014-12-17 23:51:12 +08:00
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chip->gpio_state[index] &= ~BIT(offset);
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2019-06-08 01:04:16 +08:00
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
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2014-12-17 23:51:12 +08:00
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xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
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2008-11-13 05:25:38 +08:00
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/* Clear the GPIO bit in shadow register and set direction as output */
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2014-12-17 23:51:12 +08:00
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chip->gpio_dir[index] &= ~BIT(offset);
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2019-06-08 01:04:16 +08:00
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xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
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2014-12-17 23:51:12 +08:00
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xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
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2008-11-13 05:25:38 +08:00
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2014-12-17 23:51:12 +08:00
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spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
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2008-11-13 05:25:38 +08:00
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return 0;
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}
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/**
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* xgpio_save_regs - Set initial values of GPIO pins
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2019-06-08 01:04:16 +08:00
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* @chip: Pointer to GPIO instance
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2008-11-13 05:25:38 +08:00
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*/
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2019-06-08 01:04:16 +08:00
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static void xgpio_save_regs(struct xgpio_instance *chip)
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2008-11-13 05:25:38 +08:00
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{
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2019-06-08 01:04:16 +08:00
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]);
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xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
|
2014-12-17 23:51:12 +08:00
|
|
|
|
|
|
|
if (!chip->gpio_width[1])
|
|
|
|
return;
|
|
|
|
|
2019-06-08 01:04:16 +08:00
|
|
|
xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
|
2014-12-17 23:51:12 +08:00
|
|
|
chip->gpio_state[1]);
|
2019-06-08 01:04:16 +08:00
|
|
|
xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
|
2014-12-17 23:51:12 +08:00
|
|
|
chip->gpio_dir[1]);
|
2008-11-13 05:25:38 +08:00
|
|
|
}
|
|
|
|
|
2020-11-13 01:12:25 +08:00
|
|
|
/**
|
|
|
|
* xgpio_remove - Remove method for the GPIO device.
|
|
|
|
* @pdev: pointer to the platform device
|
|
|
|
*
|
|
|
|
* This function remove gpiochips and frees all the allocated resources.
|
|
|
|
*
|
|
|
|
* Return: 0 always
|
|
|
|
*/
|
|
|
|
static int xgpio_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct xgpio_instance *gpio = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
clk_disable_unprepare(gpio->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-11-13 05:25:38 +08:00
|
|
|
/**
|
|
|
|
* xgpio_of_probe - Probe method for the GPIO device.
|
2014-12-17 23:51:09 +08:00
|
|
|
* @pdev: pointer to the platform device
|
2008-11-13 05:25:38 +08:00
|
|
|
*
|
2014-12-17 23:51:11 +08:00
|
|
|
* Return:
|
|
|
|
* It returns 0, if the driver is bound to the GPIO device, or
|
|
|
|
* a negative value if there is an error.
|
2008-11-13 05:25:38 +08:00
|
|
|
*/
|
2014-12-17 23:51:09 +08:00
|
|
|
static int xgpio_probe(struct platform_device *pdev)
|
2008-11-13 05:25:38 +08:00
|
|
|
{
|
|
|
|
struct xgpio_instance *chip;
|
|
|
|
int status = 0;
|
2014-12-17 23:51:09 +08:00
|
|
|
struct device_node *np = pdev->dev.of_node;
|
2014-12-17 23:51:12 +08:00
|
|
|
u32 is_dual;
|
2008-11-13 05:25:38 +08:00
|
|
|
|
2014-12-17 23:51:12 +08:00
|
|
|
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
|
|
|
|
if (!chip)
|
2008-11-13 05:25:38 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2014-12-17 23:51:12 +08:00
|
|
|
platform_set_drvdata(pdev, chip);
|
2014-12-17 23:51:09 +08:00
|
|
|
|
2008-11-13 05:25:38 +08:00
|
|
|
/* Update GPIO state shadow register with default value */
|
2020-11-13 01:12:27 +08:00
|
|
|
if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]))
|
|
|
|
chip->gpio_state[0] = 0x0;
|
2008-11-13 05:25:38 +08:00
|
|
|
|
|
|
|
/* Update GPIO direction shadow register with default value */
|
2014-12-17 23:51:12 +08:00
|
|
|
if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
|
|
|
|
chip->gpio_dir[0] = 0xFFFFFFFF;
|
2013-06-03 20:31:16 +08:00
|
|
|
|
2014-09-24 06:58:45 +08:00
|
|
|
/*
|
|
|
|
* Check device node and parent device node for device width
|
|
|
|
* and assume default width of 32
|
|
|
|
*/
|
2014-12-17 23:51:12 +08:00
|
|
|
if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
|
|
|
|
chip->gpio_width[0] = 32;
|
|
|
|
|
|
|
|
spin_lock_init(&chip->gpio_lock[0]);
|
|
|
|
|
|
|
|
if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
|
|
|
|
is_dual = 0;
|
2008-11-13 05:25:38 +08:00
|
|
|
|
2014-12-17 23:51:12 +08:00
|
|
|
if (is_dual) {
|
|
|
|
/* Update GPIO state shadow register with default value */
|
2020-11-13 01:12:27 +08:00
|
|
|
if (of_property_read_u32(np, "xlnx,dout-default-2",
|
|
|
|
&chip->gpio_state[1]))
|
|
|
|
chip->gpio_state[1] = 0x0;
|
2014-12-17 23:51:12 +08:00
|
|
|
|
|
|
|
/* Update GPIO direction shadow register with default value */
|
|
|
|
if (of_property_read_u32(np, "xlnx,tri-default-2",
|
|
|
|
&chip->gpio_dir[1]))
|
|
|
|
chip->gpio_dir[1] = 0xFFFFFFFF;
|
2008-11-13 05:25:38 +08:00
|
|
|
|
2014-12-17 23:51:12 +08:00
|
|
|
/*
|
|
|
|
* Check device node and parent device node for device width
|
|
|
|
* and assume default width of 32
|
|
|
|
*/
|
|
|
|
if (of_property_read_u32(np, "xlnx,gpio2-width",
|
|
|
|
&chip->gpio_width[1]))
|
|
|
|
chip->gpio_width[1] = 32;
|
|
|
|
|
|
|
|
spin_lock_init(&chip->gpio_lock[1]);
|
|
|
|
}
|
|
|
|
|
2019-06-08 01:04:16 +08:00
|
|
|
chip->gc.base = -1;
|
|
|
|
chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
|
|
|
|
chip->gc.parent = &pdev->dev;
|
|
|
|
chip->gc.direction_input = xgpio_dir_in;
|
|
|
|
chip->gc.direction_output = xgpio_dir_out;
|
|
|
|
chip->gc.get = xgpio_get;
|
|
|
|
chip->gc.set = xgpio_set;
|
|
|
|
chip->gc.set_multiple = xgpio_set_multiple;
|
|
|
|
|
|
|
|
chip->gc.label = dev_name(&pdev->dev);
|
|
|
|
|
|
|
|
chip->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
if (IS_ERR(chip->regs)) {
|
|
|
|
dev_err(&pdev->dev, "failed to ioremap memory resource\n");
|
|
|
|
return PTR_ERR(chip->regs);
|
|
|
|
}
|
2008-11-13 05:25:38 +08:00
|
|
|
|
2020-11-13 01:12:22 +08:00
|
|
|
chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
|
2021-01-29 22:26:46 +08:00
|
|
|
if (IS_ERR(chip->clk))
|
|
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
|
2020-11-13 01:12:22 +08:00
|
|
|
|
|
|
|
status = clk_prepare_enable(chip->clk);
|
|
|
|
if (status < 0) {
|
|
|
|
dev_err(&pdev->dev, "Failed to prepare clk\n");
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2019-06-08 01:04:16 +08:00
|
|
|
xgpio_save_regs(chip);
|
2008-11-13 05:25:38 +08:00
|
|
|
|
2019-06-08 01:04:16 +08:00
|
|
|
status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
|
2008-11-13 05:25:38 +08:00
|
|
|
if (status) {
|
2019-06-08 01:04:16 +08:00
|
|
|
dev_err(&pdev->dev, "failed to add GPIO chip\n");
|
2020-11-13 01:12:22 +08:00
|
|
|
clk_disable_unprepare(chip->clk);
|
2008-11-13 05:25:38 +08:00
|
|
|
return status;
|
|
|
|
}
|
2013-06-03 20:31:17 +08:00
|
|
|
|
2008-11-13 05:25:38 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-05-07 17:08:20 +08:00
|
|
|
static const struct of_device_id xgpio_of_match[] = {
|
2008-11-13 05:25:38 +08:00
|
|
|
{ .compatible = "xlnx,xps-gpio-1.00.a", },
|
|
|
|
{ /* end of list */ },
|
|
|
|
};
|
|
|
|
|
2014-12-17 23:51:09 +08:00
|
|
|
MODULE_DEVICE_TABLE(of, xgpio_of_match);
|
2008-11-13 05:25:38 +08:00
|
|
|
|
2014-12-17 23:51:09 +08:00
|
|
|
static struct platform_driver xgpio_plat_driver = {
|
|
|
|
.probe = xgpio_probe,
|
2020-11-13 01:12:25 +08:00
|
|
|
.remove = xgpio_remove,
|
2014-12-17 23:51:09 +08:00
|
|
|
.driver = {
|
|
|
|
.name = "gpio-xilinx",
|
|
|
|
.of_match_table = xgpio_of_match,
|
|
|
|
},
|
|
|
|
};
|
2008-11-13 05:25:38 +08:00
|
|
|
|
2014-12-17 23:51:09 +08:00
|
|
|
static int __init xgpio_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&xgpio_plat_driver);
|
2008-11-13 05:25:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
subsys_initcall(xgpio_init);
|
2014-12-17 23:51:09 +08:00
|
|
|
|
|
|
|
static void __exit xgpio_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&xgpio_plat_driver);
|
|
|
|
}
|
|
|
|
module_exit(xgpio_exit);
|
2008-11-13 05:25:38 +08:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Xilinx, Inc.");
|
|
|
|
MODULE_DESCRIPTION("Xilinx GPIO driver");
|
|
|
|
MODULE_LICENSE("GPL");
|