2017-02-08 21:27:07 +08:00
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/*
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* Copyright(c) 2016 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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2019-04-11 22:16:11 +08:00
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#include <rdma/rdmavt_qp.h>
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2017-02-08 21:28:25 +08:00
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#include <rdma/ib_hdrs.h>
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2017-02-08 21:27:07 +08:00
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/*
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* Convert the AETH credit code into the number of credits.
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*/
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static const u16 credit_table[31] = {
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0, /* 0 */
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1, /* 1 */
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2, /* 2 */
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3, /* 3 */
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4, /* 4 */
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6, /* 5 */
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8, /* 6 */
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12, /* 7 */
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16, /* 8 */
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24, /* 9 */
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32, /* A */
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48, /* B */
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64, /* C */
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96, /* D */
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128, /* E */
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192, /* F */
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256, /* 10 */
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384, /* 11 */
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512, /* 12 */
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768, /* 13 */
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1024, /* 14 */
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1536, /* 15 */
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2048, /* 16 */
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3072, /* 17 */
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4096, /* 18 */
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6144, /* 19 */
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8192, /* 1A */
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12288, /* 1B */
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16384, /* 1C */
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24576, /* 1D */
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32768 /* 1E */
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};
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/**
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* rvt_compute_aeth - compute the AETH (syndrome + MSN)
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* @qp: the queue pair to compute the AETH for
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*
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* Returns the AETH.
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*/
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__be32 rvt_compute_aeth(struct rvt_qp *qp)
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{
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2017-02-08 21:28:25 +08:00
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u32 aeth = qp->r_msn & IB_MSN_MASK;
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2017-02-08 21:27:07 +08:00
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if (qp->ibqp.srq) {
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/*
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* Shared receive queues don't generate credits.
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* Set the credit field to the invalid value.
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*/
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2017-02-08 21:28:25 +08:00
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aeth |= IB_AETH_CREDIT_INVAL << IB_AETH_CREDIT_SHIFT;
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2017-02-08 21:27:07 +08:00
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} else {
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u32 min, max, x;
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u32 credits;
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u32 head;
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u32 tail;
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2019-06-29 02:04:30 +08:00
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credits = READ_ONCE(qp->r_rq.kwq->count);
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if (credits == 0) {
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/* sanity check pointers before trusting them */
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if (qp->ip) {
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head = RDMA_READ_UAPI_ATOMIC(qp->r_rq.wq->head);
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tail = RDMA_READ_UAPI_ATOMIC(qp->r_rq.wq->tail);
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} else {
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head = READ_ONCE(qp->r_rq.kwq->head);
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tail = READ_ONCE(qp->r_rq.kwq->tail);
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}
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if (head >= qp->r_rq.size)
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head = 0;
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if (tail >= qp->r_rq.size)
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tail = 0;
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/*
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* Compute the number of credits available (RWQEs).
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* There is a small chance that the pair of reads are
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* not atomic, which is OK, since the fuzziness is
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* resolved as further ACKs go out.
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*/
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credits = head - tail;
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if ((int)credits < 0)
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credits += qp->r_rq.size;
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2019-06-29 02:04:24 +08:00
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}
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2017-02-08 21:27:07 +08:00
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/*
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* Binary search the credit table to find the code to
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* use.
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*/
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min = 0;
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max = 31;
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for (;;) {
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x = (min + max) / 2;
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if (credit_table[x] == credits)
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break;
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if (credit_table[x] > credits) {
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max = x;
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} else {
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if (min == x)
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break;
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min = x;
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}
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}
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2017-02-08 21:28:25 +08:00
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aeth |= x << IB_AETH_CREDIT_SHIFT;
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2017-02-08 21:27:07 +08:00
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}
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return cpu_to_be32(aeth);
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}
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EXPORT_SYMBOL(rvt_compute_aeth);
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/**
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* rvt_get_credit - flush the send work queue of a QP
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* @qp: the qp who's send work queue to flush
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* @aeth: the Acknowledge Extended Transport Header
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*
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* The QP s_lock should be held.
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*/
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void rvt_get_credit(struct rvt_qp *qp, u32 aeth)
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{
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struct rvt_dev_info *rdi = ib_to_rvt(qp->ibqp.device);
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2017-02-08 21:28:25 +08:00
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u32 credit = (aeth >> IB_AETH_CREDIT_SHIFT) & IB_AETH_CREDIT_MASK;
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2017-02-08 21:27:07 +08:00
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lockdep_assert_held(&qp->s_lock);
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/*
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* If the credit is invalid, we can send
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* as many packets as we like. Otherwise, we have to
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* honor the credit field.
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*/
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2017-02-08 21:28:25 +08:00
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if (credit == IB_AETH_CREDIT_INVAL) {
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2017-02-08 21:27:07 +08:00
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if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
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qp->s_flags |= RVT_S_UNLIMITED_CREDIT;
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if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
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qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
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rdi->driver_f.schedule_send(qp);
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}
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}
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} else if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
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/* Compute new LSN (i.e., MSN + credit) */
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2017-02-08 21:28:25 +08:00
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credit = (aeth + credit_table[credit]) & IB_MSN_MASK;
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2017-02-08 21:27:07 +08:00
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if (rvt_cmp_msn(credit, qp->s_lsn) > 0) {
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qp->s_lsn = credit;
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if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
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qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
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rdi->driver_f.schedule_send(qp);
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}
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}
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}
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}
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EXPORT_SYMBOL(rvt_get_credit);
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2019-01-24 11:29:44 +08:00
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/* rvt_restart_sge - rewind the sge state for a wqe */
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u32 rvt_restart_sge(struct rvt_sge_state *ss, struct rvt_swqe *wqe, u32 len)
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{
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ss->sge = wqe->sg_list[0];
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ss->sg_list = wqe->sg_list + 1;
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ss->num_sge = wqe->wr.num_sge;
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ss->total_len = wqe->length;
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rvt_skip_sge(ss, len, false);
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return wqe->length - len;
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}
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EXPORT_SYMBOL(rvt_restart_sge);
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