2019-06-04 16:11:33 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2008-04-27 19:55:59 +08:00
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/****************************************************************************
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2013-08-30 06:32:48 +08:00
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* Driver for Solarflare network controllers and boards
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2008-04-27 19:55:59 +08:00
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* Copyright 2005-2006 Fen Systems Ltd.
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2013-08-30 06:32:48 +08:00
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* Copyright 2006-2013 Solarflare Communications Inc.
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2008-04-27 19:55:59 +08:00
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*/
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2009-11-29 23:12:08 +08:00
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#ifndef EFX_NIC_H
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#define EFX_NIC_H
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2008-04-27 19:55:59 +08:00
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2020-06-29 21:34:39 +08:00
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#include "nic_common.h"
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2008-12-13 13:50:08 +08:00
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#include "efx.h"
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2008-04-27 19:55:59 +08:00
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2013-09-24 02:37:59 +08:00
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u32 efx_farch_fpga_ver(struct efx_nic *efx);
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2009-11-29 11:43:56 +08:00
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2009-11-29 23:08:55 +08:00
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enum {
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PHY_TYPE_NONE = 0,
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PHY_TYPE_TXC43128 = 1,
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PHY_TYPE_88E1111 = 2,
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PHY_TYPE_SFX7101 = 3,
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PHY_TYPE_QT2022C2 = 4,
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PHY_TYPE_PM8358 = 6,
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PHY_TYPE_SFT9001A = 8,
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PHY_TYPE_QT2025C = 9,
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PHY_TYPE_SFT9001B = 10,
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};
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2012-12-15 05:52:56 +08:00
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enum {
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2014-07-15 18:58:12 +08:00
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SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
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2012-12-15 05:52:56 +08:00
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SIENA_STAT_tx_good_bytes,
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SIENA_STAT_tx_bad_bytes,
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SIENA_STAT_tx_packets,
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SIENA_STAT_tx_bad,
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SIENA_STAT_tx_pause,
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SIENA_STAT_tx_control,
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SIENA_STAT_tx_unicast,
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SIENA_STAT_tx_multicast,
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SIENA_STAT_tx_broadcast,
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SIENA_STAT_tx_lt64,
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SIENA_STAT_tx_64,
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SIENA_STAT_tx_65_to_127,
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SIENA_STAT_tx_128_to_255,
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SIENA_STAT_tx_256_to_511,
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SIENA_STAT_tx_512_to_1023,
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SIENA_STAT_tx_1024_to_15xx,
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SIENA_STAT_tx_15xx_to_jumbo,
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SIENA_STAT_tx_gtjumbo,
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SIENA_STAT_tx_collision,
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SIENA_STAT_tx_single_collision,
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SIENA_STAT_tx_multiple_collision,
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SIENA_STAT_tx_excessive_collision,
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SIENA_STAT_tx_deferred,
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SIENA_STAT_tx_late_collision,
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SIENA_STAT_tx_excessive_deferred,
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SIENA_STAT_tx_non_tcpudp,
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SIENA_STAT_tx_mac_src_error,
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SIENA_STAT_tx_ip_src_error,
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SIENA_STAT_rx_bytes,
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SIENA_STAT_rx_good_bytes,
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SIENA_STAT_rx_bad_bytes,
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SIENA_STAT_rx_packets,
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SIENA_STAT_rx_good,
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SIENA_STAT_rx_bad,
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SIENA_STAT_rx_pause,
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SIENA_STAT_rx_control,
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SIENA_STAT_rx_unicast,
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SIENA_STAT_rx_multicast,
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SIENA_STAT_rx_broadcast,
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SIENA_STAT_rx_lt64,
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SIENA_STAT_rx_64,
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SIENA_STAT_rx_65_to_127,
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SIENA_STAT_rx_128_to_255,
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SIENA_STAT_rx_256_to_511,
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SIENA_STAT_rx_512_to_1023,
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SIENA_STAT_rx_1024_to_15xx,
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SIENA_STAT_rx_15xx_to_jumbo,
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SIENA_STAT_rx_gtjumbo,
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SIENA_STAT_rx_bad_gtjumbo,
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SIENA_STAT_rx_overflow,
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SIENA_STAT_rx_false_carrier,
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SIENA_STAT_rx_symbol_error,
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SIENA_STAT_rx_align_error,
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SIENA_STAT_rx_length_error,
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SIENA_STAT_rx_internal_error,
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SIENA_STAT_rx_nodesc_drop_cnt,
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SIENA_STAT_COUNT
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};
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2009-11-29 23:15:41 +08:00
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/**
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* struct siena_nic_data - Siena NIC state
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2014-11-05 20:16:18 +08:00
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* @efx: Pointer back to main interface structure
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2009-11-29 23:15:41 +08:00
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* @wol_filter_id: Wake-on-LAN packet filter id
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2012-12-15 05:52:56 +08:00
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* @stats: Hardware statistics
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2015-05-06 07:55:36 +08:00
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* @vf: Array of &struct siena_vf objects
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2014-11-05 20:16:18 +08:00
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* @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
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* @vfdi_status: Common VFDI status page to be dmad to VF address space.
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* @local_addr_list: List of local addresses. Protected by %local_lock.
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* @local_page_list: List of DMA addressable pages used to broadcast
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* %local_addr_list. Protected by %local_lock.
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* @local_lock: Mutex protecting %local_addr_list and %local_page_list.
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* @peer_work: Work item to broadcast peer addresses to VMs.
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2009-11-29 23:15:41 +08:00
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*/
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struct siena_nic_data {
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2014-11-05 20:16:18 +08:00
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struct efx_nic *efx;
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2009-11-29 23:15:41 +08:00
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int wol_filter_id;
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2012-12-15 05:52:56 +08:00
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u64 stats[SIENA_STAT_COUNT];
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2014-11-05 20:16:18 +08:00
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#ifdef CONFIG_SFC_SRIOV
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2015-05-06 07:55:36 +08:00
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struct siena_vf *vf;
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2014-11-05 20:16:18 +08:00
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struct efx_channel *vfdi_channel;
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unsigned vf_buftbl_base;
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struct efx_buffer vfdi_status;
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struct list_head local_addr_list;
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struct list_head local_page_list;
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struct mutex local_lock;
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struct work_struct peer_work;
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#endif
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2009-11-29 23:15:41 +08:00
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};
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2013-08-30 02:19:29 +08:00
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enum {
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2015-06-02 18:38:34 +08:00
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EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
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EF10_STAT_port_tx_packets,
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EF10_STAT_port_tx_pause,
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EF10_STAT_port_tx_control,
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EF10_STAT_port_tx_unicast,
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EF10_STAT_port_tx_multicast,
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EF10_STAT_port_tx_broadcast,
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EF10_STAT_port_tx_lt64,
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EF10_STAT_port_tx_64,
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EF10_STAT_port_tx_65_to_127,
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EF10_STAT_port_tx_128_to_255,
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EF10_STAT_port_tx_256_to_511,
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EF10_STAT_port_tx_512_to_1023,
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EF10_STAT_port_tx_1024_to_15xx,
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EF10_STAT_port_tx_15xx_to_jumbo,
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EF10_STAT_port_rx_bytes,
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EF10_STAT_port_rx_bytes_minus_good_bytes,
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EF10_STAT_port_rx_good_bytes,
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EF10_STAT_port_rx_bad_bytes,
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EF10_STAT_port_rx_packets,
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EF10_STAT_port_rx_good,
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EF10_STAT_port_rx_bad,
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EF10_STAT_port_rx_pause,
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EF10_STAT_port_rx_control,
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EF10_STAT_port_rx_unicast,
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EF10_STAT_port_rx_multicast,
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EF10_STAT_port_rx_broadcast,
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EF10_STAT_port_rx_lt64,
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EF10_STAT_port_rx_64,
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EF10_STAT_port_rx_65_to_127,
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EF10_STAT_port_rx_128_to_255,
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EF10_STAT_port_rx_256_to_511,
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EF10_STAT_port_rx_512_to_1023,
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EF10_STAT_port_rx_1024_to_15xx,
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EF10_STAT_port_rx_15xx_to_jumbo,
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EF10_STAT_port_rx_gtjumbo,
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EF10_STAT_port_rx_bad_gtjumbo,
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EF10_STAT_port_rx_overflow,
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EF10_STAT_port_rx_align_error,
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EF10_STAT_port_rx_length_error,
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EF10_STAT_port_rx_nodesc_drops,
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EF10_STAT_port_rx_pm_trunc_bb_overflow,
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EF10_STAT_port_rx_pm_discard_bb_overflow,
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EF10_STAT_port_rx_pm_trunc_vfifo_full,
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EF10_STAT_port_rx_pm_discard_vfifo_full,
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EF10_STAT_port_rx_pm_trunc_qbb,
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EF10_STAT_port_rx_pm_discard_qbb,
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EF10_STAT_port_rx_pm_discard_mapping,
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EF10_STAT_port_rx_dp_q_disabled_packets,
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EF10_STAT_port_rx_dp_di_dropped_packets,
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EF10_STAT_port_rx_dp_streaming_packets,
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EF10_STAT_port_rx_dp_hlb_fetch,
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EF10_STAT_port_rx_dp_hlb_wait,
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2015-06-02 18:39:06 +08:00
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EF10_STAT_rx_unicast,
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EF10_STAT_rx_unicast_bytes,
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EF10_STAT_rx_multicast,
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EF10_STAT_rx_multicast_bytes,
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EF10_STAT_rx_broadcast,
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EF10_STAT_rx_broadcast_bytes,
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EF10_STAT_rx_bad,
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EF10_STAT_rx_bad_bytes,
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EF10_STAT_rx_overflow,
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EF10_STAT_tx_unicast,
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EF10_STAT_tx_unicast_bytes,
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EF10_STAT_tx_multicast,
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EF10_STAT_tx_multicast_bytes,
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EF10_STAT_tx_broadcast,
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EF10_STAT_tx_broadcast_bytes,
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EF10_STAT_tx_bad,
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EF10_STAT_tx_bad_bytes,
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EF10_STAT_tx_overflow,
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2017-12-21 17:00:36 +08:00
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EF10_STAT_V1_COUNT,
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EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
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EF10_STAT_fec_corrected_errors,
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EF10_STAT_fec_corrected_symbols_lane0,
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EF10_STAT_fec_corrected_symbols_lane1,
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EF10_STAT_fec_corrected_symbols_lane2,
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EF10_STAT_fec_corrected_symbols_lane3,
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2017-12-21 17:00:41 +08:00
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EF10_STAT_ctpio_vi_busy_fallback,
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EF10_STAT_ctpio_long_write_success,
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EF10_STAT_ctpio_missing_dbell_fail,
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EF10_STAT_ctpio_overflow_fail,
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EF10_STAT_ctpio_underflow_fail,
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EF10_STAT_ctpio_timeout_fail,
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EF10_STAT_ctpio_noncontig_wr_fail,
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EF10_STAT_ctpio_frm_clobber_fail,
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EF10_STAT_ctpio_invalid_wr_fail,
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EF10_STAT_ctpio_vi_clobber_fallback,
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EF10_STAT_ctpio_unqualified_fallback,
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EF10_STAT_ctpio_runt_fallback,
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EF10_STAT_ctpio_success,
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EF10_STAT_ctpio_fallback,
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EF10_STAT_ctpio_poison,
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EF10_STAT_ctpio_erase,
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2013-08-30 02:19:29 +08:00
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EF10_STAT_COUNT
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};
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2013-06-29 04:47:12 +08:00
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/* Maximum number of TX PIO buffers we may allocate to a function.
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* This matches the total number of buffers on each SFC9100-family
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* controller.
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*/
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#define EF10_TX_PIOBUF_COUNT 16
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2013-08-30 02:19:29 +08:00
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/**
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* struct efx_ef10_nic_data - EF10 architecture NIC state
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* @mcdi_buf: DMA buffer for MCDI
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* @warm_boot_count: Last seen MC warm boot count
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* @vi_base: Absolute index of first VI in this function
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* @n_allocated_vis: Number of VIs allocated to this function
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2013-06-29 04:47:12 +08:00
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* @n_piobufs: Number of PIO buffers allocated to this function
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* @wc_membase: Base address of write-combining mapping of the memory BAR
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* @pio_write_base: Base address for writing PIO buffers
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* @pio_write_vi_base: Relative VI number for @pio_write_base
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* @piobuf_handle: Handle of each PIO buffer allocated
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2017-01-14 05:20:29 +08:00
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* @piobuf_size: size of a single PIO buffer
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2013-06-29 04:47:12 +08:00
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* @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
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* reboot
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2020-06-29 21:34:20 +08:00
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* @mc_stats: Scratch buffer for converting statistics to the kernel's format
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2013-08-30 02:19:29 +08:00
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* @stats: Hardware statistics
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* @workaround_35388: Flag: firmware supports workaround for bug 35388
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2015-07-21 22:09:18 +08:00
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* @workaround_26807: Flag: firmware supports workaround for bug 26807
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2016-08-11 20:02:09 +08:00
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* @workaround_61265: Flag: firmware supports workaround for bug 61265
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2013-09-06 05:51:55 +08:00
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* @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
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* after MC reboot
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2013-08-30 02:19:29 +08:00
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* @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
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* %MC_CMD_GET_CAPABILITIES response)
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2016-08-11 20:01:35 +08:00
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* @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
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* %MC_CMD_GET_CAPABILITIES response)
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2015-05-06 07:56:55 +08:00
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* @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
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* @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
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2015-05-06 07:57:34 +08:00
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* @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
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2015-05-06 07:57:53 +08:00
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* @pf_index: The number for this PF, or the parent PF if this is a VF
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2015-05-06 07:58:31 +08:00
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#ifdef CONFIG_SFC_SRIOV
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* @vf: Pointer to VF data structure
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#endif
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2016-06-16 00:48:14 +08:00
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* @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
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* @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
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* @vlan_lock: Lock to serialize access to vlan_list.
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2017-02-09 00:52:10 +08:00
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* @udp_tunnels: UDP tunnel port numbers and types.
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* @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
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* @udp_tunnels to hardware and thus the push must be re-done.
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* @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
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2013-08-30 02:19:29 +08:00
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*/
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struct efx_ef10_nic_data {
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struct efx_buffer mcdi_buf;
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u16 warm_boot_count;
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unsigned int vi_base;
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unsigned int n_allocated_vis;
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2013-06-29 04:47:12 +08:00
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unsigned int n_piobufs;
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void __iomem *wc_membase, *pio_write_base;
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unsigned int pio_write_vi_base;
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unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
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2017-01-14 05:20:29 +08:00
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u16 piobuf_size;
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2013-06-29 04:47:12 +08:00
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bool must_restore_piobufs;
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2020-06-29 21:34:20 +08:00
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__le64 *mc_stats;
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2013-08-30 02:19:29 +08:00
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u64 stats[EF10_STAT_COUNT];
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bool workaround_35388;
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2015-07-21 22:09:18 +08:00
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|
bool workaround_26807;
|
2016-08-11 20:02:09 +08:00
|
|
|
bool workaround_61265;
|
2013-09-06 05:51:55 +08:00
|
|
|
bool must_check_datapath_caps;
|
2013-08-30 02:19:29 +08:00
|
|
|
u32 datapath_caps;
|
2016-08-11 20:01:35 +08:00
|
|
|
u32 datapath_caps2;
|
2015-05-06 07:56:55 +08:00
|
|
|
unsigned int rx_dpcpu_fw_id;
|
|
|
|
unsigned int tx_dpcpu_fw_id;
|
2015-05-06 07:57:34 +08:00
|
|
|
bool must_probe_vswitching;
|
2015-05-06 07:57:53 +08:00
|
|
|
unsigned int pf_index;
|
2015-06-02 18:38:16 +08:00
|
|
|
u8 port_id[ETH_ALEN];
|
2015-05-06 07:58:31 +08:00
|
|
|
#ifdef CONFIG_SFC_SRIOV
|
2015-05-20 18:09:15 +08:00
|
|
|
unsigned int vf_index;
|
2015-05-06 07:58:31 +08:00
|
|
|
struct ef10_vf *vf;
|
|
|
|
#endif
|
|
|
|
u8 vport_mac[ETH_ALEN];
|
2016-06-16 00:48:14 +08:00
|
|
|
struct list_head vlan_list;
|
|
|
|
struct mutex vlan_lock;
|
2017-02-09 00:52:10 +08:00
|
|
|
struct efx_udp_tunnel udp_tunnels[16];
|
|
|
|
bool udp_tunnels_dirty;
|
|
|
|
struct mutex udp_tunnels_lock;
|
2018-01-26 01:25:33 +08:00
|
|
|
u64 licensed_features;
|
2013-08-30 02:19:29 +08:00
|
|
|
};
|
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_init_sriov(void);
|
|
|
|
void efx_fini_sriov(void);
|
sfc: Add SR-IOV back-end support for SFC9000 family
On the SFC9000 family, each port has 1024 Virtual Interfaces (VIs),
each with an RX queue, a TX queue, an event queue and a mailbox
register. These may be assigned to up to 127 SR-IOV virtual functions
per port, with up to 64 VIs per VF.
We allocate an extra channel (IRQ and event queue only) to receive
requests from VF drivers.
There is a per-port limit of 4 concurrent RX queue flushes, and queue
flushes may be initiated by the MC in response to a Function Level
Reset (FLR) of a VF. Therefore, when SR-IOV is in use, we submit all
flush requests via the MC.
The RSS indirection table is shared with VFs, so the number of RX
queues used in the PF is limited to the number of VIs per VF.
This is almost entirely the work of Steve Hodgson, formerly
shodgson@solarflare.com.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
2012-02-14 08:48:07 +08:00
|
|
|
|
2011-04-14 13:50:12 +08:00
|
|
|
extern const struct efx_nic_type siena_a0_nic_type;
|
2013-08-30 02:19:29 +08:00
|
|
|
extern const struct efx_nic_type efx_hunt_a0_nic_type;
|
2015-05-06 07:58:14 +08:00
|
|
|
extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
|
2009-10-23 16:29:51 +08:00
|
|
|
|
2013-08-22 02:51:04 +08:00
|
|
|
/* Falcon/Siena queue operations */
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
|
|
|
|
void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
|
|
|
|
void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
|
|
|
|
void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
|
|
|
|
void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
|
2016-11-17 18:51:54 +08:00
|
|
|
unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
|
|
|
|
dma_addr_t dma_addr, unsigned int len);
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
|
|
|
|
void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
|
|
|
|
void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
|
|
|
|
void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
|
|
|
|
void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
|
|
|
|
void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
|
|
|
|
int efx_farch_ev_probe(struct efx_channel *channel);
|
|
|
|
int efx_farch_ev_init(struct efx_channel *channel);
|
|
|
|
void efx_farch_ev_fini(struct efx_channel *channel);
|
|
|
|
void efx_farch_ev_remove(struct efx_channel *channel);
|
|
|
|
int efx_farch_ev_process(struct efx_channel *channel, int quota);
|
|
|
|
void efx_farch_ev_read_ack(struct efx_channel *channel);
|
|
|
|
void efx_farch_ev_test_generate(struct efx_channel *channel);
|
2013-08-22 02:51:04 +08:00
|
|
|
|
2012-11-08 09:46:53 +08:00
|
|
|
/* Falcon/Siena filter operations */
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_filter_table_probe(struct efx_nic *efx);
|
|
|
|
void efx_farch_filter_table_restore(struct efx_nic *efx);
|
|
|
|
void efx_farch_filter_table_remove(struct efx_nic *efx);
|
|
|
|
void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
|
|
|
|
s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
|
|
|
|
bool replace);
|
|
|
|
int efx_farch_filter_remove_safe(struct efx_nic *efx,
|
|
|
|
enum efx_filter_priority priority,
|
|
|
|
u32 filter_id);
|
|
|
|
int efx_farch_filter_get_safe(struct efx_nic *efx,
|
|
|
|
enum efx_filter_priority priority, u32 filter_id,
|
|
|
|
struct efx_filter_spec *);
|
2013-11-22 03:15:03 +08:00
|
|
|
int efx_farch_filter_clear_rx(struct efx_nic *efx,
|
|
|
|
enum efx_filter_priority priority);
|
2013-09-24 02:37:59 +08:00
|
|
|
u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
|
|
|
|
enum efx_filter_priority priority);
|
|
|
|
u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
|
|
|
|
s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
|
|
|
|
enum efx_filter_priority priority, u32 *buf,
|
|
|
|
u32 size);
|
2012-11-08 09:46:53 +08:00
|
|
|
#ifdef CONFIG_RFS_ACCEL
|
2013-09-24 02:37:59 +08:00
|
|
|
bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
|
|
|
|
unsigned int index);
|
2012-11-08 09:46:53 +08:00
|
|
|
#endif
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
|
2012-11-08 09:46:53 +08:00
|
|
|
|
2013-08-22 02:51:04 +08:00
|
|
|
/* Falcon/Siena interrupts */
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_irq_enable_master(struct efx_nic *efx);
|
2016-08-26 22:13:30 +08:00
|
|
|
int efx_farch_irq_test_generate(struct efx_nic *efx);
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_irq_disable_master(struct efx_nic *efx);
|
|
|
|
irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
|
|
|
|
irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
|
|
|
|
irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
|
2009-11-29 11:43:56 +08:00
|
|
|
|
2008-04-27 19:55:59 +08:00
|
|
|
/* Global Resources */
|
2013-09-24 02:37:59 +08:00
|
|
|
void siena_prepare_flush(struct efx_nic *efx);
|
|
|
|
int efx_farch_fini_dmaq(struct efx_nic *efx);
|
sfc:On MCDI timeout, issue an FLR (and mark MCDI to fail-fast)
When an MCDI command times out (whether or not we find it
completed when we poll), call efx_mcdi_abandon(), which tells
all subsequent MCDI calls to fail-fast, and queues up an FLR.
Because an FLR doesn't lead to receiving any reboot even from
the MC (unlike most other types of reset), we have to call
efx_ef10_reset_mc_allocations.
In efx_start_all(), if a reset (of any kind) is pending, we
bail out.
Without this, attempts to reconfigure (e.g. change mtu) can
cause driver/mc state inconsistency if the first MCDI call
triggers an FLR.
For similar reasons, on EF10, in
efx_reset_down(method=RESET_TYPE_MCDI_TIMEOUT), set the number
of active queues to zero before calling efx_stop_all().
And, on farch, in efx_reset_up(method=RESET_TYPE_MCDI_TIMEOUT),
set active_queues and flushes pending & outstanding to zero.
efx_mcdi_mode_{poll,event}() should not take us out of fail-fast
mode. Instead, this is done by efx_mcdi_reset() after the FLR
completes.
The new FLR reset_type RESET_TYPE_MCDI_TIMEOUT doesn't really
fit into the hierarchy of reset 'scopes' whereby efx_reset()
decides some resets subsume others. Thus, it uses separate logic.
Also, fixed up some inconsistency around RESET_TYPE_MC_BIST,
which was in the wrong place in that hierarchy.
Signed-off-by: Shradha Shah <sshah@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-04-17 02:27:48 +08:00
|
|
|
void efx_farch_finish_flr(struct efx_nic *efx);
|
2013-09-24 02:37:59 +08:00
|
|
|
void siena_finish_flush(struct efx_nic *efx);
|
|
|
|
void falcon_start_nic_stats(struct efx_nic *efx);
|
|
|
|
void falcon_stop_nic_stats(struct efx_nic *efx);
|
|
|
|
int falcon_reset_xaui(struct efx_nic *efx);
|
|
|
|
void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
|
|
|
|
void efx_farch_init_common(struct efx_nic *efx);
|
|
|
|
void efx_farch_rx_push_indir_table(struct efx_nic *efx);
|
2017-01-17 20:02:12 +08:00
|
|
|
void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
|
2009-11-29 11:43:56 +08:00
|
|
|
|
2008-09-01 19:49:02 +08:00
|
|
|
/* Tests */
|
2013-08-22 02:51:04 +08:00
|
|
|
struct efx_farch_register_test {
|
2009-11-29 11:43:56 +08:00
|
|
|
unsigned address;
|
|
|
|
efx_oword_t mask;
|
|
|
|
};
|
2020-01-09 00:10:32 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_test_registers(struct efx_nic *efx,
|
|
|
|
const struct efx_farch_register_test *regs,
|
|
|
|
size_t n_regs);
|
2008-09-01 19:49:02 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
|
|
|
|
efx_qword_t *event);
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2009-11-29 23:12:08 +08:00
|
|
|
#endif /* EFX_NIC_H */
|