2015-04-21 04:55:21 +08:00
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/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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2016-01-30 13:59:34 +08:00
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#include <drm/drm_cache.h>
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2015-04-21 04:55:21 +08:00
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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int amdgpu_ttm_init(struct amdgpu_device *adev);
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void amdgpu_ttm_fini(struct amdgpu_device *adev);
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static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
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2015-04-24 17:37:30 +08:00
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struct ttm_mem_reg *mem)
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2015-04-21 04:55:21 +08:00
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{
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u64 ret = 0;
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if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
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ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
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adev->mc.visible_vram_size ?
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2015-04-24 17:37:30 +08:00
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adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
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2015-04-21 04:55:21 +08:00
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mem->size;
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}
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return ret;
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}
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static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
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struct ttm_mem_reg *old_mem,
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struct ttm_mem_reg *new_mem)
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{
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u64 vis_size;
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if (!adev)
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return;
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if (new_mem) {
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switch (new_mem->mem_type) {
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case TTM_PL_TT:
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atomic64_add(new_mem->size, &adev->gtt_usage);
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break;
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case TTM_PL_VRAM:
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atomic64_add(new_mem->size, &adev->vram_usage);
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vis_size = amdgpu_get_vis_part_size(adev, new_mem);
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atomic64_add(vis_size, &adev->vram_vis_usage);
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break;
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}
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}
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if (old_mem) {
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switch (old_mem->mem_type) {
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case TTM_PL_TT:
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atomic64_sub(old_mem->size, &adev->gtt_usage);
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break;
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case TTM_PL_VRAM:
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atomic64_sub(old_mem->size, &adev->vram_usage);
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vis_size = amdgpu_get_vis_part_size(adev, old_mem);
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atomic64_sub(vis_size, &adev->vram_vis_usage);
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break;
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}
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}
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}
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static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
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{
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struct amdgpu_bo *bo;
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bo = container_of(tbo, struct amdgpu_bo, tbo);
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amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
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drm_gem_object_release(&bo->gem_base);
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2015-11-27 23:49:00 +08:00
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amdgpu_bo_unref(&bo->parent);
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2015-04-21 04:55:21 +08:00
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kfree(bo->metadata);
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kfree(bo);
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}
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bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
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{
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if (bo->destroy == &amdgpu_ttm_bo_destroy)
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return true;
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return false;
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}
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2015-04-24 17:37:30 +08:00
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static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
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struct ttm_placement *placement,
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struct ttm_place *placements,
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u32 domain, u64 flags)
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2015-04-21 04:55:21 +08:00
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{
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u32 c = 0, i;
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2015-04-24 17:37:30 +08:00
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placement->placement = placements;
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placement->busy_placement = placements;
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2015-04-21 04:55:21 +08:00
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if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
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2015-04-24 17:37:30 +08:00
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if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
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adev->mc.visible_vram_size < adev->mc.real_vram_size) {
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placements[c].fpfn =
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adev->mc.visible_vram_size >> PAGE_SHIFT;
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placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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2015-09-03 03:06:08 +08:00
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TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN;
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2015-04-21 04:55:21 +08:00
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}
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2015-04-24 17:37:30 +08:00
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_VRAM;
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2015-09-23 17:22:43 +08:00
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if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
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placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;
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2015-04-21 04:55:21 +08:00
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}
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if (domain & AMDGPU_GEM_DOMAIN_GTT) {
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2015-04-24 17:37:30 +08:00
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if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
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TTM_PL_FLAG_UNCACHED;
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2015-04-21 04:55:21 +08:00
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} else {
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2015-04-24 17:37:30 +08:00
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
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2015-04-21 04:55:21 +08:00
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}
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}
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if (domain & AMDGPU_GEM_DOMAIN_CPU) {
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2015-04-24 17:37:30 +08:00
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if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
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TTM_PL_FLAG_UNCACHED;
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2015-04-21 04:55:21 +08:00
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} else {
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2015-04-24 17:37:30 +08:00
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
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2015-04-21 04:55:21 +08:00
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}
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}
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if (domain & AMDGPU_GEM_DOMAIN_GDS) {
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2015-04-24 17:37:30 +08:00
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_UNCACHED |
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AMDGPU_PL_FLAG_GDS;
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2015-04-21 04:55:21 +08:00
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}
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if (domain & AMDGPU_GEM_DOMAIN_GWS) {
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2015-04-24 17:37:30 +08:00
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_UNCACHED |
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AMDGPU_PL_FLAG_GWS;
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2015-04-21 04:55:21 +08:00
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}
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if (domain & AMDGPU_GEM_DOMAIN_OA) {
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2015-04-24 17:37:30 +08:00
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_FLAG_UNCACHED |
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AMDGPU_PL_FLAG_OA;
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2015-04-21 04:55:21 +08:00
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}
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if (!c) {
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2015-04-24 17:37:30 +08:00
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placements[c].fpfn = 0;
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placements[c++].flags = TTM_PL_MASK_CACHING |
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TTM_PL_FLAG_SYSTEM;
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2015-04-21 04:55:21 +08:00
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}
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2015-04-24 17:37:30 +08:00
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placement->num_placement = c;
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placement->num_busy_placement = c;
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2015-04-21 04:55:21 +08:00
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for (i = 0; i < c; i++) {
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2015-04-24 17:37:30 +08:00
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if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
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(placements[i].flags & TTM_PL_FLAG_VRAM) &&
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!placements[i].fpfn)
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placements[i].lpfn =
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adev->mc.visible_vram_size >> PAGE_SHIFT;
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2015-04-21 04:55:21 +08:00
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else
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2015-04-24 17:37:30 +08:00
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placements[i].lpfn = 0;
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2015-04-21 04:55:21 +08:00
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}
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}
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2015-04-24 17:37:30 +08:00
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void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
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{
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amdgpu_ttm_placement_init(rbo->adev, &rbo->placement,
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rbo->placements, domain, rbo->flags);
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}
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static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
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struct ttm_placement *placement)
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{
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BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
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memcpy(bo->placements, placement->placement,
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placement->num_placement * sizeof(struct ttm_place));
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bo->placement.num_placement = placement->num_placement;
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bo->placement.num_busy_placement = placement->num_busy_placement;
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bo->placement.placement = bo->placements;
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bo->placement.busy_placement = bo->placements;
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}
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int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
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unsigned long size, int byte_align,
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bool kernel, u32 domain, u64 flags,
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struct sg_table *sg,
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struct ttm_placement *placement,
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2015-09-03 23:34:59 +08:00
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struct reservation_object *resv,
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2015-04-24 17:37:30 +08:00
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struct amdgpu_bo **bo_ptr)
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2015-04-21 04:55:21 +08:00
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{
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struct amdgpu_bo *bo;
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enum ttm_bo_type type;
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unsigned long page_align;
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size_t acc_size;
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int r;
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page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
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size = ALIGN(size, PAGE_SIZE);
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else if (sg) {
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type = ttm_bo_type_sg;
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} else {
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type = ttm_bo_type_device;
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}
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*bo_ptr = NULL;
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acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
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sizeof(struct amdgpu_bo));
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bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
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if (bo == NULL)
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return -ENOMEM;
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r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
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if (unlikely(r)) {
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kfree(bo);
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return r;
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}
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bo->adev = adev;
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INIT_LIST_HEAD(&bo->list);
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INIT_LIST_HEAD(&bo->va);
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2015-12-19 05:13:12 +08:00
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bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT |
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AMDGPU_GEM_DOMAIN_CPU |
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AMDGPU_GEM_DOMAIN_GDS |
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AMDGPU_GEM_DOMAIN_GWS |
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AMDGPU_GEM_DOMAIN_OA);
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bo->allowed_domains = bo->prefered_domains;
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if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
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bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
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2015-04-21 04:55:21 +08:00
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bo->flags = flags;
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2016-01-30 13:59:34 +08:00
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/* For architectures that don't support WC memory,
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* mask out the WC flag from the BO
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*/
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if (!drm_arch_can_wc_memory())
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bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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2015-04-24 17:37:30 +08:00
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amdgpu_fill_placement_to_bo(bo, placement);
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2015-04-21 04:55:21 +08:00
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/* Kernel allocation are uninterruptible */
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r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
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&bo->placement, page_align, !kernel, NULL,
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2015-09-03 23:34:59 +08:00
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acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
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2015-04-21 04:55:21 +08:00
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if (unlikely(r != 0)) {
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return r;
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}
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*bo_ptr = bo;
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trace_amdgpu_bo_create(bo);
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return 0;
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}
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2015-04-24 17:37:30 +08:00
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int amdgpu_bo_create(struct amdgpu_device *adev,
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unsigned long size, int byte_align,
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bool kernel, u32 domain, u64 flags,
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2015-09-03 23:34:59 +08:00
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struct sg_table *sg,
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struct reservation_object *resv,
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struct amdgpu_bo **bo_ptr)
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2015-04-24 17:37:30 +08:00
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{
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struct ttm_placement placement = {0};
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struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
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memset(&placements, 0,
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(AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
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amdgpu_ttm_placement_init(adev, &placement,
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placements, domain, flags);
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2015-09-03 23:34:59 +08:00
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return amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
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domain, flags, sg, &placement,
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resv, bo_ptr);
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2015-04-24 17:37:30 +08:00
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}
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2015-04-21 04:55:21 +08:00
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int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
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{
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bool is_iomem;
|
2016-03-10 23:21:04 +08:00
|
|
|
long r;
|
2015-04-21 04:55:21 +08:00
|
|
|
|
2015-05-13 20:30:53 +08:00
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
|
|
|
|
return -EPERM;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
if (bo->kptr) {
|
|
|
|
if (ptr) {
|
|
|
|
*ptr = bo->kptr;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2016-03-10 23:21:04 +08:00
|
|
|
|
|
|
|
r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
|
|
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (r < 0)
|
|
|
|
return r;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
|
2016-03-10 23:21:04 +08:00
|
|
|
if (r)
|
2015-04-21 04:55:21 +08:00
|
|
|
return r;
|
2016-03-10 23:21:04 +08:00
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
|
2016-03-10 23:21:04 +08:00
|
|
|
if (ptr)
|
2015-04-21 04:55:21 +08:00
|
|
|
*ptr = bo->kptr;
|
2016-03-10 23:21:04 +08:00
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
|
|
|
|
{
|
|
|
|
if (bo->kptr == NULL)
|
|
|
|
return;
|
|
|
|
bo->kptr = NULL;
|
|
|
|
ttm_bo_kunmap(&bo->kmap);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
|
|
|
|
{
|
|
|
|
if (bo == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
ttm_bo_reference(&bo->tbo);
|
|
|
|
return bo;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_unref(struct amdgpu_bo **bo)
|
|
|
|
{
|
|
|
|
struct ttm_buffer_object *tbo;
|
|
|
|
|
|
|
|
if ((*bo) == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
tbo = &((*bo)->tbo);
|
|
|
|
ttm_bo_unref(&tbo);
|
|
|
|
if (tbo == NULL)
|
|
|
|
*bo = NULL;
|
|
|
|
}
|
|
|
|
|
2015-04-24 17:37:30 +08:00
|
|
|
int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
|
|
|
|
u64 min_offset, u64 max_offset,
|
2015-04-21 04:55:21 +08:00
|
|
|
u64 *gpu_addr)
|
|
|
|
{
|
|
|
|
int r, i;
|
2015-04-24 17:37:30 +08:00
|
|
|
unsigned fpfn, lpfn;
|
2015-04-21 04:55:21 +08:00
|
|
|
|
2016-02-08 18:08:35 +08:00
|
|
|
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
|
2015-04-21 04:55:21 +08:00
|
|
|
return -EPERM;
|
|
|
|
|
2015-04-24 17:37:30 +08:00
|
|
|
if (WARN_ON_ONCE(min_offset > max_offset))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
if (bo->pin_count) {
|
|
|
|
bo->pin_count++;
|
|
|
|
if (gpu_addr)
|
|
|
|
*gpu_addr = amdgpu_bo_gpu_offset(bo);
|
|
|
|
|
|
|
|
if (max_offset != 0) {
|
|
|
|
u64 domain_start;
|
|
|
|
if (domain == AMDGPU_GEM_DOMAIN_VRAM)
|
|
|
|
domain_start = bo->adev->mc.vram_start;
|
|
|
|
else
|
|
|
|
domain_start = bo->adev->mc.gtt_start;
|
|
|
|
WARN_ON_ONCE(max_offset <
|
|
|
|
(amdgpu_bo_gpu_offset(bo) - domain_start));
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
amdgpu_ttm_placement_from_domain(bo, domain);
|
|
|
|
for (i = 0; i < bo->placement.num_placement; i++) {
|
|
|
|
/* force to pin into visible video ram */
|
|
|
|
if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
|
2015-04-24 17:37:30 +08:00
|
|
|
!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
|
|
|
|
(!max_offset || max_offset > bo->adev->mc.visible_vram_size)) {
|
|
|
|
if (WARN_ON_ONCE(min_offset >
|
|
|
|
bo->adev->mc.visible_vram_size))
|
|
|
|
return -EINVAL;
|
|
|
|
fpfn = min_offset >> PAGE_SHIFT;
|
|
|
|
lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
|
|
|
|
} else {
|
|
|
|
fpfn = min_offset >> PAGE_SHIFT;
|
|
|
|
lpfn = max_offset >> PAGE_SHIFT;
|
|
|
|
}
|
|
|
|
if (fpfn > bo->placements[i].fpfn)
|
|
|
|
bo->placements[i].fpfn = fpfn;
|
2016-01-19 19:48:14 +08:00
|
|
|
if (!bo->placements[i].lpfn ||
|
|
|
|
(lpfn && lpfn < bo->placements[i].lpfn))
|
2015-04-24 17:37:30 +08:00
|
|
|
bo->placements[i].lpfn = lpfn;
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
|
|
|
|
if (likely(r == 0)) {
|
|
|
|
bo->pin_count = 1;
|
|
|
|
if (gpu_addr != NULL)
|
|
|
|
*gpu_addr = amdgpu_bo_gpu_offset(bo);
|
2016-04-05 10:48:48 +08:00
|
|
|
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->adev->vram_pin_size += amdgpu_bo_size(bo);
|
2016-04-05 10:48:48 +08:00
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
|
|
|
|
bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
|
|
|
|
} else
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->adev->gart_pin_size += amdgpu_bo_size(bo);
|
|
|
|
} else {
|
|
|
|
dev_err(bo->adev->dev, "%p pin failed\n", bo);
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
|
|
|
|
{
|
2015-04-24 17:37:30 +08:00
|
|
|
return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_unpin(struct amdgpu_bo *bo)
|
|
|
|
{
|
|
|
|
int r, i;
|
|
|
|
|
|
|
|
if (!bo->pin_count) {
|
|
|
|
dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
bo->pin_count--;
|
|
|
|
if (bo->pin_count)
|
|
|
|
return 0;
|
|
|
|
for (i = 0; i < bo->placement.num_placement; i++) {
|
|
|
|
bo->placements[i].lpfn = 0;
|
|
|
|
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
|
|
|
|
}
|
|
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
|
|
|
|
if (likely(r == 0)) {
|
2016-04-05 10:48:48 +08:00
|
|
|
if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
|
2016-04-05 10:48:48 +08:00
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
|
|
|
|
bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
|
|
|
|
} else
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
|
|
|
|
} else {
|
|
|
|
dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
|
2015-07-22 11:29:01 +08:00
|
|
|
if (0 && (adev->flags & AMD_IS_APU)) {
|
2015-04-21 04:55:21 +08:00
|
|
|
/* Useless to evict on IGP chips */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
|
|
|
|
}
|
|
|
|
|
2016-04-01 04:56:22 +08:00
|
|
|
static const char *amdgpu_vram_names[] = {
|
|
|
|
"UNKNOWN",
|
|
|
|
"GDDR1",
|
|
|
|
"DDR2",
|
|
|
|
"GDDR3",
|
|
|
|
"GDDR4",
|
|
|
|
"GDDR5",
|
|
|
|
"HBM",
|
|
|
|
"DDR3"
|
|
|
|
};
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
int amdgpu_bo_init(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
/* Add an MTRR for the VRAM */
|
|
|
|
adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
|
|
|
|
adev->mc.aper_size);
|
|
|
|
DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
|
|
|
|
adev->mc.mc_vram_size >> 20,
|
|
|
|
(unsigned long long)adev->mc.aper_size >> 20);
|
2016-04-01 04:56:22 +08:00
|
|
|
DRM_INFO("RAM width %dbits %s\n",
|
|
|
|
adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
|
2015-04-21 04:55:21 +08:00
|
|
|
return amdgpu_ttm_init(adev);
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_fini(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
amdgpu_ttm_fini(adev);
|
|
|
|
arch_phys_wc_del(adev->mc.vram_mtrr);
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
|
|
|
|
struct vm_area_struct *vma)
|
|
|
|
{
|
|
|
|
return ttm_fbdev_mmap(vma, &bo->tbo);
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
|
|
|
|
{
|
2015-05-15 05:48:26 +08:00
|
|
|
if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
|
2015-04-21 04:55:21 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
bo->tiling_flags = tiling_flags;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
|
|
|
|
{
|
|
|
|
lockdep_assert_held(&bo->tbo.resv->lock.base);
|
|
|
|
|
|
|
|
if (tiling_flags)
|
|
|
|
*tiling_flags = bo->tiling_flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
|
|
|
|
uint32_t metadata_size, uint64_t flags)
|
|
|
|
{
|
|
|
|
void *buffer;
|
|
|
|
|
|
|
|
if (!metadata_size) {
|
|
|
|
if (bo->metadata_size) {
|
|
|
|
kfree(bo->metadata);
|
2016-05-03 10:44:29 +08:00
|
|
|
bo->metadata = NULL;
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->metadata_size = 0;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (metadata == NULL)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-09-22 05:34:39 +08:00
|
|
|
buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
|
2015-04-21 04:55:21 +08:00
|
|
|
if (buffer == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
kfree(bo->metadata);
|
|
|
|
bo->metadata_flags = flags;
|
|
|
|
bo->metadata = buffer;
|
|
|
|
bo->metadata_size = metadata_size;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
|
|
|
|
size_t buffer_size, uint32_t *metadata_size,
|
|
|
|
uint64_t *flags)
|
|
|
|
{
|
|
|
|
if (!buffer && !metadata_size)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (buffer) {
|
|
|
|
if (buffer_size < bo->metadata_size)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (bo->metadata_size)
|
|
|
|
memcpy(buffer, bo->metadata, bo->metadata_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (metadata_size)
|
|
|
|
*metadata_size = bo->metadata_size;
|
|
|
|
if (flags)
|
|
|
|
*flags = bo->metadata_flags;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
|
|
|
|
struct ttm_mem_reg *new_mem)
|
|
|
|
{
|
|
|
|
struct amdgpu_bo *rbo;
|
|
|
|
|
|
|
|
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
|
|
|
|
return;
|
|
|
|
|
|
|
|
rbo = container_of(bo, struct amdgpu_bo, tbo);
|
|
|
|
amdgpu_vm_bo_invalidate(rbo->adev, rbo);
|
|
|
|
|
|
|
|
/* update statistics */
|
|
|
|
if (!new_mem)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* move_notify is called before move happens */
|
|
|
|
amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
|
|
{
|
|
|
|
struct amdgpu_device *adev;
|
2015-05-21 23:03:46 +08:00
|
|
|
struct amdgpu_bo *abo;
|
|
|
|
unsigned long offset, size, lpfn;
|
|
|
|
int i, r;
|
2015-04-21 04:55:21 +08:00
|
|
|
|
|
|
|
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
|
|
|
|
return 0;
|
2015-05-21 23:03:46 +08:00
|
|
|
|
|
|
|
abo = container_of(bo, struct amdgpu_bo, tbo);
|
|
|
|
adev = abo->adev;
|
|
|
|
if (bo->mem.mem_type != TTM_PL_VRAM)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
size = bo->mem.num_pages << PAGE_SHIFT;
|
|
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
|
|
|
if ((offset + size) <= adev->mc.visible_vram_size)
|
|
|
|
return 0;
|
|
|
|
|
2016-03-28 11:53:02 +08:00
|
|
|
/* Can't move a pinned BO to visible VRAM */
|
|
|
|
if (abo->pin_count > 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-05-21 23:03:46 +08:00
|
|
|
/* hurrah the memory is not visible ! */
|
|
|
|
amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
|
|
|
|
lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
|
|
|
|
for (i = 0; i < abo->placement.num_placement; i++) {
|
|
|
|
/* Force into visible VRAM */
|
|
|
|
if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
|
|
|
|
(!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn))
|
|
|
|
abo->placements[i].lpfn = lpfn;
|
|
|
|
}
|
|
|
|
r = ttm_bo_validate(bo, &abo->placement, false, false);
|
|
|
|
if (unlikely(r == -ENOMEM)) {
|
|
|
|
amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
|
|
|
|
return ttm_bo_validate(bo, &abo->placement, false, false);
|
|
|
|
} else if (unlikely(r != 0)) {
|
|
|
|
return r;
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
2015-05-21 23:03:46 +08:00
|
|
|
|
|
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
|
|
|
/* this should never happen */
|
|
|
|
if ((offset + size) > adev->mc.visible_vram_size)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_bo_fence - add fence to buffer object
|
|
|
|
*
|
|
|
|
* @bo: buffer object in question
|
|
|
|
* @fence: fence to add
|
|
|
|
* @shared: true if fence should be added shared
|
|
|
|
*
|
|
|
|
*/
|
2015-08-03 11:38:09 +08:00
|
|
|
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
|
2015-04-21 04:55:21 +08:00
|
|
|
bool shared)
|
|
|
|
{
|
|
|
|
struct reservation_object *resv = bo->tbo.resv;
|
|
|
|
|
|
|
|
if (shared)
|
2015-08-03 11:38:09 +08:00
|
|
|
reservation_object_add_shared_fence(resv, fence);
|
2015-04-21 04:55:21 +08:00
|
|
|
else
|
2015-08-03 11:38:09 +08:00
|
|
|
reservation_object_add_excl_fence(resv, fence);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|