63 lines
2.0 KiB
C
63 lines
2.0 KiB
C
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/*
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* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
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* AVR32 systems.)
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DW_DMAC_H
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#define DW_DMAC_H
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#include <linux/dmaengine.h>
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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};
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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* @slave: Generic information about the slave
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* @ctl_lo: Platform-specific initializer for the CTL_LO register
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* @cfg_hi: Platform-specific initializer for the CFG_HI register
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* @cfg_lo: Platform-specific initializer for the CFG_LO register
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*/
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struct dw_dma_slave {
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struct dma_slave slave;
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u32 cfg_hi;
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u32 cfg_lo;
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};
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/* Platform-configurable bits in CFG_HI */
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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#define DWC_CFGH_PROTCTL(x) ((x) << 2)
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#define DWC_CFGH_SRC_PER(x) ((x) << 7)
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#define DWC_CFGH_DST_PER(x) ((x) << 11)
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/* Platform-configurable bits in CFG_LO */
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#define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
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#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
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#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
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#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
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#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
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#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
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#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
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#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
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#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
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#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
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#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
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static inline struct dw_dma_slave *to_dw_dma_slave(struct dma_slave *slave)
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{
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return container_of(slave, struct dw_dma_slave, slave);
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}
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#endif /* DW_DMAC_H */
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