2019-05-29 22:17:58 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2015-03-04 08:21:53 +08:00
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/*
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* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
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*
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* lpass.h - Definitions for the QTi LPASS
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*/
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#ifndef __LPASS_H__
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#define __LPASS_H__
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#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define LPASS_AHBIX_CLOCK_FREQUENCY 131072000
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2015-05-22 05:52:49 +08:00
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#define LPASS_MAX_MI2S_PORTS (8)
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2015-05-22 05:53:14 +08:00
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#define LPASS_MAX_DMA_CHANNELS (8)
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2015-03-04 08:21:53 +08:00
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2020-08-14 18:53:01 +08:00
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struct lpaif_i2sctl {
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struct regmap_field *loopback;
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struct regmap_field *spken;
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struct regmap_field *spkmode;
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struct regmap_field *spkmono;
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struct regmap_field *micen;
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struct regmap_field *micmode;
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struct regmap_field *micmono;
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struct regmap_field *wssrc;
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struct regmap_field *bitwidth;
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};
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struct lpaif_dmactl {
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struct regmap_field *bursten;
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struct regmap_field *wpscnt;
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struct regmap_field *intf;
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struct regmap_field *fifowm;
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struct regmap_field *enable;
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struct regmap_field *dyncclk;
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};
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2015-03-04 08:21:53 +08:00
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/* Both the CPU DAI and platform drivers will access this data */
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struct lpass_data {
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/* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
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struct clk *ahbix_clk;
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/* MI2S system clock */
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2015-05-22 05:52:49 +08:00
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struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
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2015-03-04 08:21:53 +08:00
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/* MI2S bit clock (derived from system clock by a divider */
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2015-05-22 05:52:49 +08:00
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struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
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2015-03-04 08:21:53 +08:00
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ASoC: qcom: lpass-cpu: Make I2S SD lines configurable
The LPASS hardware allows configuring the MI2S SD lines to use
when playing/recording audio. However, at the moment the lpass-cpu
driver has SD0 hard-coded for mono/stereo (or additional fixed
SD lines for more channels).
For weird reasons there seems to be hardware that uses one of the
other SD lines for mono/stereo. For example, some Samsung devices
use an external Speaker amplifier connected to Quaternary MI2S.
For some reason, the SD line for audio playback was connected to
SD1 rather than SD0. (I have no idea why...)
At the moment, the lpass-cpu driver cannot be configured to work
for the Speaker on these devices.
The q6afe driver already allows configuring the MI2S SD lines
through the "qcom,sd-lines" device tree property, but this works
only when routing audio through the ADSP.
This commit adds a very similar configuration for the lpass-cpu driver.
It is now possible to add additional subnodes to the lpass device in
the device tree, to configure the SD lines for playback and/or capture.
E.g. for the Samsung devices mentioned above:
&lpass {
dai@3 {
reg = <MI2S_QUATERNARY>;
qcom,playback-sd-lines = <1>;
};
};
qcom,playback/capture-sd-lines takes a list of SD lines (0-3)
in the same format as the q6afe driver. (The difference here is that
q6afe has separate DAIs for playback/capture, while lpass-cpu has one
for both...)
For backwards compatibility with older device trees, the lpass-cpu driver
defaults to LPAIF_I2SCTL_MODE_8CH if the subnode for a DAI is missing.
This is equivalent to the previous behavior: Up to 8 channels can be
configured, and SD0/QUAT01 will be chosen when setting up a stream
with fewer channels.
This allows the speaker to work on Samsung MSM8916 devices
that use an external speaker amplifier.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200425184657.121991-2-stephan@gerhold.net
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-26 02:46:57 +08:00
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/* MI2S SD lines to use for playback/capture */
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unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
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unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
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2015-03-04 08:21:53 +08:00
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/* low-power audio interface (LPAIF) registers */
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void __iomem *lpaif;
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/* regmap backed by the low-power audio interface (LPAIF) registers */
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struct regmap *lpaif_map;
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/* interrupts from the low-power audio interface (LPAIF) */
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int lpaif_irq;
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2015-05-16 20:32:17 +08:00
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/* SOC specific variations in the LPASS IP integration */
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struct lpass_variant *variant;
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2015-05-22 05:53:14 +08:00
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2015-05-22 05:53:21 +08:00
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/* bit map to keep track of static channel allocations */
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2016-02-11 20:17:51 +08:00
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unsigned long dma_ch_bit_map;
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2015-05-22 05:53:21 +08:00
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2015-05-22 05:53:14 +08:00
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/* used it for handling interrupt per dma channel */
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struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
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2015-05-22 23:53:52 +08:00
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2020-08-14 18:52:57 +08:00
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/* SOC specific clock list */
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struct clk_bulk_data *clks;
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int num_clks;
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2016-08-01 14:10:54 +08:00
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2020-08-14 18:53:01 +08:00
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/* Regmap fields of I2SCTL & DMACTL registers bitfields */
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struct lpaif_i2sctl *i2sctl;
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struct lpaif_dmactl *rd_dmactl;
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struct lpaif_dmactl *wr_dmactl;
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2015-05-16 20:32:17 +08:00
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};
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/* Vairant data per each SOC */
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struct lpass_variant {
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u32 i2sctrl_reg_base;
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u32 i2sctrl_reg_stride;
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u32 i2s_ports;
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u32 irq_reg_base;
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u32 irq_reg_stride;
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u32 irq_ports;
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u32 rdma_reg_base;
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u32 rdma_reg_stride;
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u32 rdma_channels;
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2016-02-11 20:17:23 +08:00
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u32 wrdma_reg_base;
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u32 wrdma_reg_stride;
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u32 wrdma_channels;
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2015-05-16 20:32:17 +08:00
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2020-08-14 18:53:01 +08:00
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/* I2SCTL Register fields */
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struct reg_field loopback;
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struct reg_field spken;
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struct reg_field spkmode;
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struct reg_field spkmono;
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struct reg_field micen;
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struct reg_field micmode;
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struct reg_field micmono;
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struct reg_field wssrc;
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struct reg_field bitwidth;
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/* RD_DMA Register fields */
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struct reg_field rdma_bursten;
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struct reg_field rdma_wpscnt;
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struct reg_field rdma_intf;
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struct reg_field rdma_fifowm;
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struct reg_field rdma_enable;
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struct reg_field rdma_dyncclk;
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/* WR_DMA Register fields */
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struct reg_field wrdma_bursten;
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struct reg_field wrdma_wpscnt;
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struct reg_field wrdma_intf;
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struct reg_field wrdma_fifowm;
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struct reg_field wrdma_enable;
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struct reg_field wrdma_dyncclk;
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2015-05-22 05:53:05 +08:00
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/**
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* on SOCs like APQ8016 the channel control bits start
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* at different offset to ipq806x
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**/
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2016-02-11 20:17:30 +08:00
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u32 dmactl_audif_start;
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2016-02-11 20:17:23 +08:00
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u32 wrdma_channel_start;
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2017-02-28 06:29:20 +08:00
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/* SOC specific initialization like clocks */
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2015-05-16 20:32:17 +08:00
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int (*init)(struct platform_device *pdev);
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int (*exit)(struct platform_device *pdev);
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2016-02-11 20:17:37 +08:00
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int (*alloc_dma_channel)(struct lpass_data *data, int direction);
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2015-05-16 20:32:34 +08:00
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int (*free_dma_channel)(struct lpass_data *data, int ch);
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2015-05-16 20:32:17 +08:00
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/* SOC specific dais */
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struct snd_soc_dai_driver *dai_driver;
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int num_dai;
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2017-04-05 16:34:10 +08:00
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const char * const *dai_osr_clk_names;
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const char * const *dai_bit_clk_names;
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2020-08-14 18:52:57 +08:00
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/* SOC specific clocks configuration */
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const char **clk_name;
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int num_clks;
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2015-03-04 08:21:53 +08:00
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};
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/* register the platform driver from the CPU DAI driver */
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int asoc_qcom_lpass_platform_register(struct platform_device *);
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2015-05-16 20:32:17 +08:00
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int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
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int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
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int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai);
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2015-08-28 10:53:31 +08:00
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extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
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2015-03-04 08:21:53 +08:00
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#endif /* __LPASS_H__ */
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