308 lines
7.5 KiB
C
308 lines
7.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device driver for irqs in HISI PMIC IC
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*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (c) 2011 Hisilicon.
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* Copyright (c) 2020-2021 Huawei Technologies Co., Ltd.
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*/
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/hi6421-spmi-pmic.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/irqdomain.h>
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#include <linux/regmap.h>
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struct hi6421v600_irq {
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struct device *dev;
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struct irq_domain *domain;
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int irq;
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unsigned int *irqs;
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struct regmap *regmap;
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/* Protect IRQ mask changes */
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spinlock_t lock;
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};
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enum hi6421v600_irq_list {
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OTMP = 0,
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VBUS_CONNECT,
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VBUS_DISCONNECT,
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ALARMON_R,
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HOLD_6S,
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HOLD_1S,
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POWERKEY_UP,
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POWERKEY_DOWN,
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OCP_SCP_R,
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COUL_R,
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SIM0_HPD_R,
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SIM0_HPD_F,
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SIM1_HPD_R,
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SIM1_HPD_F,
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PMIC_IRQ_LIST_MAX
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};
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#define HISI_IRQ_BANK_SIZE 2
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/*
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* IRQ number for the power key button and mask for both UP and DOWN IRQs
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*/
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#define HISI_POWERKEY_IRQ_NUM 0
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#define HISI_IRQ_POWERKEY_UP_DOWN (BIT(POWERKEY_DOWN) | BIT(POWERKEY_UP))
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/*
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* Registers for IRQ address and IRQ mask bits
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*
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* Please notice that we need to regmap a larger region, as other
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* registers are used by the irqs.
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* See drivers/irq/hi6421-irq.c.
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*/
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#define SOC_PMIC_IRQ_MASK_0_ADDR 0x0202
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#define SOC_PMIC_IRQ0_ADDR 0x0212
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/*
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* The IRQs are mapped as:
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*
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* ====================== ============= ============ =====
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* IRQ MASK REGISTER IRQ REGISTER BIT
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* ====================== ============= ============ =====
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* OTMP 0x0202 0x212 bit 0
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* VBUS_CONNECT 0x0202 0x212 bit 1
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* VBUS_DISCONNECT 0x0202 0x212 bit 2
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* ALARMON_R 0x0202 0x212 bit 3
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* HOLD_6S 0x0202 0x212 bit 4
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* HOLD_1S 0x0202 0x212 bit 5
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* POWERKEY_UP 0x0202 0x212 bit 6
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* POWERKEY_DOWN 0x0202 0x212 bit 7
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*
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* OCP_SCP_R 0x0203 0x213 bit 0
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* COUL_R 0x0203 0x213 bit 1
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* SIM0_HPD_R 0x0203 0x213 bit 2
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* SIM0_HPD_F 0x0203 0x213 bit 3
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* SIM1_HPD_R 0x0203 0x213 bit 4
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* SIM1_HPD_F 0x0203 0x213 bit 5
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* ====================== ============= ============ =====
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*
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* Each mask register contains 8 bits. The ancillary macros below
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* convert a number from 0 to 14 into a register address and a bit mask
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*/
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#define HISI_IRQ_MASK_REG(irq_data) (SOC_PMIC_IRQ_MASK_0_ADDR + \
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(irqd_to_hwirq(irq_data) / BITS_PER_BYTE))
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#define HISI_IRQ_MASK_BIT(irq_data) BIT(irqd_to_hwirq(irq_data) & (BITS_PER_BYTE - 1))
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#define HISI_8BITS_MASK 0xff
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static irqreturn_t hi6421v600_irq_handler(int irq, void *__priv)
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{
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struct hi6421v600_irq *priv = __priv;
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unsigned long pending;
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unsigned int in;
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int i, offset;
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for (i = 0; i < HISI_IRQ_BANK_SIZE; i++) {
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regmap_read(priv->regmap, SOC_PMIC_IRQ0_ADDR + i, &in);
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/* Mark pending IRQs as handled */
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regmap_write(priv->regmap, SOC_PMIC_IRQ0_ADDR + i, in);
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pending = in & HISI_8BITS_MASK;
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if (i == HISI_POWERKEY_IRQ_NUM &&
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(pending & HISI_IRQ_POWERKEY_UP_DOWN) == HISI_IRQ_POWERKEY_UP_DOWN) {
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/*
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* If both powerkey down and up IRQs are received,
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* handle them at the right order
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*/
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generic_handle_irq(priv->irqs[POWERKEY_DOWN]);
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generic_handle_irq(priv->irqs[POWERKEY_UP]);
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pending &= ~HISI_IRQ_POWERKEY_UP_DOWN;
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}
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if (!pending)
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continue;
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for_each_set_bit(offset, &pending, BITS_PER_BYTE) {
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generic_handle_irq(priv->irqs[offset + i * BITS_PER_BYTE]);
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}
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}
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return IRQ_HANDLED;
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}
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static void hi6421v600_irq_mask(struct irq_data *d)
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{
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struct hi6421v600_irq *priv = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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unsigned int data;
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u32 offset;
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offset = HISI_IRQ_MASK_REG(d);
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spin_lock_irqsave(&priv->lock, flags);
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regmap_read(priv->regmap, offset, &data);
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data |= HISI_IRQ_MASK_BIT(d);
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regmap_write(priv->regmap, offset, data);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void hi6421v600_irq_unmask(struct irq_data *d)
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{
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struct hi6421v600_irq *priv = irq_data_get_irq_chip_data(d);
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u32 data, offset;
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unsigned long flags;
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offset = HISI_IRQ_MASK_REG(d);
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spin_lock_irqsave(&priv->lock, flags);
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regmap_read(priv->regmap, offset, &data);
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data &= ~HISI_IRQ_MASK_BIT(d);
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regmap_write(priv->regmap, offset, data);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static struct irq_chip hi6421v600_pmu_irqchip = {
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.name = "hi6421v600-irq",
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.irq_mask = hi6421v600_irq_mask,
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.irq_unmask = hi6421v600_irq_unmask,
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.irq_disable = hi6421v600_irq_mask,
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.irq_enable = hi6421v600_irq_unmask,
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};
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static int hi6421v600_irq_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct hi6421v600_irq *priv = d->host_data;
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irq_set_chip_and_handler_name(virq, &hi6421v600_pmu_irqchip,
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handle_simple_irq, "hi6421v600");
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irq_set_chip_data(virq, priv);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static const struct irq_domain_ops hi6421v600_domain_ops = {
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.map = hi6421v600_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static void hi6421v600_irq_init(struct hi6421v600_irq *priv)
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{
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int i;
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unsigned int pending;
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/* Mask all IRQs */
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for (i = 0; i < HISI_IRQ_BANK_SIZE; i++)
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regmap_write(priv->regmap, SOC_PMIC_IRQ_MASK_0_ADDR + i,
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HISI_8BITS_MASK);
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/* Mark all IRQs as handled */
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for (i = 0; i < HISI_IRQ_BANK_SIZE; i++) {
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regmap_read(priv->regmap, SOC_PMIC_IRQ0_ADDR + i, &pending);
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regmap_write(priv->regmap, SOC_PMIC_IRQ0_ADDR + i,
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HISI_8BITS_MASK);
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}
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}
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static int hi6421v600_irq_probe(struct platform_device *pdev)
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{
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struct device *pmic_dev = pdev->dev.parent;
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struct device_node *np = pmic_dev->of_node;
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struct platform_device *pmic_pdev;
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struct device *dev = &pdev->dev;
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struct hi6421v600_irq *priv;
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struct hi6421_spmi_pmic *pmic;
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unsigned int virq;
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int i, ret;
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/*
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* This driver is meant to be called by hi6421-spmi-core,
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* which should first set drvdata. If this doesn't happen, hit
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* a warn on and return.
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*/
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pmic = dev_get_drvdata(pmic_dev);
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if (WARN_ON(!pmic))
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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priv->regmap = pmic->regmap;
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spin_lock_init(&priv->lock);
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pmic_pdev = container_of(pmic_dev, struct platform_device, dev);
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priv->irq = platform_get_irq(pmic_pdev, 0);
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if (priv->irq < 0) {
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dev_err(dev, "Error %d when getting IRQs\n", priv->irq);
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return priv->irq;
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}
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platform_set_drvdata(pdev, priv);
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hi6421v600_irq_init(priv);
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priv->irqs = devm_kzalloc(dev, PMIC_IRQ_LIST_MAX * sizeof(int), GFP_KERNEL);
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if (!priv->irqs)
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return -ENOMEM;
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priv->domain = irq_domain_add_simple(np, PMIC_IRQ_LIST_MAX, 0,
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&hi6421v600_domain_ops, priv);
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if (!priv->domain) {
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dev_err(dev, "Failed to create IRQ domain\n");
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return -ENODEV;
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}
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for (i = 0; i < PMIC_IRQ_LIST_MAX; i++) {
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virq = irq_create_mapping(priv->domain, i);
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if (!virq) {
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dev_err(dev, "Failed to map H/W IRQ\n");
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return -ENODEV;
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}
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priv->irqs[i] = virq;
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}
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ret = devm_request_threaded_irq(dev,
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priv->irq, hi6421v600_irq_handler,
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NULL,
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IRQF_TRIGGER_LOW | IRQF_SHARED | IRQF_NO_SUSPEND,
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"pmic", priv);
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if (ret < 0) {
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dev_err(dev, "Failed to start IRQ handling thread: error %d\n",
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ret);
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return ret;
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}
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return 0;
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}
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static const struct platform_device_id hi6421v600_irq_table[] = {
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{ .name = "hi6421v600-irq" },
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{},
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};
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MODULE_DEVICE_TABLE(platform, hi6421v600_irq_table);
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static struct platform_driver hi6421v600_irq_driver = {
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.id_table = hi6421v600_irq_table,
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.driver = {
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.name = "hi6421v600-irq",
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},
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.probe = hi6421v600_irq_probe,
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};
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module_platform_driver(hi6421v600_irq_driver);
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MODULE_DESCRIPTION("HiSilicon Hi6421v600 IRQ driver");
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MODULE_LICENSE("GPL v2");
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