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OpenCloudOS-Kernel/drivers/clk/imx/clk-gate2.c

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ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
/*
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Gated clock implementation
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
ARM: mach-imx: clk-gate2: Include "clk.h" Fix the following sparse warning: arch/arm/mach-imx/clk-gate2.c:86:12: warning: symbol 'clk_register_gate2' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-03-25 20:20:35 +08:00
#include "clk.h"
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
/**
* DOC: basic gatable clock which can gate and ungate it's ouput
*
* Traits of this clock:
* prepare - clk_(un)prepare only ensures parent is (un)prepared
* enable - clk_enable and clk_disable are functional & control gating
* rate - inherits rate from parent. No clk_set_rate support
* parent - fixed parent. No clk_set_parent support
*/
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
struct clk_gate2 {
struct clk_hw hw;
void __iomem *reg;
u8 bit_idx;
clk: imx: clk-gate2: allow custom gate configuration The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-10 10:16:47 +08:00
u8 cgr_val;
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
u8 flags;
spinlock_t *lock;
ARM: imx: add shared gate clock support It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-19 10:58:22 +08:00
unsigned int *share_count;
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
};
#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
static int clk_gate2_enable(struct clk_hw *hw)
{
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
struct clk_gate2 *gate = to_clk_gate2(hw);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
u32 reg;
unsigned long flags = 0;
ARM: imx: lock is always valid for clk_gate2 The imx specific clk_gate2 always has a valid lock with the clock. So the validation on gate->lock is not really needed. Remove it. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 16:07:44 +08:00
spin_lock_irqsave(gate->lock, flags);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
ARM: imx: add shared gate clock support It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-19 10:58:22 +08:00
if (gate->share_count && (*gate->share_count)++ > 0)
goto out;
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
reg = readl(gate->reg);
clk: imx: clk-gate2: allow custom gate configuration The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-10 10:16:47 +08:00
reg &= ~(3 << gate->bit_idx);
reg |= gate->cgr_val << gate->bit_idx;
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
writel(reg, gate->reg);
ARM: imx: add shared gate clock support It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-19 10:58:22 +08:00
out:
ARM: imx: lock is always valid for clk_gate2 The imx specific clk_gate2 always has a valid lock with the clock. So the validation on gate->lock is not really needed. Remove it. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 16:07:44 +08:00
spin_unlock_irqrestore(gate->lock, flags);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
return 0;
}
static void clk_gate2_disable(struct clk_hw *hw)
{
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
struct clk_gate2 *gate = to_clk_gate2(hw);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
u32 reg;
unsigned long flags = 0;
ARM: imx: lock is always valid for clk_gate2 The imx specific clk_gate2 always has a valid lock with the clock. So the validation on gate->lock is not really needed. Remove it. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 16:07:44 +08:00
spin_lock_irqsave(gate->lock, flags);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
ARM: imx: fix shared gate clock Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-07 10:53:51 +08:00
if (gate->share_count) {
if (WARN_ON(*gate->share_count == 0))
goto out;
else if (--(*gate->share_count) > 0)
goto out;
}
ARM: imx: add shared gate clock support It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-19 10:58:22 +08:00
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
writel(reg, gate->reg);
ARM: imx: add shared gate clock support It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-19 10:58:22 +08:00
out:
ARM: imx: lock is always valid for clk_gate2 The imx specific clk_gate2 always has a valid lock with the clock. So the validation on gate->lock is not really needed. Remove it. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 16:07:44 +08:00
spin_unlock_irqrestore(gate->lock, flags);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
}
ARM: imx: fix shared gate clock Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-07 10:53:51 +08:00
static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
{
ARM: imx: fix shared gate clock Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-07 10:53:51 +08:00
u32 val = readl(reg);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
ARM: imx: fix shared gate clock Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-07 10:53:51 +08:00
if (((val >> bit_idx) & 1) == 1)
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
return 1;
return 0;
}
ARM: imx: fix shared gate clock Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-07 10:53:51 +08:00
static int clk_gate2_is_enabled(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
ARM: imx: correct the hardware clock gate setting for shared nodes For those clk gates which hold share count, since its is_enabled callback is only checking the share count rather than reading the hardware register setting, in the late phase of kernel bootup, the clk_disable_unused action will NOT handle the scenario of share_count is 0 but the hardware setting is enabled, actually, U-Boot normally enables all clk gates, then those shared clk gates will be always enabled until they are used by some modules. So the problem would be: when kernel boot up, the usecount cat from clk tree is 0, but the clk gates actually is enabled in hardware register, it will confuse user and bring unnecessary power consumption. This patch adds .disable_unused callback and using hardware register check for .is_enabled callback of shared nodes to handle such scenario in late phase of kernel boot up, then the hardware status will match the clk tree info. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-12-10 17:51:42 +08:00
return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
}
static void clk_gate2_disable_unused(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
unsigned long flags = 0;
u32 reg;
spin_lock_irqsave(gate->lock, flags);
if (!gate->share_count || *gate->share_count == 0) {
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
writel(reg, gate->reg);
}
spin_unlock_irqrestore(gate->lock, flags);
ARM: imx: fix shared gate clock Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-07 10:53:51 +08:00
}
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
static struct clk_ops clk_gate2_ops = {
.enable = clk_gate2_enable,
.disable = clk_gate2_disable,
ARM: imx: correct the hardware clock gate setting for shared nodes For those clk gates which hold share count, since its is_enabled callback is only checking the share count rather than reading the hardware register setting, in the late phase of kernel bootup, the clk_disable_unused action will NOT handle the scenario of share_count is 0 but the hardware setting is enabled, actually, U-Boot normally enables all clk gates, then those shared clk gates will be always enabled until they are used by some modules. So the problem would be: when kernel boot up, the usecount cat from clk tree is 0, but the clk gates actually is enabled in hardware register, it will confuse user and bring unnecessary power consumption. This patch adds .disable_unused callback and using hardware register check for .is_enabled callback of shared nodes to handle such scenario in late phase of kernel boot up, then the hardware status will match the clk tree info. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-12-10 17:51:42 +08:00
.disable_unused = clk_gate2_disable_unused,
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
.is_enabled = clk_gate2_is_enabled,
};
struct clk *clk_register_gate2(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
clk: imx: clk-gate2: allow custom gate configuration The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-10 10:16:47 +08:00
void __iomem *reg, u8 bit_idx, u8 cgr_val,
ARM: imx: add shared gate clock support It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-19 10:58:22 +08:00
u8 clk_gate2_flags, spinlock_t *lock,
unsigned int *share_count)
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
{
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
struct clk_gate2 *gate;
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
struct clk *clk;
struct clk_init_data init;
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
if (!gate)
return ERR_PTR(-ENOMEM);
ARM: imx: define struct clk_gate2 on our own The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-18 15:55:16 +08:00
/* struct clk_gate2 assignments */
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
gate->reg = reg;
gate->bit_idx = bit_idx;
clk: imx: clk-gate2: allow custom gate configuration The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-10 10:16:47 +08:00
gate->cgr_val = cgr_val;
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
gate->flags = clk_gate2_flags;
gate->lock = lock;
ARM: imx: add shared gate clock support It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-19 10:58:22 +08:00
gate->share_count = share_count;
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
init.name = name;
init.ops = &clk_gate2_ops;
init.flags = flags;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
gate->hw.init = &init;
clk = clk_register(dev, &gate->hw);
if (IS_ERR(clk))
ARM i.MX: fix error-valued pointer dereference in clk_register_gate2() The error-valued pointer clk is used for the arg of kfree, it should be kfree(gate) if clk_register() return ERR_PTR(). dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-10-25 23:02:18 +08:00
kfree(gate);
ARM i.MX: Add common clock support for 2bit gate This gate consists of two bits: 0b00: clk disabled 0b01: clk enabled in run mode and disabled in sleep mode 0b11: clk enabled Currently only disabled and enabled are supported. As it's unlikely that we find something like this in another SoC create a i.MX specific clk helper for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-04-19 14:33:45 +08:00
return clk;
}