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OpenCloudOS-Kernel/arch/arm/mach-zynq/headsmp.S

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-04 16:11:33 +08:00
/* SPDX-License-Identifier: GPL-2.0-only */
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
/*
* Copyright (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
* Copyright (c) 2012-2013 Xilinx
*/
#include <linux/linkage.h>
#include <linux/init.h>
ARM: zynq: Enable big-endian Enable ARCH_SUPPORTS_BIG_ENDIAN in Kconfig. zynq_secondary_trampoline is the first function that is called on secondary CPU. Reference: "ARM: mcpm: fix big endian issue in mcpm startup code" (sha1: 519ceb9fd10cd7e836d0aa97b2068cc9e97f463b) Fix early printk support. Based on: "ARM: pl01x debug code endian fix" (sha1: 76e3faf156fa95b6465e747d702b94faf67117fc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-04-11 21:05:56 +08:00
#include <asm/assembler.h>
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
ARM: zynq: Support smp in thumb mode Add .arm directive to headsmp.S to ensure that the CPU starts in 32-bit ARM mode and the correct code size is copied on smp bring-up. This is related to the fix applied to SoCFPGA by commit 5616f36713ea ("ARM: SoCFPGA: Fix secondary CPU startup in thumb2 kernel") Additionally, start secondary CPUs on secondary_startup_arm to automatically switch from ARM to thumb on a thumb kernel Signed-off-by: Luis Araneda <luaraneda@gmail.com> Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-08-08 20:52:42 +08:00
.arm
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
ENTRY(zynq_secondary_trampoline)
ARM: zynq: Enable big-endian Enable ARCH_SUPPORTS_BIG_ENDIAN in Kconfig. zynq_secondary_trampoline is the first function that is called on secondary CPU. Reference: "ARM: mcpm: fix big endian issue in mcpm startup code" (sha1: 519ceb9fd10cd7e836d0aa97b2068cc9e97f463b) Fix early printk support. Based on: "ARM: pl01x debug code endian fix" (sha1: 76e3faf156fa95b6465e747d702b94faf67117fc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-04-11 21:05:56 +08:00
ARM_BE8(setend be) @ ensure we are in BE8 mode
ldr r0, zynq_secondary_trampoline_jump
ARM_BE8(rev r0, r0)
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
bx r0
.globl zynq_secondary_trampoline_jump
zynq_secondary_trampoline_jump:
/* Space for jumping address */
ARM: zynq: reserve space for jump target in secondary trampoline Add a zero argument to the .word directive in zynq_secondary_trampoline. Without an expression the assembler emits nothing for the .word directive. This makes it so that the intended range is communicated to ioremap and outer_flush_range in zynq_cpun_start; e.g. for LE trampoline_code_size evaluates to 12 now instead of 8. Found by inspection. I'm not aware of any real problem this fixes. Tested by doing on online/offline loop on ZC702. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-18 05:01:02 +08:00
.word 0 /* cpu 1 */
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
.globl zynq_secondary_trampoline_end
zynq_secondary_trampoline_end:
ENDPROC(zynq_secondary_trampoline)