2012-12-05 03:59:12 +08:00
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/*
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2017-12-06 04:29:31 +08:00
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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2012-12-05 03:59:12 +08:00
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* Author: Rob Clark <rob.clark@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "omap_drv.h"
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2016-04-19 07:47:02 +08:00
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struct omap_irq_wait {
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struct list_head node;
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2016-04-19 08:07:59 +08:00
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wait_queue_head_t wq;
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2018-02-11 21:07:33 +08:00
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u32 irqmask;
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2016-04-19 07:47:02 +08:00
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int count;
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};
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2016-04-19 08:07:59 +08:00
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/* call with wait_lock and dispc runtime held */
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2012-12-05 03:59:12 +08:00
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static void omap_irq_update(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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2016-04-19 07:47:02 +08:00
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struct omap_irq_wait *wait;
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2018-02-11 21:07:33 +08:00
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u32 irqmask = priv->irq_mask;
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2012-12-05 03:59:12 +08:00
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2016-04-19 08:07:59 +08:00
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assert_spin_locked(&priv->wait_lock);
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2012-12-05 03:59:12 +08:00
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2016-04-19 07:47:02 +08:00
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list_for_each_entry(wait, &priv->wait_list, node)
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irqmask |= wait->irqmask;
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2012-12-05 03:59:12 +08:00
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DBG("irqmask=%08x", irqmask);
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2015-11-06 00:39:52 +08:00
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priv->dispc_ops->write_irqenable(irqmask);
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2012-12-05 03:59:12 +08:00
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}
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2016-04-19 07:47:02 +08:00
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static void omap_irq_wait_handler(struct omap_irq_wait *wait)
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2012-12-05 03:59:12 +08:00
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{
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wait->count--;
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2016-04-19 08:07:59 +08:00
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wake_up(&wait->wq);
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2012-12-05 03:59:12 +08:00
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}
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struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
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2018-02-11 21:07:33 +08:00
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u32 irqmask, int count)
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2012-12-05 03:59:12 +08:00
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{
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2016-04-19 07:47:02 +08:00
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struct omap_drm_private *priv = dev->dev_private;
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2012-12-05 03:59:12 +08:00
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struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
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2016-04-19 07:47:02 +08:00
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unsigned long flags;
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2016-04-19 08:07:59 +08:00
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init_waitqueue_head(&wait->wq);
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2016-04-19 07:47:02 +08:00
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wait->irqmask = irqmask;
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2012-12-05 03:59:12 +08:00
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wait->count = count;
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2016-04-19 07:47:02 +08:00
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2016-04-19 08:07:59 +08:00
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spin_lock_irqsave(&priv->wait_lock, flags);
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2016-04-19 07:47:02 +08:00
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list_add(&wait->node, &priv->wait_list);
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omap_irq_update(dev);
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2016-04-19 08:07:59 +08:00
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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2016-04-19 07:47:02 +08:00
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2012-12-05 03:59:12 +08:00
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return wait;
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}
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int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
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unsigned long timeout)
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{
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2016-04-19 08:07:59 +08:00
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struct omap_drm_private *priv = dev->dev_private;
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2016-04-19 07:47:02 +08:00
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unsigned long flags;
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2016-04-19 08:07:59 +08:00
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int ret;
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ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout);
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2016-04-19 07:47:02 +08:00
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2016-04-19 08:07:59 +08:00
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spin_lock_irqsave(&priv->wait_lock, flags);
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2016-04-19 07:47:02 +08:00
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list_del(&wait->node);
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omap_irq_update(dev);
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2016-04-19 08:07:59 +08:00
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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2016-04-19 07:47:02 +08:00
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2012-12-05 03:59:12 +08:00
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kfree(wait);
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2016-04-19 07:47:02 +08:00
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return ret == 0 ? -1 : 0;
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2012-12-05 03:59:12 +08:00
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}
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/**
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* enable_vblank - enable vblank interrupt events
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* @dev: DRM device
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2015-09-25 00:35:31 +08:00
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* @pipe: which irq to enable
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2012-12-05 03:59:12 +08:00
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*
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* Enable vblank interrupts for @crtc. If the device doesn't have
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* a hardware vblank counter, this routine should be a no-op, since
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* interrupts will have to stay on to keep the count accurate.
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*
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* RETURNS
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* Zero on success, appropriate errno if the given @crtc's vblank
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* interrupt cannot be enabled.
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*/
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2017-02-08 19:26:00 +08:00
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int omap_irq_enable_vblank(struct drm_crtc *crtc)
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2012-12-05 03:59:12 +08:00
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{
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2017-02-08 19:26:00 +08:00
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struct drm_device *dev = crtc->dev;
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2012-12-05 03:59:12 +08:00
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struct omap_drm_private *priv = dev->dev_private;
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unsigned long flags;
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2017-02-08 19:26:00 +08:00
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enum omap_channel channel = omap_crtc_channel(crtc);
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2012-12-05 03:59:12 +08:00
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2017-02-08 19:26:00 +08:00
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DBG("dev=%p, crtc=%u", dev, channel);
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2012-12-05 03:59:12 +08:00
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2016-04-19 08:07:59 +08:00
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spin_lock_irqsave(&priv->wait_lock, flags);
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2015-11-06 00:39:52 +08:00
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priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(channel);
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2012-12-05 03:59:12 +08:00
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omap_irq_update(dev);
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2016-04-19 08:07:59 +08:00
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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2012-12-05 03:59:12 +08:00
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return 0;
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}
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/**
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* disable_vblank - disable vblank interrupt events
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* @dev: DRM device
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2015-09-25 00:35:31 +08:00
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* @pipe: which irq to enable
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2012-12-05 03:59:12 +08:00
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*
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* Disable vblank interrupts for @crtc. If the device doesn't have
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* a hardware vblank counter, this routine should be a no-op, since
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* interrupts will have to stay on to keep the count accurate.
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*/
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2017-02-08 19:26:00 +08:00
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void omap_irq_disable_vblank(struct drm_crtc *crtc)
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2012-12-05 03:59:12 +08:00
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{
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2017-02-08 19:26:00 +08:00
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struct drm_device *dev = crtc->dev;
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2012-12-05 03:59:12 +08:00
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struct omap_drm_private *priv = dev->dev_private;
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unsigned long flags;
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2017-02-08 19:26:00 +08:00
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enum omap_channel channel = omap_crtc_channel(crtc);
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2012-12-05 03:59:12 +08:00
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2017-02-08 19:26:00 +08:00
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DBG("dev=%p, crtc=%u", dev, channel);
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2012-12-05 03:59:12 +08:00
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2016-04-19 08:07:59 +08:00
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spin_lock_irqsave(&priv->wait_lock, flags);
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2015-11-06 00:39:52 +08:00
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priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(channel);
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2012-12-05 03:59:12 +08:00
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omap_irq_update(dev);
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2016-04-19 08:07:59 +08:00
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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2012-12-05 03:59:12 +08:00
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}
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2015-05-28 05:21:29 +08:00
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static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
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u32 irqstatus)
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{
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static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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static const struct {
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const char *name;
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u32 mask;
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} sources[] = {
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{ "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW },
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{ "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW },
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{ "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW },
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{ "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW },
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};
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const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW
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| DISPC_IRQ_VID1_FIFO_UNDERFLOW
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| DISPC_IRQ_VID2_FIFO_UNDERFLOW
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| DISPC_IRQ_VID3_FIFO_UNDERFLOW;
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unsigned int i;
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2016-04-19 08:07:59 +08:00
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spin_lock(&priv->wait_lock);
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2015-05-28 05:21:29 +08:00
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irqstatus &= priv->irq_mask & mask;
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2016-04-19 08:07:59 +08:00
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spin_unlock(&priv->wait_lock);
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2015-05-28 05:21:29 +08:00
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if (!irqstatus)
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return;
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if (!__ratelimit(&_rs))
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return;
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DRM_ERROR("FIFO underflow on ");
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for (i = 0; i < ARRAY_SIZE(sources); ++i) {
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if (sources[i].mask & irqstatus)
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pr_cont("%s ", sources[i].name);
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}
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pr_cont("(0x%08x)\n", irqstatus);
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}
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2017-03-03 18:15:39 +08:00
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static void omap_irq_ocp_error_handler(struct drm_device *dev,
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u32 irqstatus)
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2015-05-28 06:05:20 +08:00
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{
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if (!(irqstatus & DISPC_IRQ_OCP_ERR))
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return;
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2017-03-03 18:15:39 +08:00
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dev_err_ratelimited(dev->dev, "OCP error\n");
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2015-05-28 06:05:20 +08:00
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}
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2015-01-26 04:06:45 +08:00
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static irqreturn_t omap_irq_handler(int irq, void *arg)
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2012-12-05 03:59:12 +08:00
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{
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struct drm_device *dev = (struct drm_device *) arg;
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struct omap_drm_private *priv = dev->dev_private;
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2016-04-19 07:47:02 +08:00
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struct omap_irq_wait *wait, *n;
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2012-12-05 03:59:12 +08:00
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unsigned long flags;
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unsigned int id;
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u32 irqstatus;
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2015-11-06 00:39:52 +08:00
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irqstatus = priv->dispc_ops->read_irqstatus();
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priv->dispc_ops->clear_irqstatus(irqstatus);
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priv->dispc_ops->read_irqstatus(); /* flush posted write */
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2012-12-05 03:59:12 +08:00
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VERB("irqs: %08x", irqstatus);
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drm/omap: Fix and improve crtc and overlay manager correlation
The omapdrm driver currently takes a config/module arg to figure out the number
of crtcs it needs to create. We could create as many crtcs as there are overlay
managers in the DSS hardware, but we don't do that because each crtc eats up
one DSS overlay, and that reduces the number of planes we can attach to a single
crtc.
Since the number of crtcs may be lesser than the number of hardware overlay
managers, we need to figure out which overlay managers to use for our crtcs. The
current approach is to use pipe2chan(), which returns a higher numbered manager
for the crtc.
The problem with this approach is that it assumes that the overlay managers we
choose will connect to the encoders the platform's panels are going to use,
this isn't true, an overlay manager connects only to a few outputs/encoders, and
choosing any overlay manager for our crtc might lead to a situation where the
encoder cannot connect to any of the crtcs we have chosen. For example, an
omap5-panda board has just one hdmi output. If num_crtc is set to 1, with the
current approach, pipe2chan will pick up the LCD2 overlay manager, which cannot
connect to the hdmi encoder at all. The only manager that could have connected
to hdmi was the TV overlay manager.
Therefore, there is a need to choose our overlay managers keeping in mind the
panels we have on that platform. The new approach iterates through all the
available panels, creates encoders and connectors for them, and then tries to
get a suitable overlay manager to create a crtc which can connect to the
encoders.
We use the dispc_channel field in omap_dss_output to retrieve the desired
overlay manager's channel number, we then check whether the manager had already
been assigned to a crtc or not. If it was already assigned to a crtc, we assume
that out of all the encoders which intend use this crtc, only one will run at a
time. If the overlay manager wan't assigned to a crtc till then, we create a
new crtc and link it with the overlay manager.
This approach just looks for the best dispc_channel for each encoder. On DSS HW,
some encoders can connect to multiple overlay managers. Since we don't try
looking for alternate overlay managers, there is a greater possibility that 2
or more encoders end up asking for the same crtc, causing only one encoder to
run at a time.
Also, this approach isn't the most optimal one, it can do either good or bad
depending on the sequence in which the panels/outputs are parsed. The optimal
way would be some sort of back tracking approach, where we improve the set of
managers we use as we iterate through the list of panels/encoders. That's
something left for later.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 21:45:19 +08:00
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for (id = 0; id < priv->num_crtcs; id++) {
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struct drm_crtc *crtc = priv->crtcs[id];
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2015-05-28 05:21:29 +08:00
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enum omap_channel channel = omap_crtc_channel(crtc);
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drm/omap: Fix and improve crtc and overlay manager correlation
The omapdrm driver currently takes a config/module arg to figure out the number
of crtcs it needs to create. We could create as many crtcs as there are overlay
managers in the DSS hardware, but we don't do that because each crtc eats up
one DSS overlay, and that reduces the number of planes we can attach to a single
crtc.
Since the number of crtcs may be lesser than the number of hardware overlay
managers, we need to figure out which overlay managers to use for our crtcs. The
current approach is to use pipe2chan(), which returns a higher numbered manager
for the crtc.
The problem with this approach is that it assumes that the overlay managers we
choose will connect to the encoders the platform's panels are going to use,
this isn't true, an overlay manager connects only to a few outputs/encoders, and
choosing any overlay manager for our crtc might lead to a situation where the
encoder cannot connect to any of the crtcs we have chosen. For example, an
omap5-panda board has just one hdmi output. If num_crtc is set to 1, with the
current approach, pipe2chan will pick up the LCD2 overlay manager, which cannot
connect to the hdmi encoder at all. The only manager that could have connected
to hdmi was the TV overlay manager.
Therefore, there is a need to choose our overlay managers keeping in mind the
panels we have on that platform. The new approach iterates through all the
available panels, creates encoders and connectors for them, and then tries to
get a suitable overlay manager to create a crtc which can connect to the
encoders.
We use the dispc_channel field in omap_dss_output to retrieve the desired
overlay manager's channel number, we then check whether the manager had already
been assigned to a crtc or not. If it was already assigned to a crtc, we assume
that out of all the encoders which intend use this crtc, only one will run at a
time. If the overlay manager wan't assigned to a crtc till then, we create a
new crtc and link it with the overlay manager.
This approach just looks for the best dispc_channel for each encoder. On DSS HW,
some encoders can connect to multiple overlay managers. Since we don't try
looking for alternate overlay managers, there is a greater possibility that 2
or more encoders end up asking for the same crtc, causing only one encoder to
run at a time.
Also, this approach isn't the most optimal one, it can do either good or bad
depending on the sequence in which the panels/outputs are parsed. The optimal
way would be some sort of back tracking approach, where we improve the set of
managers we use as we iterate through the list of panels/encoders. That's
something left for later.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 21:45:19 +08:00
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|
2015-11-06 00:39:52 +08:00
|
|
|
if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(channel)) {
|
2012-12-05 03:59:12 +08:00
|
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drm_handle_vblank(dev, id);
|
2016-04-19 06:43:03 +08:00
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omap_crtc_vblank_irq(crtc);
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}
|
2015-05-28 05:21:29 +08:00
|
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2015-11-06 00:39:52 +08:00
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|
|
if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(channel))
|
2015-05-28 05:21:29 +08:00
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|
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omap_crtc_error_irq(crtc, irqstatus);
|
drm/omap: Fix and improve crtc and overlay manager correlation
The omapdrm driver currently takes a config/module arg to figure out the number
of crtcs it needs to create. We could create as many crtcs as there are overlay
managers in the DSS hardware, but we don't do that because each crtc eats up
one DSS overlay, and that reduces the number of planes we can attach to a single
crtc.
Since the number of crtcs may be lesser than the number of hardware overlay
managers, we need to figure out which overlay managers to use for our crtcs. The
current approach is to use pipe2chan(), which returns a higher numbered manager
for the crtc.
The problem with this approach is that it assumes that the overlay managers we
choose will connect to the encoders the platform's panels are going to use,
this isn't true, an overlay manager connects only to a few outputs/encoders, and
choosing any overlay manager for our crtc might lead to a situation where the
encoder cannot connect to any of the crtcs we have chosen. For example, an
omap5-panda board has just one hdmi output. If num_crtc is set to 1, with the
current approach, pipe2chan will pick up the LCD2 overlay manager, which cannot
connect to the hdmi encoder at all. The only manager that could have connected
to hdmi was the TV overlay manager.
Therefore, there is a need to choose our overlay managers keeping in mind the
panels we have on that platform. The new approach iterates through all the
available panels, creates encoders and connectors for them, and then tries to
get a suitable overlay manager to create a crtc which can connect to the
encoders.
We use the dispc_channel field in omap_dss_output to retrieve the desired
overlay manager's channel number, we then check whether the manager had already
been assigned to a crtc or not. If it was already assigned to a crtc, we assume
that out of all the encoders which intend use this crtc, only one will run at a
time. If the overlay manager wan't assigned to a crtc till then, we create a
new crtc and link it with the overlay manager.
This approach just looks for the best dispc_channel for each encoder. On DSS HW,
some encoders can connect to multiple overlay managers. Since we don't try
looking for alternate overlay managers, there is a greater possibility that 2
or more encoders end up asking for the same crtc, causing only one encoder to
run at a time.
Also, this approach isn't the most optimal one, it can do either good or bad
depending on the sequence in which the panels/outputs are parsed. The optimal
way would be some sort of back tracking approach, where we improve the set of
managers we use as we iterate through the list of panels/encoders. That's
something left for later.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 21:45:19 +08:00
|
|
|
}
|
2012-12-05 03:59:12 +08:00
|
|
|
|
2017-03-03 18:15:39 +08:00
|
|
|
omap_irq_ocp_error_handler(dev, irqstatus);
|
2015-05-28 05:21:29 +08:00
|
|
|
omap_irq_fifo_underflow(priv, irqstatus);
|
|
|
|
|
2016-04-19 08:07:59 +08:00
|
|
|
spin_lock_irqsave(&priv->wait_lock, flags);
|
2016-04-19 07:47:02 +08:00
|
|
|
list_for_each_entry_safe(wait, n, &priv->wait_list, node) {
|
|
|
|
if (wait->irqmask & irqstatus)
|
|
|
|
omap_irq_wait_handler(wait);
|
2012-12-05 03:59:12 +08:00
|
|
|
}
|
2016-04-19 08:07:59 +08:00
|
|
|
spin_unlock_irqrestore(&priv->wait_lock, flags);
|
2012-12-05 03:59:12 +08:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2015-05-28 05:21:29 +08:00
|
|
|
static const u32 omap_underflow_irqs[] = {
|
|
|
|
[OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW,
|
|
|
|
[OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW,
|
|
|
|
[OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW,
|
|
|
|
[OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW,
|
|
|
|
};
|
|
|
|
|
2015-01-26 04:06:45 +08:00
|
|
|
/*
|
|
|
|
* We need a special version, instead of just using drm_irq_install(),
|
|
|
|
* because we need to register the irq via omapdss. Once omapdss and
|
|
|
|
* omapdrm are merged together we can assign the dispc hwmod data to
|
|
|
|
* ourselves and drop these and just use drm_irq_{install,uninstall}()
|
|
|
|
*/
|
2012-12-05 03:59:12 +08:00
|
|
|
|
2015-01-26 04:06:45 +08:00
|
|
|
int omap_drm_irq_install(struct drm_device *dev)
|
2012-12-05 03:59:12 +08:00
|
|
|
{
|
|
|
|
struct omap_drm_private *priv = dev->dev_private;
|
2015-11-06 00:39:52 +08:00
|
|
|
unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs();
|
2015-05-28 05:21:29 +08:00
|
|
|
unsigned int max_planes;
|
|
|
|
unsigned int i;
|
2015-01-26 04:06:45 +08:00
|
|
|
int ret;
|
2012-12-05 03:59:12 +08:00
|
|
|
|
2016-04-19 08:07:59 +08:00
|
|
|
spin_lock_init(&priv->wait_lock);
|
2016-04-19 07:47:02 +08:00
|
|
|
INIT_LIST_HEAD(&priv->wait_list);
|
2012-12-05 03:59:12 +08:00
|
|
|
|
2015-05-28 06:05:20 +08:00
|
|
|
priv->irq_mask = DISPC_IRQ_OCP_ERR;
|
2015-05-28 05:21:29 +08:00
|
|
|
|
|
|
|
max_planes = min(ARRAY_SIZE(priv->planes),
|
|
|
|
ARRAY_SIZE(omap_underflow_irqs));
|
|
|
|
for (i = 0; i < max_planes; ++i) {
|
|
|
|
if (priv->planes[i])
|
|
|
|
priv->irq_mask |= omap_underflow_irqs[i];
|
|
|
|
}
|
|
|
|
|
2015-05-28 05:21:29 +08:00
|
|
|
for (i = 0; i < num_mgrs; ++i)
|
2015-11-06 00:39:52 +08:00
|
|
|
priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(i);
|
2015-05-28 05:21:29 +08:00
|
|
|
|
2015-11-06 00:39:52 +08:00
|
|
|
priv->dispc_ops->runtime_get();
|
|
|
|
priv->dispc_ops->clear_irqstatus(0xffffffff);
|
|
|
|
priv->dispc_ops->runtime_put();
|
2015-01-26 04:06:45 +08:00
|
|
|
|
2015-11-06 00:39:52 +08:00
|
|
|
ret = priv->dispc_ops->request_irq(omap_irq_handler, dev);
|
2015-01-26 04:06:45 +08:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-10-04 19:53:37 +08:00
|
|
|
dev->irq_enabled = true;
|
2012-12-05 03:59:12 +08:00
|
|
|
|
2015-01-26 04:06:45 +08:00
|
|
|
return 0;
|
2012-12-05 03:59:12 +08:00
|
|
|
}
|
|
|
|
|
2015-01-26 04:06:45 +08:00
|
|
|
void omap_drm_irq_uninstall(struct drm_device *dev)
|
2012-12-05 03:59:12 +08:00
|
|
|
{
|
2015-11-06 00:39:52 +08:00
|
|
|
struct omap_drm_private *priv = dev->dev_private;
|
2012-12-05 03:59:12 +08:00
|
|
|
|
2015-01-26 04:06:45 +08:00
|
|
|
if (!dev->irq_enabled)
|
|
|
|
return;
|
|
|
|
|
2013-10-04 19:53:37 +08:00
|
|
|
dev->irq_enabled = false;
|
2012-12-05 03:59:12 +08:00
|
|
|
|
2015-11-06 00:39:52 +08:00
|
|
|
priv->dispc_ops->free_irq(dev);
|
2012-12-05 03:59:12 +08:00
|
|
|
}
|