2009-11-03 17:23:50 +08:00
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/*
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* linux/drivers/video/omap2/dss/dss.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "DSS"
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#include <linux/kernel.h>
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2013-12-16 21:13:24 +08:00
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#include <linux/module.h>
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2009-11-03 17:23:50 +08:00
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#include <linux/io.h>
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2011-07-11 01:20:26 +08:00
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#include <linux/export.h>
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2009-11-03 17:23:50 +08:00
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/clk.h>
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2011-05-23 16:51:18 +08:00
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#include <linux/platform_device.h>
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2011-05-27 15:52:19 +08:00
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#include <linux/pm_runtime.h>
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2012-07-11 21:06:18 +08:00
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#include <linux/gfp.h>
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2012-09-28 18:54:35 +08:00
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#include <linux/sizes.h>
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2014-07-04 16:07:15 +08:00
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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2013-12-16 21:13:24 +08:00
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#include <linux/of.h>
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2014-07-04 16:08:27 +08:00
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#include <linux/regulator/consumer.h>
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2015-02-25 18:08:14 +08:00
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#include <linux/suspend.h>
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OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
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#include <linux/component.h>
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2009-11-03 17:23:50 +08:00
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2011-05-11 19:05:07 +08:00
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#include <video/omapdss.h>
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2012-02-25 02:34:35 +08:00
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2009-11-03 17:23:50 +08:00
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#include "dss.h"
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2011-02-24 20:18:50 +08:00
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#include "dss_features.h"
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2009-11-03 17:23:50 +08:00
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#define DSS_SZ_REGS SZ_512
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struct dss_reg {
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u16 idx;
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};
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#define DSS_REG(idx) ((const struct dss_reg) { idx })
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#define DSS_REVISION DSS_REG(0x0000)
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#define DSS_SYSCONFIG DSS_REG(0x0010)
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#define DSS_SYSSTATUS DSS_REG(0x0014)
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#define DSS_CONTROL DSS_REG(0x0040)
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#define DSS_SDI_CONTROL DSS_REG(0x0044)
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#define DSS_PLL_CONTROL DSS_REG(0x0048)
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#define DSS_SDI_STATUS DSS_REG(0x005C)
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#define REG_GET(idx, start, end) \
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FLD_GET(dss_read_reg(idx), start, end)
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#define REG_FLD_MOD(idx, val, start, end) \
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dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
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2012-07-11 21:06:18 +08:00
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struct dss_features {
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u8 fck_div_max;
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u8 dss_fck_multiplier;
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2013-11-01 17:38:04 +08:00
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const char *parent_clk_name;
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2014-12-11 21:59:31 +08:00
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const enum omap_display_type *ports;
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2014-05-22 19:31:57 +08:00
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int num_ports;
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2014-04-23 20:30:18 +08:00
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int (*dpi_select_source)(int port, enum omap_channel channel);
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2012-07-11 21:06:18 +08:00
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};
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2009-11-03 17:23:50 +08:00
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static struct {
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2011-01-24 14:21:57 +08:00
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struct platform_device *pdev;
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2009-11-03 17:23:50 +08:00
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void __iomem *base;
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2014-07-04 16:07:15 +08:00
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struct regmap *syscon_pll_ctrl;
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u32 syscon_pll_ctrl_offset;
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2011-05-27 15:52:19 +08:00
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2013-11-01 17:38:04 +08:00
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struct clk *parent_clk;
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2011-05-27 15:52:19 +08:00
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struct clk *dss_clk;
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2012-12-12 16:37:03 +08:00
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unsigned long dss_clk_rate;
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2009-11-03 17:23:50 +08:00
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unsigned long cache_req_pck;
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unsigned long cache_prate;
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struct dispc_clock_info cache_dispc_cinfo;
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2016-05-17 18:45:09 +08:00
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enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
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enum dss_clk_source dispc_clk_source;
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enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
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2010-01-09 00:00:36 +08:00
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2011-06-01 20:56:39 +08:00
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bool ctx_valid;
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2009-11-03 17:23:50 +08:00
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u32 ctx[DSS_SZ_REGS / sizeof(u32)];
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2012-07-11 21:06:18 +08:00
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const struct dss_features *feat;
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2014-07-04 16:08:27 +08:00
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struct dss_pll *video1_pll;
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struct dss_pll *video2_pll;
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2009-11-03 17:23:50 +08:00
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} dss;
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2011-03-15 12:28:21 +08:00
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static const char * const dss_generic_clk_source_names[] = {
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2016-05-17 19:01:10 +08:00
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[DSS_CLK_SRC_FCK] = "FCK",
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[DSS_CLK_SRC_PLL1_1] = "PLL1:1",
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[DSS_CLK_SRC_PLL1_2] = "PLL1:2",
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[DSS_CLK_SRC_PLL2_1] = "PLL2:1",
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[DSS_CLK_SRC_PLL2_2] = "PLL2:2",
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2011-03-02 14:27:25 +08:00
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};
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2015-06-04 17:35:42 +08:00
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static bool dss_initialized;
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bool omapdss_is_initialized(void)
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{
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return dss_initialized;
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}
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EXPORT_SYMBOL(omapdss_is_initialized);
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2009-11-03 17:23:50 +08:00
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static inline void dss_write_reg(const struct dss_reg idx, u32 val)
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{
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__raw_writel(val, dss.base + idx.idx);
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}
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static inline u32 dss_read_reg(const struct dss_reg idx)
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{
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return __raw_readl(dss.base + idx.idx);
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}
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#define SR(reg) \
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dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
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#define RR(reg) \
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dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
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2011-05-27 15:52:19 +08:00
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static void dss_save_context(void)
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2009-11-03 17:23:50 +08:00
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{
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2011-05-27 15:52:19 +08:00
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DSSDBG("dss_save_context\n");
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2009-11-03 17:23:50 +08:00
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SR(CONTROL);
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2011-02-24 20:18:50 +08:00
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if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
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OMAP_DISPLAY_TYPE_SDI) {
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SR(SDI_CONTROL);
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SR(PLL_CONTROL);
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}
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2011-06-01 20:56:39 +08:00
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dss.ctx_valid = true;
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DSSDBG("context saved\n");
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2009-11-03 17:23:50 +08:00
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}
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2011-05-27 15:52:19 +08:00
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static void dss_restore_context(void)
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2009-11-03 17:23:50 +08:00
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{
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2011-05-27 15:52:19 +08:00
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DSSDBG("dss_restore_context\n");
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2009-11-03 17:23:50 +08:00
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2011-06-01 20:56:39 +08:00
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if (!dss.ctx_valid)
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return;
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2009-11-03 17:23:50 +08:00
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RR(CONTROL);
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2011-02-24 20:18:50 +08:00
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if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
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OMAP_DISPLAY_TYPE_SDI) {
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RR(SDI_CONTROL);
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RR(PLL_CONTROL);
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}
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2011-06-01 20:56:39 +08:00
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DSSDBG("context restored\n");
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2009-11-03 17:23:50 +08:00
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}
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#undef SR
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#undef RR
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2014-07-04 16:07:15 +08:00
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void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
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{
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unsigned shift;
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unsigned val;
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if (!dss.syscon_pll_ctrl)
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return;
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val = !enable;
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switch (pll_id) {
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case DSS_PLL_VIDEO1:
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shift = 0;
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break;
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case DSS_PLL_VIDEO2:
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shift = 1;
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break;
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case DSS_PLL_HDMI:
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shift = 2;
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break;
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default:
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DSSERR("illegal DSS PLL ID %d\n", pll_id);
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return;
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}
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regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
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1 << shift, val << shift);
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}
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void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
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enum omap_channel channel)
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{
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unsigned shift, val;
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if (!dss.syscon_pll_ctrl)
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return;
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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shift = 3;
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switch (pll_id) {
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case DSS_PLL_VIDEO1:
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val = 0; break;
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case DSS_PLL_HDMI:
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val = 1; break;
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default:
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DSSERR("error in PLL mux config for LCD\n");
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return;
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}
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break;
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case OMAP_DSS_CHANNEL_LCD2:
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shift = 5;
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switch (pll_id) {
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case DSS_PLL_VIDEO1:
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val = 0; break;
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case DSS_PLL_VIDEO2:
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val = 1; break;
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case DSS_PLL_HDMI:
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val = 2; break;
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default:
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DSSERR("error in PLL mux config for LCD2\n");
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return;
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}
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break;
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case OMAP_DSS_CHANNEL_LCD3:
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shift = 7;
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switch (pll_id) {
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case DSS_PLL_VIDEO1:
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val = 1; break;
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case DSS_PLL_VIDEO2:
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val = 0; break;
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case DSS_PLL_HDMI:
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val = 2; break;
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default:
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DSSERR("error in PLL mux config for LCD3\n");
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return;
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}
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break;
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default:
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DSSERR("error in PLL mux config\n");
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return;
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}
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regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
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0x3 << shift, val << shift);
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}
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2012-07-20 19:48:49 +08:00
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void dss_sdi_init(int datapairs)
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2009-11-03 17:23:50 +08:00
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{
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u32 l;
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BUG_ON(datapairs > 3 || datapairs < 1);
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l = dss_read_reg(DSS_SDI_CONTROL);
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l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
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l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
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l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
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dss_write_reg(DSS_SDI_CONTROL, l);
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l = dss_read_reg(DSS_PLL_CONTROL);
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l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
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l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
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l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
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dss_write_reg(DSS_PLL_CONTROL, l);
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}
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int dss_sdi_enable(void)
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{
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unsigned long timeout;
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dispc_pck_free_enable(1);
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/* Reset SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
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udelay(1); /* wait 2x PCLK */
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/* Lock SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
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/* Waiting for PLL lock request to complete */
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timeout = jiffies + msecs_to_jiffies(500);
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while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
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if (time_after_eq(jiffies, timeout)) {
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DSSERR("PLL lock request timed out\n");
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goto err1;
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}
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}
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/* Clearing PLL_GO bit */
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REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
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/* Waiting for PLL to lock */
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|
|
timeout = jiffies + msecs_to_jiffies(500);
|
|
|
|
while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
|
|
|
|
if (time_after_eq(jiffies, timeout)) {
|
|
|
|
DSSERR("PLL lock timed out\n");
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dispc_lcd_enable_signal(1);
|
|
|
|
|
|
|
|
/* Waiting for SDI reset to complete */
|
|
|
|
timeout = jiffies + msecs_to_jiffies(500);
|
|
|
|
while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
|
|
|
|
if (time_after_eq(jiffies, timeout)) {
|
|
|
|
DSSERR("SDI reset timed out\n");
|
|
|
|
goto err2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err2:
|
|
|
|
dispc_lcd_enable_signal(0);
|
|
|
|
err1:
|
|
|
|
/* Reset SDI PLL */
|
|
|
|
REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
|
|
|
|
|
|
|
|
dispc_pck_free_enable(0);
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dss_sdi_disable(void)
|
|
|
|
{
|
|
|
|
dispc_lcd_enable_signal(0);
|
|
|
|
|
|
|
|
dispc_pck_free_enable(0);
|
|
|
|
|
|
|
|
/* Reset SDI PLL */
|
|
|
|
REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
|
|
|
|
}
|
|
|
|
|
2016-05-17 18:50:55 +08:00
|
|
|
const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
|
2011-03-02 14:27:25 +08:00
|
|
|
{
|
2011-03-15 12:28:21 +08:00
|
|
|
return dss_generic_clk_source_names[clk_src];
|
2011-03-02 14:27:25 +08:00
|
|
|
}
|
|
|
|
|
2009-11-03 17:23:50 +08:00
|
|
|
void dss_dump_clocks(struct seq_file *s)
|
|
|
|
{
|
2016-05-17 18:49:18 +08:00
|
|
|
const char *fclk_name;
|
2011-03-14 20:28:57 +08:00
|
|
|
unsigned long fclk_rate;
|
2009-11-03 17:23:50 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
if (dss_runtime_get())
|
|
|
|
return;
|
2009-11-03 17:23:50 +08:00
|
|
|
|
|
|
|
seq_printf(s, "- DSS -\n");
|
|
|
|
|
2016-05-17 19:01:10 +08:00
|
|
|
fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK);
|
2011-05-27 15:52:19 +08:00
|
|
|
fclk_rate = clk_get_rate(dss.dss_clk);
|
2009-11-03 17:23:50 +08:00
|
|
|
|
2016-05-17 18:49:18 +08:00
|
|
|
seq_printf(s, "%s = %lu\n",
|
|
|
|
fclk_name,
|
2013-11-01 17:36:10 +08:00
|
|
|
fclk_rate);
|
2009-11-03 17:23:50 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
dss_runtime_put();
|
2009-11-03 17:23:50 +08:00
|
|
|
}
|
|
|
|
|
2012-03-03 00:01:07 +08:00
|
|
|
static void dss_dump_regs(struct seq_file *s)
|
2009-11-03 17:23:50 +08:00
|
|
|
{
|
|
|
|
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
|
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
if (dss_runtime_get())
|
|
|
|
return;
|
2009-11-03 17:23:50 +08:00
|
|
|
|
|
|
|
DUMPREG(DSS_REVISION);
|
|
|
|
DUMPREG(DSS_SYSCONFIG);
|
|
|
|
DUMPREG(DSS_SYSSTATUS);
|
|
|
|
DUMPREG(DSS_CONTROL);
|
2011-02-24 20:18:50 +08:00
|
|
|
|
|
|
|
if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
|
|
|
|
OMAP_DISPLAY_TYPE_SDI) {
|
|
|
|
DUMPREG(DSS_SDI_CONTROL);
|
|
|
|
DUMPREG(DSS_PLL_CONTROL);
|
|
|
|
DUMPREG(DSS_SDI_STATUS);
|
|
|
|
}
|
2009-11-03 17:23:50 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
dss_runtime_put();
|
2009-11-03 17:23:50 +08:00
|
|
|
#undef DUMPREG
|
|
|
|
}
|
|
|
|
|
2016-05-17 18:45:09 +08:00
|
|
|
static void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
|
2010-01-09 00:00:36 +08:00
|
|
|
{
|
|
|
|
int b;
|
2011-03-08 19:50:35 +08:00
|
|
|
u8 start, end;
|
2010-01-09 00:00:36 +08:00
|
|
|
|
2011-03-08 19:50:34 +08:00
|
|
|
switch (clk_src) {
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_FCK:
|
2011-03-08 19:50:34 +08:00
|
|
|
b = 0;
|
|
|
|
break;
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_PLL1_1:
|
2011-03-08 19:50:34 +08:00
|
|
|
b = 1;
|
|
|
|
break;
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_PLL2_1:
|
2011-05-12 19:56:29 +08:00
|
|
|
b = 2;
|
|
|
|
break;
|
2011-03-08 19:50:34 +08:00
|
|
|
default:
|
|
|
|
BUG();
|
2012-05-18 16:47:02 +08:00
|
|
|
return;
|
2011-03-08 19:50:34 +08:00
|
|
|
}
|
2010-06-09 20:28:12 +08:00
|
|
|
|
2011-03-08 19:50:35 +08:00
|
|
|
dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
|
|
|
|
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
|
2010-01-09 00:00:36 +08:00
|
|
|
|
|
|
|
dss.dispc_clk_source = clk_src;
|
|
|
|
}
|
|
|
|
|
2011-05-12 19:56:29 +08:00
|
|
|
void dss_select_dsi_clk_source(int dsi_module,
|
2016-05-17 18:45:09 +08:00
|
|
|
enum dss_clk_source clk_src)
|
2009-11-03 17:23:50 +08:00
|
|
|
{
|
2012-05-07 19:21:35 +08:00
|
|
|
int b, pos;
|
2010-01-09 00:00:36 +08:00
|
|
|
|
2011-03-08 19:50:34 +08:00
|
|
|
switch (clk_src) {
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_FCK:
|
2011-03-08 19:50:34 +08:00
|
|
|
b = 0;
|
|
|
|
break;
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_PLL1_2:
|
2011-05-12 19:56:29 +08:00
|
|
|
BUG_ON(dsi_module != 0);
|
2011-03-08 19:50:34 +08:00
|
|
|
b = 1;
|
|
|
|
break;
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_PLL2_2:
|
2011-05-12 19:56:29 +08:00
|
|
|
BUG_ON(dsi_module != 1);
|
|
|
|
b = 1;
|
|
|
|
break;
|
2011-03-08 19:50:34 +08:00
|
|
|
default:
|
|
|
|
BUG();
|
2012-05-18 16:47:02 +08:00
|
|
|
return;
|
2011-03-08 19:50:34 +08:00
|
|
|
}
|
2010-06-09 20:28:12 +08:00
|
|
|
|
2012-05-07 19:21:35 +08:00
|
|
|
pos = dsi_module == 0 ? 1 : 10;
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
|
2010-01-09 00:00:36 +08:00
|
|
|
|
2011-05-12 19:56:29 +08:00
|
|
|
dss.dsi_clk_source[dsi_module] = clk_src;
|
2009-11-03 17:23:50 +08:00
|
|
|
}
|
|
|
|
|
2011-03-08 19:50:35 +08:00
|
|
|
void dss_select_lcd_clk_source(enum omap_channel channel,
|
2016-05-17 18:45:09 +08:00
|
|
|
enum dss_clk_source clk_src)
|
2011-03-08 19:50:35 +08:00
|
|
|
{
|
|
|
|
int b, ix, pos;
|
|
|
|
|
OMAPDSS: hide dss_select_dispc_clk_source()
dss.c currently exposes functions to configure the dispc source clock
and lcd source clock. There are configured separately from the output
drivers.
However, there is no safe way for the output drivers to handle dispc
clock, as it's shared between the outputs. Thus, if, say, the DSI driver
sets up DSI PLL and configures both the dispc and lcd clock sources to
that DSI PLL, the resulting dispc clock could be too low for, say, HDMI.
Thus the output drivers should really only be concerned about the lcd
clock, which is what the output drivers actually use. There's lot to do
to clean up the dss clock handling, but this patch takes one step
forward and removes the use of dss_select_dispc_clk_source() from the
output drivers.
After this patch, the output drivers only configure the lcd source
clock. On omap4+ the dispc src clock is never changed from the default
PRCM source. On omap3, where the dispc and lcd clocks are actually the
same, setting the lcd clock source sets the dispc clock source.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-22 21:58:36 +08:00
|
|
|
if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
|
|
|
|
dss_select_dispc_clk_source(clk_src);
|
2011-03-08 19:50:35 +08:00
|
|
|
return;
|
OMAPDSS: hide dss_select_dispc_clk_source()
dss.c currently exposes functions to configure the dispc source clock
and lcd source clock. There are configured separately from the output
drivers.
However, there is no safe way for the output drivers to handle dispc
clock, as it's shared between the outputs. Thus, if, say, the DSI driver
sets up DSI PLL and configures both the dispc and lcd clock sources to
that DSI PLL, the resulting dispc clock could be too low for, say, HDMI.
Thus the output drivers should really only be concerned about the lcd
clock, which is what the output drivers actually use. There's lot to do
to clean up the dss clock handling, but this patch takes one step
forward and removes the use of dss_select_dispc_clk_source() from the
output drivers.
After this patch, the output drivers only configure the lcd source
clock. On omap4+ the dispc src clock is never changed from the default
PRCM source. On omap3, where the dispc and lcd clocks are actually the
same, setting the lcd clock source sets the dispc clock source.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-22 21:58:36 +08:00
|
|
|
}
|
2011-03-08 19:50:35 +08:00
|
|
|
|
|
|
|
switch (clk_src) {
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_FCK:
|
2011-03-08 19:50:35 +08:00
|
|
|
b = 0;
|
|
|
|
break;
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_PLL1_1:
|
2011-03-08 19:50:35 +08:00
|
|
|
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
|
|
|
|
b = 1;
|
|
|
|
break;
|
2016-05-17 19:01:10 +08:00
|
|
|
case DSS_CLK_SRC_PLL2_1:
|
2012-06-29 13:13:13 +08:00
|
|
|
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
|
|
|
|
channel != OMAP_DSS_CHANNEL_LCD3);
|
2011-05-12 19:56:29 +08:00
|
|
|
b = 1;
|
|
|
|
break;
|
2011-03-08 19:50:35 +08:00
|
|
|
default:
|
|
|
|
BUG();
|
2012-05-18 16:47:02 +08:00
|
|
|
return;
|
2011-03-08 19:50:35 +08:00
|
|
|
}
|
|
|
|
|
2012-06-29 13:13:13 +08:00
|
|
|
pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
|
|
|
|
(channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
|
2011-03-08 19:50:35 +08:00
|
|
|
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
|
|
|
|
|
2012-06-29 13:13:13 +08:00
|
|
|
ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
|
|
|
|
(channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
|
2011-03-08 19:50:35 +08:00
|
|
|
dss.lcd_clk_source[ix] = clk_src;
|
|
|
|
}
|
|
|
|
|
2016-05-17 18:45:09 +08:00
|
|
|
enum dss_clk_source dss_get_dispc_clk_source(void)
|
2009-11-03 17:23:50 +08:00
|
|
|
{
|
2010-01-09 00:00:36 +08:00
|
|
|
return dss.dispc_clk_source;
|
2009-11-03 17:23:50 +08:00
|
|
|
}
|
|
|
|
|
2016-05-17 18:45:09 +08:00
|
|
|
enum dss_clk_source dss_get_dsi_clk_source(int dsi_module)
|
2009-11-03 17:23:50 +08:00
|
|
|
{
|
2011-05-12 19:56:29 +08:00
|
|
|
return dss.dsi_clk_source[dsi_module];
|
2009-11-03 17:23:50 +08:00
|
|
|
}
|
|
|
|
|
2016-05-17 18:45:09 +08:00
|
|
|
enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
|
2011-03-08 19:50:35 +08:00
|
|
|
{
|
2011-03-31 15:53:35 +08:00
|
|
|
if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
|
2012-06-29 13:13:13 +08:00
|
|
|
int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
|
|
|
|
(channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
|
2011-03-31 15:53:35 +08:00
|
|
|
return dss.lcd_clk_source[ix];
|
|
|
|
} else {
|
|
|
|
/* LCD_CLK source is the same as DISPC_FCLK source for
|
|
|
|
* OMAP2 and OMAP3 */
|
|
|
|
return dss.dispc_clk_source;
|
|
|
|
}
|
2011-03-08 19:50:35 +08:00
|
|
|
}
|
|
|
|
|
2013-10-31 22:41:57 +08:00
|
|
|
bool dss_div_calc(unsigned long pck, unsigned long fck_min,
|
|
|
|
dss_div_calc_func func, void *data)
|
2013-03-05 22:34:05 +08:00
|
|
|
{
|
|
|
|
int fckd, fckd_start, fckd_stop;
|
|
|
|
unsigned long fck;
|
|
|
|
unsigned long fck_hw_max;
|
|
|
|
unsigned long fckd_hw_max;
|
|
|
|
unsigned long prate;
|
2013-04-10 19:47:38 +08:00
|
|
|
unsigned m;
|
2013-03-05 22:34:05 +08:00
|
|
|
|
2013-10-31 22:42:13 +08:00
|
|
|
fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
|
|
|
|
|
2013-11-01 17:38:04 +08:00
|
|
|
if (dss.parent_clk == NULL) {
|
2013-10-31 22:42:13 +08:00
|
|
|
unsigned pckd;
|
|
|
|
|
|
|
|
pckd = fck_hw_max / pck;
|
|
|
|
|
|
|
|
fck = pck * pckd;
|
|
|
|
|
|
|
|
fck = clk_round_rate(dss.dss_clk, fck);
|
|
|
|
|
2013-10-31 20:44:23 +08:00
|
|
|
return func(fck, data);
|
2013-03-05 22:34:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
fckd_hw_max = dss.feat->fck_div_max;
|
|
|
|
|
2013-04-10 19:47:38 +08:00
|
|
|
m = dss.feat->dss_fck_multiplier;
|
2013-10-31 22:06:38 +08:00
|
|
|
prate = clk_get_rate(dss.parent_clk);
|
2013-03-05 22:34:05 +08:00
|
|
|
|
|
|
|
fck_min = fck_min ? fck_min : 1;
|
|
|
|
|
2013-04-10 19:47:38 +08:00
|
|
|
fckd_start = min(prate * m / fck_min, fckd_hw_max);
|
|
|
|
fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
|
2013-03-05 22:34:05 +08:00
|
|
|
|
|
|
|
for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
|
2014-02-13 17:36:22 +08:00
|
|
|
fck = DIV_ROUND_UP(prate, fckd) * m;
|
2013-03-05 22:34:05 +08:00
|
|
|
|
2013-10-31 20:44:23 +08:00
|
|
|
if (func(fck, data))
|
2013-03-05 22:34:05 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-10-31 20:44:23 +08:00
|
|
|
int dss_set_fck_rate(unsigned long rate)
|
2009-11-03 17:23:50 +08:00
|
|
|
{
|
2013-10-31 22:06:38 +08:00
|
|
|
int r;
|
2009-11-03 17:23:50 +08:00
|
|
|
|
2013-10-31 22:06:38 +08:00
|
|
|
DSSDBG("set fck to %lu\n", rate);
|
2009-11-03 17:23:50 +08:00
|
|
|
|
2013-10-31 22:06:38 +08:00
|
|
|
r = clk_set_rate(dss.dss_clk, rate);
|
|
|
|
if (r)
|
|
|
|
return r;
|
2009-11-03 17:23:50 +08:00
|
|
|
|
2012-12-12 16:37:03 +08:00
|
|
|
dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
|
|
|
|
|
2013-10-31 20:44:23 +08:00
|
|
|
WARN_ONCE(dss.dss_clk_rate != rate,
|
2013-04-10 19:47:38 +08:00
|
|
|
"clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
|
2013-10-31 20:44:23 +08:00
|
|
|
rate);
|
2009-11-03 17:23:50 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-12 16:37:03 +08:00
|
|
|
unsigned long dss_get_dispc_clk_rate(void)
|
|
|
|
{
|
|
|
|
return dss.dss_clk_rate;
|
|
|
|
}
|
|
|
|
|
2012-10-22 21:35:41 +08:00
|
|
|
static int dss_setup_default_clock(void)
|
|
|
|
{
|
|
|
|
unsigned long max_dss_fck, prate;
|
2013-10-31 20:44:23 +08:00
|
|
|
unsigned long fck;
|
2012-10-22 21:35:41 +08:00
|
|
|
unsigned fck_div;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
|
|
|
|
|
2013-10-31 22:42:13 +08:00
|
|
|
if (dss.parent_clk == NULL) {
|
|
|
|
fck = clk_round_rate(dss.dss_clk, max_dss_fck);
|
|
|
|
} else {
|
|
|
|
prate = clk_get_rate(dss.parent_clk);
|
2012-10-22 21:35:41 +08:00
|
|
|
|
2013-10-31 22:42:13 +08:00
|
|
|
fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
|
|
|
|
max_dss_fck);
|
2014-02-13 17:36:22 +08:00
|
|
|
fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
|
2013-10-31 22:42:13 +08:00
|
|
|
}
|
2012-10-22 21:35:41 +08:00
|
|
|
|
2013-10-31 20:44:23 +08:00
|
|
|
r = dss_set_fck_rate(fck);
|
2012-10-22 21:35:41 +08:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-03 17:23:50 +08:00
|
|
|
void dss_set_venc_output(enum omap_dss_venc_type type)
|
|
|
|
{
|
|
|
|
int l = 0;
|
|
|
|
|
|
|
|
if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
|
|
|
|
l = 0;
|
|
|
|
else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
|
|
|
|
l = 1;
|
|
|
|
else
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
/* venc out selection. 0 = comp, 1 = svideo */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dss_set_dac_pwrdn_bgz(bool enable)
|
|
|
|
{
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
|
|
|
|
}
|
|
|
|
|
2012-08-01 20:56:40 +08:00
|
|
|
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
|
2011-03-09 19:01:38 +08:00
|
|
|
{
|
2012-08-01 20:56:40 +08:00
|
|
|
enum omap_display_type dp;
|
|
|
|
dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
|
|
|
|
|
|
|
|
/* Complain about invalid selections */
|
|
|
|
WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
|
|
|
|
WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
|
|
|
|
|
|
|
|
/* Select only if we have options */
|
|
|
|
if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */
|
2011-03-09 19:01:38 +08:00
|
|
|
}
|
|
|
|
|
2011-08-31 19:33:31 +08:00
|
|
|
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
|
|
|
|
{
|
|
|
|
enum omap_display_type displays;
|
|
|
|
|
|
|
|
displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
|
|
|
|
if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
|
|
|
|
return DSS_VENC_TV_CLK;
|
|
|
|
|
2012-08-01 20:56:40 +08:00
|
|
|
if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
|
|
|
|
return DSS_HDMI_M_PCLK;
|
|
|
|
|
2011-08-31 19:33:31 +08:00
|
|
|
return REG_GET(DSS_CONTROL, 15, 15);
|
|
|
|
}
|
|
|
|
|
2014-04-23 20:30:18 +08:00
|
|
|
static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
|
2012-09-21 17:09:54 +08:00
|
|
|
{
|
|
|
|
if (channel != OMAP_DSS_CHANNEL_LCD)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-23 20:30:18 +08:00
|
|
|
static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
|
2012-09-21 17:09:54 +08:00
|
|
|
{
|
|
|
|
int val;
|
|
|
|
|
|
|
|
switch (channel) {
|
|
|
|
case OMAP_DSS_CHANNEL_LCD2:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
case OMAP_DSS_CHANNEL_DIGIT:
|
|
|
|
val = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-23 20:30:18 +08:00
|
|
|
static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
|
2012-09-21 17:09:54 +08:00
|
|
|
{
|
|
|
|
int val;
|
|
|
|
|
|
|
|
switch (channel) {
|
|
|
|
case OMAP_DSS_CHANNEL_LCD:
|
|
|
|
val = 1;
|
|
|
|
break;
|
|
|
|
case OMAP_DSS_CHANNEL_LCD2:
|
|
|
|
val = 2;
|
|
|
|
break;
|
|
|
|
case OMAP_DSS_CHANNEL_LCD3:
|
|
|
|
val = 3;
|
|
|
|
break;
|
|
|
|
case OMAP_DSS_CHANNEL_DIGIT:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-12-31 17:23:31 +08:00
|
|
|
static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
|
|
|
|
{
|
|
|
|
switch (port) {
|
|
|
|
case 0:
|
|
|
|
return dss_dpi_select_source_omap5(port, channel);
|
|
|
|
case 1:
|
|
|
|
if (channel != OMAP_DSS_CHANNEL_LCD2)
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
if (channel != OMAP_DSS_CHANNEL_LCD3)
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-23 20:30:18 +08:00
|
|
|
int dss_dpi_select_source(int port, enum omap_channel channel)
|
2012-09-21 17:09:54 +08:00
|
|
|
{
|
2014-04-23 20:30:18 +08:00
|
|
|
return dss.feat->dpi_select_source(port, channel);
|
2012-09-21 17:09:54 +08:00
|
|
|
}
|
|
|
|
|
2011-01-24 14:21:58 +08:00
|
|
|
static int dss_get_clocks(void)
|
|
|
|
{
|
2011-05-27 15:52:19 +08:00
|
|
|
struct clk *clk;
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2013-04-08 16:55:00 +08:00
|
|
|
clk = devm_clk_get(&dss.pdev->dev, "fck");
|
2011-05-27 15:52:19 +08:00
|
|
|
if (IS_ERR(clk)) {
|
|
|
|
DSSERR("can't get clock fck\n");
|
2013-04-08 16:55:00 +08:00
|
|
|
return PTR_ERR(clk);
|
2011-03-01 16:42:14 +08:00
|
|
|
}
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
dss.dss_clk = clk;
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2013-11-01 17:38:04 +08:00
|
|
|
if (dss.feat->parent_clk_name) {
|
|
|
|
clk = clk_get(NULL, dss.feat->parent_clk_name);
|
2012-11-22 03:48:51 +08:00
|
|
|
if (IS_ERR(clk)) {
|
2013-11-01 17:38:04 +08:00
|
|
|
DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
|
2013-04-08 16:55:00 +08:00
|
|
|
return PTR_ERR(clk);
|
2012-11-22 03:48:51 +08:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
clk = NULL;
|
2011-05-16 18:43:04 +08:00
|
|
|
}
|
|
|
|
|
2013-11-01 17:38:04 +08:00
|
|
|
dss.parent_clk = clk;
|
2011-05-16 18:43:04 +08:00
|
|
|
|
2011-01-24 14:21:58 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dss_put_clocks(void)
|
|
|
|
{
|
2013-11-01 17:38:04 +08:00
|
|
|
if (dss.parent_clk)
|
|
|
|
clk_put(dss.parent_clk);
|
2011-01-24 14:21:58 +08:00
|
|
|
}
|
|
|
|
|
2014-07-04 16:08:27 +08:00
|
|
|
int dss_runtime_get(void)
|
2011-01-24 14:21:58 +08:00
|
|
|
{
|
2011-05-27 15:52:19 +08:00
|
|
|
int r;
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
DSSDBG("dss_runtime_get\n");
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
r = pm_runtime_get_sync(&dss.pdev->dev);
|
|
|
|
WARN_ON(r < 0);
|
|
|
|
return r < 0 ? r : 0;
|
2011-01-24 14:21:58 +08:00
|
|
|
}
|
|
|
|
|
2014-07-04 16:08:27 +08:00
|
|
|
void dss_runtime_put(void)
|
2011-01-24 14:21:58 +08:00
|
|
|
{
|
2011-05-27 15:52:19 +08:00
|
|
|
int r;
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
DSSDBG("dss_runtime_put\n");
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2012-01-23 19:23:08 +08:00
|
|
|
r = pm_runtime_put_sync(&dss.pdev->dev);
|
2012-06-27 21:37:18 +08:00
|
|
|
WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
|
2011-01-24 14:21:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* DEBUGFS */
|
2012-09-29 13:55:42 +08:00
|
|
|
#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
|
2011-01-24 14:21:58 +08:00
|
|
|
void dss_debug_dump_clocks(struct seq_file *s)
|
|
|
|
{
|
|
|
|
dss_dump_clocks(s);
|
|
|
|
dispc_dump_clocks(s);
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_DSI
|
|
|
|
dsi_dump_clocks(s);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-05-22 19:31:57 +08:00
|
|
|
|
2014-12-11 21:59:31 +08:00
|
|
|
static const enum omap_display_type omap2plus_ports[] = {
|
2014-05-22 19:31:57 +08:00
|
|
|
OMAP_DISPLAY_TYPE_DPI,
|
|
|
|
};
|
|
|
|
|
2014-12-11 21:59:31 +08:00
|
|
|
static const enum omap_display_type omap34xx_ports[] = {
|
2014-05-22 19:31:57 +08:00
|
|
|
OMAP_DISPLAY_TYPE_DPI,
|
|
|
|
OMAP_DISPLAY_TYPE_SDI,
|
|
|
|
};
|
|
|
|
|
2014-12-31 17:23:31 +08:00
|
|
|
static const enum omap_display_type dra7xx_ports[] = {
|
|
|
|
OMAP_DISPLAY_TYPE_DPI,
|
|
|
|
OMAP_DISPLAY_TYPE_DPI,
|
|
|
|
OMAP_DISPLAY_TYPE_DPI,
|
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static const struct dss_features omap24xx_dss_feats = {
|
2013-11-01 17:26:43 +08:00
|
|
|
/*
|
|
|
|
* fck div max is really 16, but the divider range has gaps. The range
|
|
|
|
* from 1 to 6 has no gaps, so let's use that as a max.
|
|
|
|
*/
|
|
|
|
.fck_div_max = 6,
|
2012-09-21 17:03:31 +08:00
|
|
|
.dss_fck_multiplier = 2,
|
2013-10-31 22:06:38 +08:00
|
|
|
.parent_clk_name = "core_ck",
|
2012-09-21 17:09:54 +08:00
|
|
|
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
|
2014-05-22 19:31:57 +08:00
|
|
|
.ports = omap2plus_ports,
|
|
|
|
.num_ports = ARRAY_SIZE(omap2plus_ports),
|
2012-09-21 17:03:31 +08:00
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static const struct dss_features omap34xx_dss_feats = {
|
2012-09-21 17:03:31 +08:00
|
|
|
.fck_div_max = 16,
|
|
|
|
.dss_fck_multiplier = 2,
|
2013-10-31 22:06:38 +08:00
|
|
|
.parent_clk_name = "dpll4_ck",
|
2012-09-21 17:09:54 +08:00
|
|
|
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
|
2014-05-22 19:31:57 +08:00
|
|
|
.ports = omap34xx_ports,
|
|
|
|
.num_ports = ARRAY_SIZE(omap34xx_ports),
|
2012-09-21 17:03:31 +08:00
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static const struct dss_features omap3630_dss_feats = {
|
2012-09-21 17:03:31 +08:00
|
|
|
.fck_div_max = 32,
|
|
|
|
.dss_fck_multiplier = 1,
|
2013-10-31 22:06:38 +08:00
|
|
|
.parent_clk_name = "dpll4_ck",
|
2012-09-21 17:09:54 +08:00
|
|
|
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
|
2014-05-22 19:31:57 +08:00
|
|
|
.ports = omap2plus_ports,
|
|
|
|
.num_ports = ARRAY_SIZE(omap2plus_ports),
|
2012-09-21 17:03:31 +08:00
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static const struct dss_features omap44xx_dss_feats = {
|
2012-09-21 17:03:31 +08:00
|
|
|
.fck_div_max = 32,
|
|
|
|
.dss_fck_multiplier = 1,
|
2013-10-31 22:06:38 +08:00
|
|
|
.parent_clk_name = "dpll_per_x2_ck",
|
2012-09-21 17:09:54 +08:00
|
|
|
.dpi_select_source = &dss_dpi_select_source_omap4,
|
2014-05-22 19:31:57 +08:00
|
|
|
.ports = omap2plus_ports,
|
|
|
|
.num_ports = ARRAY_SIZE(omap2plus_ports),
|
2012-09-21 17:03:31 +08:00
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static const struct dss_features omap54xx_dss_feats = {
|
2012-09-21 17:03:31 +08:00
|
|
|
.fck_div_max = 64,
|
|
|
|
.dss_fck_multiplier = 1,
|
2013-10-31 22:06:38 +08:00
|
|
|
.parent_clk_name = "dpll_per_x2_ck",
|
2012-09-21 17:09:54 +08:00
|
|
|
.dpi_select_source = &dss_dpi_select_source_omap5,
|
2014-05-22 19:31:57 +08:00
|
|
|
.ports = omap2plus_ports,
|
|
|
|
.num_ports = ARRAY_SIZE(omap2plus_ports),
|
2012-09-21 17:03:31 +08:00
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static const struct dss_features am43xx_dss_feats = {
|
2014-03-24 19:01:51 +08:00
|
|
|
.fck_div_max = 0,
|
|
|
|
.dss_fck_multiplier = 0,
|
|
|
|
.parent_clk_name = NULL,
|
|
|
|
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
|
2014-05-22 19:31:57 +08:00
|
|
|
.ports = omap2plus_ports,
|
|
|
|
.num_ports = ARRAY_SIZE(omap2plus_ports),
|
2014-03-24 19:01:51 +08:00
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static const struct dss_features dra7xx_dss_feats = {
|
2014-12-31 17:23:31 +08:00
|
|
|
.fck_div_max = 64,
|
|
|
|
.dss_fck_multiplier = 1,
|
|
|
|
.parent_clk_name = "dpll_per_x2_ck",
|
|
|
|
.dpi_select_source = &dss_dpi_select_source_dra7xx,
|
|
|
|
.ports = dra7xx_ports,
|
|
|
|
.num_ports = ARRAY_SIZE(dra7xx_ports),
|
|
|
|
};
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static int dss_init_features(struct platform_device *pdev)
|
2012-07-11 21:06:18 +08:00
|
|
|
{
|
|
|
|
const struct dss_features *src;
|
|
|
|
struct dss_features *dst;
|
|
|
|
|
2012-09-28 17:56:00 +08:00
|
|
|
dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
|
2012-07-11 21:06:18 +08:00
|
|
|
if (!dst) {
|
2012-09-28 17:56:00 +08:00
|
|
|
dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
|
2012-07-11 21:06:18 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2012-10-18 18:46:29 +08:00
|
|
|
switch (omapdss_get_version()) {
|
2012-09-28 17:56:00 +08:00
|
|
|
case OMAPDSS_VER_OMAP24xx:
|
2012-07-11 21:06:18 +08:00
|
|
|
src = &omap24xx_dss_feats;
|
2012-09-28 17:56:00 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OMAPDSS_VER_OMAP34xx_ES1:
|
|
|
|
case OMAPDSS_VER_OMAP34xx_ES3:
|
|
|
|
case OMAPDSS_VER_AM35xx:
|
2012-07-11 21:06:18 +08:00
|
|
|
src = &omap34xx_dss_feats;
|
2012-09-28 17:56:00 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OMAPDSS_VER_OMAP3630:
|
2012-07-11 21:06:18 +08:00
|
|
|
src = &omap3630_dss_feats;
|
2012-09-28 17:56:00 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OMAPDSS_VER_OMAP4430_ES1:
|
|
|
|
case OMAPDSS_VER_OMAP4430_ES2:
|
|
|
|
case OMAPDSS_VER_OMAP4:
|
2012-07-11 21:06:18 +08:00
|
|
|
src = &omap44xx_dss_feats;
|
2012-09-28 17:56:00 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OMAPDSS_VER_OMAP5:
|
2012-04-08 19:17:01 +08:00
|
|
|
src = &omap54xx_dss_feats;
|
2012-09-28 17:56:00 +08:00
|
|
|
break;
|
|
|
|
|
2014-03-24 19:01:51 +08:00
|
|
|
case OMAPDSS_VER_AM43xx:
|
|
|
|
src = &am43xx_dss_feats;
|
|
|
|
break;
|
|
|
|
|
2014-12-31 17:23:31 +08:00
|
|
|
case OMAPDSS_VER_DRA7xx:
|
|
|
|
src = &dra7xx_dss_feats;
|
|
|
|
break;
|
|
|
|
|
2012-09-28 17:56:00 +08:00
|
|
|
default:
|
2012-07-11 21:06:18 +08:00
|
|
|
return -ENODEV;
|
2012-09-28 17:56:00 +08:00
|
|
|
}
|
2012-07-11 21:06:18 +08:00
|
|
|
|
|
|
|
memcpy(dst, src, sizeof(*dst));
|
|
|
|
dss.feat = dst;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static int dss_init_ports(struct platform_device *pdev)
|
2013-12-16 21:13:24 +08:00
|
|
|
{
|
|
|
|
struct device_node *parent = pdev->dev.of_node;
|
|
|
|
struct device_node *port;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (parent == NULL)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
port = omapdss_of_get_next_port(parent, NULL);
|
2014-05-08 17:15:12 +08:00
|
|
|
if (!port)
|
2013-12-16 21:13:24 +08:00
|
|
|
return 0;
|
|
|
|
|
2014-05-22 19:31:57 +08:00
|
|
|
if (dss.feat->num_ports == 0)
|
|
|
|
return 0;
|
|
|
|
|
2013-12-16 21:13:24 +08:00
|
|
|
do {
|
2014-05-22 19:31:57 +08:00
|
|
|
enum omap_display_type port_type;
|
2013-12-16 21:13:24 +08:00
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
r = of_property_read_u32(port, "reg", ®);
|
|
|
|
if (r)
|
|
|
|
reg = 0;
|
|
|
|
|
2014-05-22 19:31:57 +08:00
|
|
|
if (reg >= dss.feat->num_ports)
|
|
|
|
continue;
|
2013-12-16 21:13:24 +08:00
|
|
|
|
2014-05-22 19:31:57 +08:00
|
|
|
port_type = dss.feat->ports[reg];
|
2013-12-16 21:13:24 +08:00
|
|
|
|
2014-05-22 19:31:57 +08:00
|
|
|
switch (port_type) {
|
|
|
|
case OMAP_DISPLAY_TYPE_DPI:
|
|
|
|
dpi_init_port(pdev, port);
|
|
|
|
break;
|
|
|
|
case OMAP_DISPLAY_TYPE_SDI:
|
|
|
|
sdi_init_port(pdev, port);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2013-12-16 21:13:24 +08:00
|
|
|
} while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-06-04 19:12:16 +08:00
|
|
|
static void dss_uninit_ports(struct platform_device *pdev)
|
2013-12-16 21:13:24 +08:00
|
|
|
{
|
2014-06-02 16:41:51 +08:00
|
|
|
struct device_node *parent = pdev->dev.of_node;
|
|
|
|
struct device_node *port;
|
|
|
|
|
|
|
|
if (parent == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
port = omapdss_of_get_next_port(parent, NULL);
|
|
|
|
if (!port)
|
|
|
|
return;
|
|
|
|
|
2014-05-22 19:31:57 +08:00
|
|
|
if (dss.feat->num_ports == 0)
|
|
|
|
return;
|
2013-12-16 21:13:24 +08:00
|
|
|
|
2014-05-22 19:31:57 +08:00
|
|
|
do {
|
|
|
|
enum omap_display_type port_type;
|
|
|
|
u32 reg;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
r = of_property_read_u32(port, "reg", ®);
|
|
|
|
if (r)
|
|
|
|
reg = 0;
|
|
|
|
|
|
|
|
if (reg >= dss.feat->num_ports)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
port_type = dss.feat->ports[reg];
|
|
|
|
|
|
|
|
switch (port_type) {
|
|
|
|
case OMAP_DISPLAY_TYPE_DPI:
|
|
|
|
dpi_uninit_port(port);
|
|
|
|
break;
|
|
|
|
case OMAP_DISPLAY_TYPE_SDI:
|
|
|
|
sdi_uninit_port(port);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
|
2013-12-16 21:13:24 +08:00
|
|
|
}
|
|
|
|
|
2015-06-04 18:02:52 +08:00
|
|
|
static int dss_video_pll_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct regulator *pll_regulator;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (!np)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (of_property_read_bool(np, "syscon-pll-ctrl")) {
|
|
|
|
dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
|
|
|
|
"syscon-pll-ctrl");
|
|
|
|
if (IS_ERR(dss.syscon_pll_ctrl)) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"failed to get syscon-pll-ctrl regmap\n");
|
|
|
|
return PTR_ERR(dss.syscon_pll_ctrl);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
|
|
|
|
&dss.syscon_pll_ctrl_offset)) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"failed to get syscon-pll-ctrl offset\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
|
|
|
|
if (IS_ERR(pll_regulator)) {
|
|
|
|
r = PTR_ERR(pll_regulator);
|
|
|
|
|
|
|
|
switch (r) {
|
|
|
|
case -ENOENT:
|
|
|
|
pll_regulator = NULL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case -EPROBE_DEFER:
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
|
|
|
default:
|
|
|
|
DSSERR("can't get DPLL VDDA regulator\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
|
|
|
|
dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
|
|
|
|
if (IS_ERR(dss.video1_pll))
|
|
|
|
return PTR_ERR(dss.video1_pll);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
|
|
|
|
dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
|
|
|
|
if (IS_ERR(dss.video2_pll)) {
|
|
|
|
dss_video_pll_uninit(dss.video1_pll);
|
|
|
|
return PTR_ERR(dss.video2_pll);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-24 14:21:57 +08:00
|
|
|
/* DSS HW IP initialisation */
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
static int dss_bind(struct device *dev)
|
2011-01-24 14:21:57 +08:00
|
|
|
{
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2011-05-16 18:52:51 +08:00
|
|
|
struct resource *dss_mem;
|
|
|
|
u32 rev;
|
2011-01-24 14:21:57 +08:00
|
|
|
int r;
|
|
|
|
|
|
|
|
dss.pdev = pdev;
|
|
|
|
|
2012-09-28 17:56:00 +08:00
|
|
|
r = dss_init_features(dss.pdev);
|
2012-07-11 21:06:18 +08:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2011-05-16 18:52:51 +08:00
|
|
|
dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!dss_mem) {
|
|
|
|
DSSERR("can't get IORESOURCE_MEM DSS\n");
|
2012-01-25 19:31:04 +08:00
|
|
|
return -EINVAL;
|
2011-05-16 18:52:51 +08:00
|
|
|
}
|
2012-01-25 19:31:04 +08:00
|
|
|
|
2012-01-24 21:00:45 +08:00
|
|
|
dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
|
|
|
|
resource_size(dss_mem));
|
2011-05-16 18:52:51 +08:00
|
|
|
if (!dss.base) {
|
|
|
|
DSSERR("can't ioremap DSS\n");
|
2012-01-25 19:31:04 +08:00
|
|
|
return -ENOMEM;
|
2011-05-16 18:52:51 +08:00
|
|
|
}
|
|
|
|
|
2011-01-24 14:21:58 +08:00
|
|
|
r = dss_get_clocks();
|
|
|
|
if (r)
|
2012-01-25 19:31:04 +08:00
|
|
|
return r;
|
2011-01-24 14:21:58 +08:00
|
|
|
|
2012-10-22 21:35:41 +08:00
|
|
|
r = dss_setup_default_clock();
|
|
|
|
if (r)
|
|
|
|
goto err_setup_clocks;
|
|
|
|
|
2015-06-04 18:02:52 +08:00
|
|
|
r = dss_video_pll_probe(pdev);
|
|
|
|
if (r)
|
|
|
|
goto err_pll_init;
|
|
|
|
|
2015-06-04 18:06:37 +08:00
|
|
|
r = dss_init_ports(pdev);
|
|
|
|
if (r)
|
|
|
|
goto err_init_ports;
|
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
2011-05-16 18:52:51 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
r = dss_runtime_get();
|
|
|
|
if (r)
|
|
|
|
goto err_runtime_get;
|
2011-05-16 18:52:51 +08:00
|
|
|
|
2012-12-12 16:37:03 +08:00
|
|
|
dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
|
|
|
|
|
2011-05-16 18:52:51 +08:00
|
|
|
/* Select DPLL */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
|
|
|
|
|
2016-05-17 19:01:10 +08:00
|
|
|
dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
|
OMAPDSS: hide dss_select_dispc_clk_source()
dss.c currently exposes functions to configure the dispc source clock
and lcd source clock. There are configured separately from the output
drivers.
However, there is no safe way for the output drivers to handle dispc
clock, as it's shared between the outputs. Thus, if, say, the DSI driver
sets up DSI PLL and configures both the dispc and lcd clock sources to
that DSI PLL, the resulting dispc clock could be too low for, say, HDMI.
Thus the output drivers should really only be concerned about the lcd
clock, which is what the output drivers actually use. There's lot to do
to clean up the dss clock handling, but this patch takes one step
forward and removes the use of dss_select_dispc_clk_source() from the
output drivers.
After this patch, the output drivers only configure the lcd source
clock. On omap4+ the dispc src clock is never changed from the default
PRCM source. On omap3, where the dispc and lcd clocks are actually the
same, setting the lcd clock source sets the dispc clock source.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-22 21:58:36 +08:00
|
|
|
|
2011-05-16 18:52:51 +08:00
|
|
|
#ifdef CONFIG_OMAP2_DSS_VENC
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
|
|
|
|
#endif
|
2016-05-17 19:01:10 +08:00
|
|
|
dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK;
|
|
|
|
dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK;
|
|
|
|
dss.dispc_clk_source = DSS_CLK_SRC_FCK;
|
|
|
|
dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
|
|
|
|
dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
|
2011-01-24 14:21:57 +08:00
|
|
|
|
2011-05-16 18:52:51 +08:00
|
|
|
rev = dss_read_reg(DSS_REVISION);
|
|
|
|
printk(KERN_INFO "OMAP DSS rev %d.%d\n",
|
|
|
|
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
|
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
dss_runtime_put();
|
2011-05-16 18:52:51 +08:00
|
|
|
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
r = component_bind_all(&pdev->dev, NULL);
|
|
|
|
if (r)
|
|
|
|
goto err_component;
|
|
|
|
|
2012-03-03 00:01:07 +08:00
|
|
|
dss_debugfs_create_file("dss", dss_dump_regs);
|
|
|
|
|
2015-02-25 18:08:14 +08:00
|
|
|
pm_set_vt_switch(0);
|
|
|
|
|
2015-06-04 17:35:42 +08:00
|
|
|
dss_initialized = true;
|
|
|
|
|
2011-01-24 14:21:58 +08:00
|
|
|
return 0;
|
2012-02-20 22:57:37 +08:00
|
|
|
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
err_component:
|
2015-06-04 18:02:52 +08:00
|
|
|
err_runtime_get:
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2015-06-04 18:06:37 +08:00
|
|
|
dss_uninit_ports(pdev);
|
|
|
|
err_init_ports:
|
2014-07-04 16:08:27 +08:00
|
|
|
if (dss.video1_pll)
|
|
|
|
dss_video_pll_uninit(dss.video1_pll);
|
|
|
|
|
|
|
|
if (dss.video2_pll)
|
|
|
|
dss_video_pll_uninit(dss.video2_pll);
|
2015-06-04 18:02:52 +08:00
|
|
|
err_pll_init:
|
2012-10-22 21:35:41 +08:00
|
|
|
err_setup_clocks:
|
2011-01-24 14:21:58 +08:00
|
|
|
dss_put_clocks();
|
2011-01-24 14:21:57 +08:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
static void dss_unbind(struct device *dev)
|
2011-01-24 14:21:57 +08:00
|
|
|
{
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
|
2015-06-04 17:35:42 +08:00
|
|
|
dss_initialized = false;
|
|
|
|
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
component_unbind_all(&pdev->dev, NULL);
|
|
|
|
|
2014-07-04 16:08:27 +08:00
|
|
|
if (dss.video1_pll)
|
|
|
|
dss_video_pll_uninit(dss.video1_pll);
|
|
|
|
|
|
|
|
if (dss.video2_pll)
|
|
|
|
dss_video_pll_uninit(dss.video2_pll);
|
|
|
|
|
2014-06-01 15:17:44 +08:00
|
|
|
dss_uninit_ports(pdev);
|
2013-12-16 21:13:24 +08:00
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
2011-01-24 14:21:58 +08:00
|
|
|
|
|
|
|
dss_put_clocks();
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct component_master_ops dss_component_ops = {
|
|
|
|
.bind = dss_bind,
|
|
|
|
.unbind = dss_unbind,
|
|
|
|
};
|
2011-05-16 18:52:51 +08:00
|
|
|
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
static int dss_component_compare(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
struct device *child = data;
|
|
|
|
return dev == child;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dss_add_child_component(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
struct component_match **match = data;
|
|
|
|
|
2015-06-30 17:23:45 +08:00
|
|
|
/*
|
|
|
|
* HACK
|
|
|
|
* We don't have a working driver for rfbi, so skip it here always.
|
|
|
|
* Otherwise dss will never get probed successfully, as it will wait
|
|
|
|
* for rfbi to get probed.
|
|
|
|
*/
|
|
|
|
if (strstr(dev_name(dev), "rfbi"))
|
|
|
|
return 0;
|
|
|
|
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
component_match_add(dev->parent, match, dss_component_compare, dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dss_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct component_match *match = NULL;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
/* add all the child devices as components */
|
|
|
|
device_for_each_child(&pdev->dev, &match, dss_add_child_component);
|
|
|
|
|
|
|
|
r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dss_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
component_master_del(&pdev->dev, &dss_component_ops);
|
2011-01-24 14:21:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
static int dss_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
dss_save_context();
|
2012-03-08 18:52:38 +08:00
|
|
|
dss_set_min_bus_tput(dev, 0);
|
2014-11-01 05:28:57 +08:00
|
|
|
|
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
2011-05-27 15:52:19 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dss_runtime_resume(struct device *dev)
|
|
|
|
{
|
2012-03-08 18:52:38 +08:00
|
|
|
int r;
|
2014-11-01 05:28:57 +08:00
|
|
|
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
|
2012-03-08 18:52:38 +08:00
|
|
|
/*
|
|
|
|
* Set an arbitrarily high tput request to ensure OPP100.
|
|
|
|
* What we should really do is to make a request to stay in OPP100,
|
|
|
|
* without any tput requirements, but that is not currently possible
|
|
|
|
* via the PM layer.
|
|
|
|
*/
|
|
|
|
|
|
|
|
r = dss_set_min_bus_tput(dev, 1000000000);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2011-05-26 19:54:05 +08:00
|
|
|
dss_restore_context();
|
2011-05-27 15:52:19 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dev_pm_ops dss_pm_ops = {
|
|
|
|
.runtime_suspend = dss_runtime_suspend,
|
|
|
|
.runtime_resume = dss_runtime_resume,
|
|
|
|
};
|
|
|
|
|
2013-12-16 21:13:24 +08:00
|
|
|
static const struct of_device_id dss_of_match[] = {
|
|
|
|
{ .compatible = "ti,omap2-dss", },
|
|
|
|
{ .compatible = "ti,omap3-dss", },
|
|
|
|
{ .compatible = "ti,omap4-dss", },
|
2014-04-16 18:16:43 +08:00
|
|
|
{ .compatible = "ti,omap5-dss", },
|
2014-12-31 17:23:31 +08:00
|
|
|
{ .compatible = "ti,dra7-dss", },
|
2013-12-16 21:13:24 +08:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(of, dss_of_match);
|
|
|
|
|
2011-01-24 14:21:57 +08:00
|
|
|
static struct platform_driver omap_dsshw_driver = {
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
|
|
|
.probe = dss_probe,
|
|
|
|
.remove = dss_remove,
|
2011-01-24 14:21:57 +08:00
|
|
|
.driver = {
|
|
|
|
.name = "omapdss_dss",
|
2011-05-27 15:52:19 +08:00
|
|
|
.pm = &dss_pm_ops,
|
2013-12-16 21:13:24 +08:00
|
|
|
.of_match_table = dss_of_match,
|
2014-10-16 14:54:25 +08:00
|
|
|
.suppress_bind_attrs = true,
|
2011-01-24 14:21:57 +08:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-02-17 23:41:13 +08:00
|
|
|
int __init dss_init_platform_driver(void)
|
2011-01-24 14:21:57 +08:00
|
|
|
{
|
OMAPDSS: componentize omapdss
omapdss kernel module contains drivers for multiple devices, one for
each DSS submodule. The probing we have at the moment is a mess, and
doesn't give us proper deferred probing nor ensure that all the devices
are probed before omapfb/omapdrm start using omapdss.
This patch solves the mess by using the component system for DSS
submodules.
The changes to all DSS submodules (dispc, dpi, dsi, hdmi4/5, rfbi, sdi,
venc) are the same: probe & remove functions are changed to bind &
unbind, and new probe & remove functions are added which call
component_add/del.
The dss_core driver (dss.c) acts as a component master. Adding and
matching the components is simple: all dss device's child devices are
added as components.
However, we do have some dependencies between the drivers. The order in
which they should be probed is reflected by the list in core.c
(dss_output_drv_reg_funcs). The drivers are registered in that order,
which causes the components to be added in that order, which makes the
components to be bound in that order. This feels a bit fragile, and we
probably should improve the code to manage binds in random order.
However, for now, this works fine.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-06-04 20:22:23 +08:00
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return platform_driver_register(&omap_dsshw_driver);
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2011-01-24 14:21:57 +08:00
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}
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void dss_uninit_platform_driver(void)
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{
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2012-02-23 21:32:37 +08:00
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platform_driver_unregister(&omap_dsshw_driver);
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2011-01-24 14:21:57 +08:00
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}
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