2019-05-27 14:55:01 +08:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2005-10-10 20:36:14 +08:00
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains the system call entry code, context switch
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* code, and exception/interrupt return code for PowerPC.
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*/
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#include <linux/errno.h>
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powerpc/kernel: Switch to using MAX_ERRNO
Currently on powerpc we have our own #define for the highest (negative)
errno value, called _LAST_ERRNO. This is defined to be 516, for reasons
which are not clear.
The generic code, and x86, use MAX_ERRNO, which is defined to be 4095.
In particular seccomp uses MAX_ERRNO to restrict the value that a
seccomp filter can return.
Currently with the mismatch between _LAST_ERRNO and MAX_ERRNO, a seccomp
tracer wanting to return 600, expecting it to be seen as an error, would
instead find on powerpc that userspace sees a successful syscall with a
return value of 600.
To avoid this inconsistency, switch powerpc to use MAX_ERRNO.
We are somewhat confident that generic syscalls that can return a
non-error value above negative MAX_ERRNO have already been updated to
use force_successful_syscall_return().
I have also checked all the powerpc specific syscalls, and believe that
none of them expect to return a non-error value between -MAX_ERRNO and
-516. So this change should be safe ...
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Kees Cook <keescook@chromium.org>
2015-07-23 18:21:01 +08:00
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#include <linux/err.h>
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2005-10-10 20:36:14 +08:00
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#include <linux/sys.h>
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#include <linux/threads.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/unistd.h>
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2010-11-18 23:06:17 +08:00
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#include <asm/ptrace.h>
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2016-01-14 12:33:46 +08:00
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#include <asm/export.h>
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2018-07-06 00:25:01 +08:00
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#include <asm/feature-fixups.h>
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2018-07-28 07:06:38 +08:00
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#include <asm/barrier.h>
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2019-03-11 16:30:31 +08:00
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#include <asm/kup.h>
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2019-04-30 20:39:01 +08:00
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#include <asm/bug.h>
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2021-06-04 22:54:14 +08:00
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#include <asm/interrupt.h>
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2005-10-10 20:36:14 +08:00
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2019-04-30 20:38:51 +08:00
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#include "head_32.h"
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2005-10-10 20:36:14 +08:00
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2020-07-16 09:35:22 +08:00
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/*
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* powerpc relies on return from interrupt/syscall being context synchronising
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* (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
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* synchronisation instructions.
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*/
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2017-07-12 18:08:49 +08:00
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/*
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* Align to 4k in order to ensure that all functions modyfing srr0/srr1
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* fit into one page in order to not encounter a TLB miss between the
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* modification of srr0/srr1 and the associated rfi.
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*/
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.align 12
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2021-03-12 20:50:46 +08:00
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#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
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2021-03-12 20:50:39 +08:00
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.globl prepare_transfer_to_handler
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prepare_transfer_to_handler:
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2021-03-12 20:50:21 +08:00
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/* if from kernel, check interrupted DOZE/NAP mode */
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2019-01-31 18:09:04 +08:00
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lwz r12,TI_LOCAL_FLAGS(r2)
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2006-04-18 19:49:11 +08:00
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mtcrf 0x01,r12
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bt- 31-TLF_NAPPING,4f
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2008-05-14 12:30:48 +08:00
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bt- 31-TLF_SLEEPING,7f
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2021-03-12 20:50:32 +08:00
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blr
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2019-04-30 20:39:01 +08:00
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2020-04-01 00:03:45 +08:00
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4: rlwinm r12,r12,0,~_TLF_NAPPING
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stw r12,TI_LOCAL_FLAGS(r2)
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b power_save_ppc32_restore
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7: rlwinm r12,r12,0,~_TLF_SLEEPING
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stw r12,TI_LOCAL_FLAGS(r2)
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lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
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rlwinm r9,r9,0,~MSR_EE
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lwz r12,_LINK(r11) /* and return to address in LR */
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lwz r2, GPR2(r11)
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b fast_exception_return
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2021-03-12 20:50:39 +08:00
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_ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler)
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2021-03-12 20:50:46 +08:00
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#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
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2020-04-01 00:03:45 +08:00
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powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly
When interrupt and syscall entries where converted to C, KUEP locking
and unlocking was also converted. It improved performance by unrolling
the loop, and allowed easily implementing boot time deactivation of
KUEP.
However, null_syscall selftest shows that KUEP is still heavy
(361 cycles with KUEP, 212 cycles without).
A way to improve more is to group 'mtsr's together, instead of
repeating 'addi' + 'mtsr' several times.
In order to do that, more registers need to be available. In C, GCC
will always be able to provide the requested number of registers, but
at the cost of saving some data on the stack, which is counter
performant here.
So let's do it in assembly, when we have full control of which
register can be used. It also has the advantage of locking earlier
and unlocking later and it helps GCC generating less tricky code.
The only drawback is to make boot time deactivation less straight
forward and require 'hand' instruction patching.
Group 'mtsr's by 4.
With this change, null_syscall selftest reports 336 cycles. Without
the change it was 361 cycles, that's a 7% reduction.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/115cb279e9b9948dfd93a065e047081c59e3a2a6.1634627931.git.christophe.leroy@csgroup.eu
2021-10-19 15:29:17 +08:00
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#if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32)
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.globl __kuep_lock
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__kuep_lock:
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2021-10-19 15:29:18 +08:00
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lwz r9, THREAD+THSR0(r2)
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powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly
When interrupt and syscall entries where converted to C, KUEP locking
and unlocking was also converted. It improved performance by unrolling
the loop, and allowed easily implementing boot time deactivation of
KUEP.
However, null_syscall selftest shows that KUEP is still heavy
(361 cycles with KUEP, 212 cycles without).
A way to improve more is to group 'mtsr's together, instead of
repeating 'addi' + 'mtsr' several times.
In order to do that, more registers need to be available. In C, GCC
will always be able to provide the requested number of registers, but
at the cost of saving some data on the stack, which is counter
performant here.
So let's do it in assembly, when we have full control of which
register can be used. It also has the advantage of locking earlier
and unlocking later and it helps GCC generating less tricky code.
The only drawback is to make boot time deactivation less straight
forward and require 'hand' instruction patching.
Group 'mtsr's by 4.
With this change, null_syscall selftest reports 336 cycles. Without
the change it was 361 cycles, that's a 7% reduction.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/115cb279e9b9948dfd93a065e047081c59e3a2a6.1634627931.git.christophe.leroy@csgroup.eu
2021-10-19 15:29:17 +08:00
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update_user_segments_by_4 r9, r10, r11, r12
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blr
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__kuep_unlock:
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2021-10-19 15:29:18 +08:00
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lwz r9, THREAD+THSR0(r2)
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rlwinm r9,r9,0,~SR_NX
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powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly
When interrupt and syscall entries where converted to C, KUEP locking
and unlocking was also converted. It improved performance by unrolling
the loop, and allowed easily implementing boot time deactivation of
KUEP.
However, null_syscall selftest shows that KUEP is still heavy
(361 cycles with KUEP, 212 cycles without).
A way to improve more is to group 'mtsr's together, instead of
repeating 'addi' + 'mtsr' several times.
In order to do that, more registers need to be available. In C, GCC
will always be able to provide the requested number of registers, but
at the cost of saving some data on the stack, which is counter
performant here.
So let's do it in assembly, when we have full control of which
register can be used. It also has the advantage of locking earlier
and unlocking later and it helps GCC generating less tricky code.
The only drawback is to make boot time deactivation less straight
forward and require 'hand' instruction patching.
Group 'mtsr's by 4.
With this change, null_syscall selftest reports 336 cycles. Without
the change it was 361 cycles, that's a 7% reduction.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/115cb279e9b9948dfd93a065e047081c59e3a2a6.1634627931.git.christophe.leroy@csgroup.eu
2021-10-19 15:29:17 +08:00
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update_user_segments_by_4 r9, r10, r11, r12
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blr
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.macro kuep_lock
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bl __kuep_lock
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.endm
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.macro kuep_unlock
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bl __kuep_unlock
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.endm
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#else
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.macro kuep_lock
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.endm
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.macro kuep_unlock
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.endm
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#endif
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2019-04-30 20:39:02 +08:00
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.globl transfer_to_syscall
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transfer_to_syscall:
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2021-06-04 22:54:14 +08:00
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stw r11, GPR1(r1)
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stw r11, 0(r1)
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mflr r12
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stw r12, _LINK(r1)
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2021-10-19 15:29:25 +08:00
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#ifdef CONFIG_BOOKE_OR_40x
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2021-06-04 22:54:14 +08:00
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rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
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#endif
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lis r12,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
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SAVE_GPR(2, r1)
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addi r12,r12,STACK_FRAME_REGS_MARKER@l
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stw r9,_MSR(r1)
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li r2, INTERRUPT_SYSCALL
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stw r12,8(r1)
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stw r2,_TRAP(r1)
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SAVE_GPR(0, r1)
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2021-10-22 14:13:22 +08:00
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SAVE_GPRS(3, 8, r1)
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2021-06-04 22:54:14 +08:00
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addi r2,r10,-THREAD
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2021-02-08 23:10:32 +08:00
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SAVE_NVGPRS(r1)
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powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly
When interrupt and syscall entries where converted to C, KUEP locking
and unlocking was also converted. It improved performance by unrolling
the loop, and allowed easily implementing boot time deactivation of
KUEP.
However, null_syscall selftest shows that KUEP is still heavy
(361 cycles with KUEP, 212 cycles without).
A way to improve more is to group 'mtsr's together, instead of
repeating 'addi' + 'mtsr' several times.
In order to do that, more registers need to be available. In C, GCC
will always be able to provide the requested number of registers, but
at the cost of saving some data on the stack, which is counter
performant here.
So let's do it in assembly, when we have full control of which
register can be used. It also has the advantage of locking earlier
and unlocking later and it helps GCC generating less tricky code.
The only drawback is to make boot time deactivation less straight
forward and require 'hand' instruction patching.
Group 'mtsr's by 4.
With this change, null_syscall selftest reports 336 cycles. Without
the change it was 361 cycles, that's a 7% reduction.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/115cb279e9b9948dfd93a065e047081c59e3a2a6.1634627931.git.christophe.leroy@csgroup.eu
2021-10-19 15:29:17 +08:00
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kuep_lock
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2019-04-30 20:39:02 +08:00
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2021-02-08 23:10:33 +08:00
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/* Calling convention has r9 = orig r0, r10 = regs */
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addi r10,r1,STACK_FRAME_OVERHEAD
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mr r9,r0
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bl system_call_exception
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2018-07-28 07:06:38 +08:00
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2005-10-10 20:36:14 +08:00
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ret_from_syscall:
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2021-02-08 23:10:33 +08:00
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addi r4,r1,STACK_FRAME_OVERHEAD
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li r5,0
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bl syscall_exit_prepare
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2020-10-19 01:25:18 +08:00
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#ifdef CONFIG_PPC_47x
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2007-10-31 13:42:19 +08:00
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lis r4,icache_44x_need_flush@ha
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lwz r5,icache_44x_need_flush@l(r4)
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cmplwi cr0,r5,0
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bne- 2f
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2020-10-19 01:25:18 +08:00
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#endif /* CONFIG_PPC_47x */
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powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly
When interrupt and syscall entries where converted to C, KUEP locking
and unlocking was also converted. It improved performance by unrolling
the loop, and allowed easily implementing boot time deactivation of
KUEP.
However, null_syscall selftest shows that KUEP is still heavy
(361 cycles with KUEP, 212 cycles without).
A way to improve more is to group 'mtsr's together, instead of
repeating 'addi' + 'mtsr' several times.
In order to do that, more registers need to be available. In C, GCC
will always be able to provide the requested number of registers, but
at the cost of saving some data on the stack, which is counter
performant here.
So let's do it in assembly, when we have full control of which
register can be used. It also has the advantage of locking earlier
and unlocking later and it helps GCC generating less tricky code.
The only drawback is to make boot time deactivation less straight
forward and require 'hand' instruction patching.
Group 'mtsr's by 4.
With this change, null_syscall selftest reports 336 cycles. Without
the change it was 361 cycles, that's a 7% reduction.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/115cb279e9b9948dfd93a065e047081c59e3a2a6.1634627931.git.christophe.leroy@csgroup.eu
2021-10-19 15:29:17 +08:00
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kuep_unlock
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2005-10-10 20:36:14 +08:00
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lwz r4,_LINK(r1)
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lwz r5,_CCR(r1)
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mtlr r4
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lwz r7,_NIP(r1)
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2021-02-08 23:10:33 +08:00
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lwz r8,_MSR(r1)
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cmpwi r3,0
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lwz r3,GPR3(r1)
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2020-04-01 00:03:46 +08:00
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syscall_exit_finish:
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2005-10-10 20:36:14 +08:00
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mtspr SPRN_SRR0,r7
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mtspr SPRN_SRR1,r8
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2021-02-08 23:10:33 +08:00
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bne 3f
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mtcr r5
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1: lwz r2,GPR2(r1)
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lwz r1,GPR1(r1)
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2020-11-09 00:57:37 +08:00
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rfi
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#ifdef CONFIG_40x
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b . /* Prevent prefetch past rfi */
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#endif
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2021-02-08 23:10:33 +08:00
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3: mtcr r5
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lwz r4,_CTR(r1)
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lwz r5,_XER(r1)
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REST_NVGPRS(r1)
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mtctr r4
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mtxer r5
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lwz r0,GPR0(r1)
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lwz r3,GPR3(r1)
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2021-10-22 14:13:22 +08:00
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REST_GPRS(4, 11, r1)
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2021-02-08 23:10:33 +08:00
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lwz r12,GPR12(r1)
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b 1b
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2007-10-31 13:42:19 +08:00
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#ifdef CONFIG_44x
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2: li r7,0
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iccci r0,r0
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stw r7,icache_44x_need_flush@l(r4)
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b 1b
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#endif /* CONFIG_44x */
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2005-10-10 20:36:14 +08:00
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.globl ret_from_fork
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ret_from_fork:
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REST_NVGPRS(r1)
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bl schedule_tail
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li r3,0
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b ret_from_syscall
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2012-09-13 06:32:42 +08:00
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.globl ret_from_kernel_thread
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|
|
ret_from_kernel_thread:
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
bl schedule_tail
|
2021-08-20 13:16:05 +08:00
|
|
|
mtctr r14
|
2012-09-13 06:32:42 +08:00
|
|
|
mr r3,r15
|
|
|
|
|
PPC440EP_ERR42
|
2021-08-20 13:16:05 +08:00
|
|
|
bctrl
|
2012-09-13 06:32:42 +08:00
|
|
|
li r3,0
|
2012-09-01 03:48:05 +08:00
|
|
|
b ret_from_syscall
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This routine switches between two different tasks. The process
|
|
|
|
|
* state of one is saved on its kernel stack. Then the state
|
|
|
|
|
* of the other is restored from its kernel stack. The memory
|
|
|
|
|
* management hardware is updated to the second process's state.
|
|
|
|
|
* Finally, we can return to the second process.
|
|
|
|
|
* On entry, r3 points to the THREAD for the current task, r4
|
|
|
|
|
* points to the THREAD for the new task.
|
|
|
|
|
*
|
|
|
|
|
* This routine is always called with interrupts disabled.
|
|
|
|
|
*
|
|
|
|
|
* Note: there are two ways to get to the "going out" portion
|
|
|
|
|
* of this code; either by coming in via the entry (_switch)
|
|
|
|
|
* or via "fork" which must set up an environment equivalent
|
|
|
|
|
* to the "_switch" path. If you change this , you'll have to
|
|
|
|
|
* change the fork code also.
|
|
|
|
|
*
|
|
|
|
|
* The code which creates the new task context is in 'copy_thread'
|
|
|
|
|
* in arch/ppc/kernel/process.c
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(_switch)
|
|
|
|
|
stwu r1,-INT_FRAME_SIZE(r1)
|
|
|
|
|
mflr r0
|
|
|
|
|
stw r0,INT_FRAME_SIZE+4(r1)
|
|
|
|
|
/* r3-r12 are caller saved -- Cort */
|
|
|
|
|
SAVE_NVGPRS(r1)
|
|
|
|
|
stw r0,_NIP(r1) /* Return to switch caller */
|
|
|
|
|
mfcr r10
|
|
|
|
|
stw r10,_CCR(r1)
|
|
|
|
|
stw r1,KSP(r3) /* Set old stack pointer */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
/* We need a sync somewhere here to make sure that if the
|
|
|
|
|
* previous task gets rescheduled on another CPU, it sees all
|
|
|
|
|
* stores it has performed on this one.
|
|
|
|
|
*/
|
|
|
|
|
sync
|
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
|
|
tophys(r0,r4)
|
2009-07-15 04:52:54 +08:00
|
|
|
mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
|
2005-10-10 20:36:14 +08:00
|
|
|
lwz r1,KSP(r4) /* Load new stack pointer */
|
|
|
|
|
|
|
|
|
|
/* save the old current 'last' for return value */
|
|
|
|
|
mr r3,r2
|
|
|
|
|
addi r2,r4,-THREAD /* Update current */
|
|
|
|
|
|
|
|
|
|
lwz r0,_CCR(r1)
|
|
|
|
|
mtcrf 0xFF,r0
|
|
|
|
|
/* r3-r12 are destroyed -- Cort */
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
|
|
|
|
|
lwz r4,_NIP(r1) /* Return to _switch caller in new task */
|
|
|
|
|
mtlr r4
|
|
|
|
|
addi r1,r1,INT_FRAME_SIZE
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl fast_exception_return
|
|
|
|
|
fast_exception_return:
|
|
|
|
|
#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
|
|
|
|
|
andi. r10,r9,MSR_RI /* check for recoverable interrupt */
|
2021-03-12 20:50:34 +08:00
|
|
|
beq 3f /* if not, we've got problems */
|
2005-10-10 20:36:14 +08:00
|
|
|
#endif
|
|
|
|
|
|
2021-10-22 14:13:22 +08:00
|
|
|
2: REST_GPRS(3, 6, r11)
|
2005-10-10 20:36:14 +08:00
|
|
|
lwz r10,_CCR(r11)
|
2021-10-22 14:13:22 +08:00
|
|
|
REST_GPRS(1, 2, r11)
|
2005-10-10 20:36:14 +08:00
|
|
|
mtcr r10
|
|
|
|
|
lwz r10,_LINK(r11)
|
|
|
|
|
mtlr r10
|
2019-02-27 19:45:30 +08:00
|
|
|
/* Clear the exception_marker on the stack to avoid confusing stacktrace */
|
|
|
|
|
li r10, 0
|
|
|
|
|
stw r10, 8(r11)
|
2005-10-10 20:36:14 +08:00
|
|
|
REST_GPR(10, r11)
|
2018-01-12 20:45:23 +08:00
|
|
|
#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
mtspr SPRN_NRI, r0
|
|
|
|
|
#endif
|
2005-10-10 20:36:14 +08:00
|
|
|
mtspr SPRN_SRR1,r9
|
|
|
|
|
mtspr SPRN_SRR0,r12
|
|
|
|
|
REST_GPR(9, r11)
|
|
|
|
|
REST_GPR(12, r11)
|
|
|
|
|
lwz r11,GPR11(r11)
|
2020-11-09 00:57:37 +08:00
|
|
|
rfi
|
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
|
b . /* Prevent prefetch past rfi */
|
|
|
|
|
#endif
|
2020-04-01 00:03:47 +08:00
|
|
|
_ASM_NOKPROBE_SYMBOL(fast_exception_return)
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/* aargh, a nonrecoverable interrupt, panic */
|
|
|
|
|
/* aargh, we don't know which trap this is */
|
|
|
|
|
3:
|
|
|
|
|
li r10,-1
|
2005-10-28 20:45:25 +08:00
|
|
|
stw r10,_TRAP(r11)
|
2021-03-12 20:50:41 +08:00
|
|
|
prepare_transfer_to_handler
|
2021-03-12 20:50:32 +08:00
|
|
|
bl unrecoverable_exception
|
2021-03-12 20:50:34 +08:00
|
|
|
trap /* should not get here */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
.globl interrupt_return
|
|
|
|
|
interrupt_return:
|
|
|
|
|
lwz r4,_MSR(r1)
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
andi. r0,r4,MSR_PR
|
|
|
|
|
beq .Lkernel_interrupt_return
|
|
|
|
|
bl interrupt_exit_user_prepare
|
|
|
|
|
cmpwi r3,0
|
powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly
When interrupt and syscall entries where converted to C, KUEP locking
and unlocking was also converted. It improved performance by unrolling
the loop, and allowed easily implementing boot time deactivation of
KUEP.
However, null_syscall selftest shows that KUEP is still heavy
(361 cycles with KUEP, 212 cycles without).
A way to improve more is to group 'mtsr's together, instead of
repeating 'addi' + 'mtsr' several times.
In order to do that, more registers need to be available. In C, GCC
will always be able to provide the requested number of registers, but
at the cost of saving some data on the stack, which is counter
performant here.
So let's do it in assembly, when we have full control of which
register can be used. It also has the advantage of locking earlier
and unlocking later and it helps GCC generating less tricky code.
The only drawback is to make boot time deactivation less straight
forward and require 'hand' instruction patching.
Group 'mtsr's by 4.
With this change, null_syscall selftest reports 336 cycles. Without
the change it was 361 cycles, that's a 7% reduction.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/115cb279e9b9948dfd93a065e047081c59e3a2a6.1634627931.git.christophe.leroy@csgroup.eu
2021-10-19 15:29:17 +08:00
|
|
|
kuep_unlock
|
2021-03-12 20:50:34 +08:00
|
|
|
bne- .Lrestore_nvgprs
|
|
|
|
|
|
|
|
|
|
.Lfast_user_interrupt_return:
|
|
|
|
|
lwz r11,_NIP(r1)
|
|
|
|
|
lwz r12,_MSR(r1)
|
|
|
|
|
mtspr SPRN_SRR0,r11
|
|
|
|
|
mtspr SPRN_SRR1,r12
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
stwcx. r0,0,r1 /* to clear the reservation */
|
|
|
|
|
FTR_SECTION_ELSE
|
|
|
|
|
lwarx r0,0,r1
|
|
|
|
|
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
2012-09-17 07:54:30 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
lwz r3,_CCR(r1)
|
|
|
|
|
lwz r4,_LINK(r1)
|
|
|
|
|
lwz r5,_CTR(r1)
|
|
|
|
|
lwz r6,_XER(r1)
|
|
|
|
|
li r0,0
|
2012-09-17 07:54:30 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
/*
|
|
|
|
|
* Leaving a stale exception_marker on the stack can confuse
|
|
|
|
|
* the reliable stack unwinder later on. Clear it.
|
|
|
|
|
*/
|
|
|
|
|
stw r0,8(r1)
|
2021-10-22 14:13:22 +08:00
|
|
|
REST_GPRS(7, 12, r1)
|
2012-09-17 07:54:30 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
mtcr r3
|
|
|
|
|
mtlr r4
|
2012-09-17 07:54:30 +08:00
|
|
|
mtctr r5
|
2021-03-12 20:50:34 +08:00
|
|
|
mtspr SPRN_XER,r6
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2021-10-22 14:13:22 +08:00
|
|
|
REST_GPRS(2, 6, r1)
|
2021-03-12 20:50:34 +08:00
|
|
|
REST_GPR(0, r1)
|
|
|
|
|
REST_GPR(1, r1)
|
|
|
|
|
rfi
|
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
|
b . /* Prevent prefetch past rfi */
|
|
|
|
|
#endif
|
2009-06-18 01:43:59 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
.Lrestore_nvgprs:
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
b .Lfast_user_interrupt_return
|
2009-06-18 01:43:59 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
.Lkernel_interrupt_return:
|
|
|
|
|
bl interrupt_exit_kernel_prepare
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
.Lfast_kernel_interrupt_return:
|
|
|
|
|
cmpwi cr1,r3,0
|
|
|
|
|
lwz r11,_NIP(r1)
|
|
|
|
|
lwz r12,_MSR(r1)
|
|
|
|
|
mtspr SPRN_SRR0,r11
|
|
|
|
|
mtspr SPRN_SRR1,r12
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2007-11-10 06:17:49 +08:00
|
|
|
BEGIN_FTR_SECTION
|
2021-03-12 20:50:34 +08:00
|
|
|
stwcx. r0,0,r1 /* to clear the reservation */
|
|
|
|
|
FTR_SECTION_ELSE
|
|
|
|
|
lwarx r0,0,r1
|
|
|
|
|
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
lwz r3,_LINK(r1)
|
|
|
|
|
lwz r4,_CTR(r1)
|
|
|
|
|
lwz r5,_XER(r1)
|
|
|
|
|
lwz r6,_CCR(r1)
|
|
|
|
|
li r0,0
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2021-10-22 14:13:22 +08:00
|
|
|
REST_GPRS(7, 12, r1)
|
2021-03-12 20:50:34 +08:00
|
|
|
|
|
|
|
|
mtlr r3
|
|
|
|
|
mtctr r4
|
|
|
|
|
mtspr SPRN_XER,r5
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/*
|
2021-03-12 20:50:34 +08:00
|
|
|
* Leaving a stale exception_marker on the stack can confuse
|
|
|
|
|
* the reliable stack unwinder later on. Clear it.
|
2005-10-10 20:36:14 +08:00
|
|
|
*/
|
2021-03-12 20:50:34 +08:00
|
|
|
stw r0,8(r1)
|
|
|
|
|
|
2021-10-22 14:13:22 +08:00
|
|
|
REST_GPRS(2, 5, r1)
|
2021-03-12 20:50:34 +08:00
|
|
|
|
|
|
|
|
bne- cr1,1f /* emulate stack store */
|
|
|
|
|
mtcr r6
|
|
|
|
|
REST_GPR(6, r1)
|
|
|
|
|
REST_GPR(0, r1)
|
|
|
|
|
REST_GPR(1, r1)
|
2020-11-09 00:57:36 +08:00
|
|
|
rfi
|
2021-03-12 20:50:34 +08:00
|
|
|
#ifdef CONFIG_40x
|
|
|
|
|
b . /* Prevent prefetch past rfi */
|
|
|
|
|
#endif
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2021-03-12 20:50:34 +08:00
|
|
|
1: /*
|
|
|
|
|
* Emulate stack store with update. New r1 value was already calculated
|
|
|
|
|
* and updated in our interrupt regs by emulate_loadstore, but we can't
|
|
|
|
|
* store the previous value of r1 to the stack before re-loading our
|
|
|
|
|
* registers from it, otherwise they could be clobbered. Use
|
|
|
|
|
* SPRG Scratch0 as temporary storage to hold the store
|
|
|
|
|
* data, as interrupts are disabled here so it won't be clobbered.
|
2005-10-10 20:36:14 +08:00
|
|
|
*/
|
2021-03-12 20:50:34 +08:00
|
|
|
mtcr r6
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
mtspr SPRN_SPRG_WSCRATCH0, r9
|
|
|
|
|
#else
|
|
|
|
|
mtspr SPRN_SPRG_SCRATCH0, r9
|
|
|
|
|
#endif
|
|
|
|
|
addi r9,r1,INT_FRAME_SIZE /* get original r1 */
|
|
|
|
|
REST_GPR(6, r1)
|
|
|
|
|
REST_GPR(0, r1)
|
|
|
|
|
REST_GPR(1, r1)
|
|
|
|
|
stw r9,0(r1) /* perform store component of stwu */
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
mfspr r9, SPRN_SPRG_RSCRATCH0
|
|
|
|
|
#else
|
|
|
|
|
mfspr r9, SPRN_SPRG_SCRATCH0
|
|
|
|
|
#endif
|
2005-10-10 20:36:14 +08:00
|
|
|
rfi
|
2021-03-12 20:50:34 +08:00
|
|
|
#ifdef CONFIG_40x
|
|
|
|
|
b . /* Prevent prefetch past rfi */
|
|
|
|
|
#endif
|
|
|
|
|
_ASM_NOKPROBE_SYMBOL(interrupt_return)
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Returning from a critical interrupt in user mode doesn't need
|
|
|
|
|
* to be any different from a normal exception. For a critical
|
|
|
|
|
* interrupt in the kernel, we just return (without checking for
|
|
|
|
|
* preemption) since the interrupt may have happened at some crucial
|
|
|
|
|
* place (e.g. inside the TLB miss handler), and because we will be
|
|
|
|
|
* running with r1 pointing into critical_stack, not the current
|
|
|
|
|
* process's kernel stack (and therefore current_thread_info() will
|
|
|
|
|
* give the wrong answer).
|
|
|
|
|
* We have to restore various SPRs that may have been in use at the
|
|
|
|
|
* time of the critical interrupt.
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
|
#define PPC_40x_TURN_OFF_MSR_DR \
|
|
|
|
|
/* avoid any possible TLB misses here by turning off MSR.DR, we \
|
|
|
|
|
* assume the instructions here are mapped by a pinned TLB entry */ \
|
|
|
|
|
li r10,MSR_IR; \
|
|
|
|
|
mtmsr r10; \
|
|
|
|
|
isync; \
|
|
|
|
|
tophys(r1, r1);
|
|
|
|
|
#else
|
|
|
|
|
#define PPC_40x_TURN_OFF_MSR_DR
|
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|
|
|
#endif
|
|
|
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|
|
|
|
#define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
|
|
|
|
|
REST_NVGPRS(r1); \
|
|
|
|
|
lwz r3,_MSR(r1); \
|
|
|
|
|
andi. r3,r3,MSR_PR; \
|
2021-03-12 20:50:34 +08:00
|
|
|
bne interrupt_return; \
|
2005-10-10 20:36:14 +08:00
|
|
|
lwz r0,GPR0(r1); \
|
|
|
|
|
lwz r2,GPR2(r1); \
|
2021-10-22 14:13:22 +08:00
|
|
|
REST_GPRS(3, 8, r1); \
|
2005-10-10 20:36:14 +08:00
|
|
|
lwz r10,_XER(r1); \
|
|
|
|
|
lwz r11,_CTR(r1); \
|
|
|
|
|
mtspr SPRN_XER,r10; \
|
|
|
|
|
mtctr r11; \
|
|
|
|
|
stwcx. r0,0,r1; /* to clear the reservation */ \
|
|
|
|
|
lwz r11,_LINK(r1); \
|
|
|
|
|
mtlr r11; \
|
|
|
|
|
lwz r10,_CCR(r1); \
|
|
|
|
|
mtcrf 0xff,r10; \
|
|
|
|
|
PPC_40x_TURN_OFF_MSR_DR; \
|
|
|
|
|
lwz r9,_DEAR(r1); \
|
|
|
|
|
lwz r10,_ESR(r1); \
|
|
|
|
|
mtspr SPRN_DEAR,r9; \
|
|
|
|
|
mtspr SPRN_ESR,r10; \
|
|
|
|
|
lwz r11,_NIP(r1); \
|
|
|
|
|
lwz r12,_MSR(r1); \
|
|
|
|
|
mtspr exc_lvl_srr0,r11; \
|
|
|
|
|
mtspr exc_lvl_srr1,r12; \
|
|
|
|
|
lwz r9,GPR9(r1); \
|
|
|
|
|
lwz r12,GPR12(r1); \
|
|
|
|
|
lwz r10,GPR10(r1); \
|
|
|
|
|
lwz r11,GPR11(r1); \
|
|
|
|
|
lwz r1,GPR1(r1); \
|
|
|
|
|
exc_lvl_rfi; \
|
|
|
|
|
b .; /* prevent prefetch past exc_lvl_rfi */
|
|
|
|
|
|
2008-04-30 18:23:21 +08:00
|
|
|
#define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
|
|
|
|
|
lwz r9,_##exc_lvl_srr0(r1); \
|
|
|
|
|
lwz r10,_##exc_lvl_srr1(r1); \
|
|
|
|
|
mtspr SPRN_##exc_lvl_srr0,r9; \
|
|
|
|
|
mtspr SPRN_##exc_lvl_srr1,r10;
|
|
|
|
|
|
2009-02-13 06:12:40 +08:00
|
|
|
#if defined(CONFIG_PPC_BOOK3E_MMU)
|
2008-04-30 18:23:21 +08:00
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define RESTORE_MAS7 \
|
|
|
|
|
lwz r11,MAS7(r1); \
|
|
|
|
|
mtspr SPRN_MAS7,r11;
|
|
|
|
|
#else
|
|
|
|
|
#define RESTORE_MAS7
|
|
|
|
|
#endif /* CONFIG_PHYS_64BIT */
|
|
|
|
|
#define RESTORE_MMU_REGS \
|
|
|
|
|
lwz r9,MAS0(r1); \
|
|
|
|
|
lwz r10,MAS1(r1); \
|
|
|
|
|
lwz r11,MAS2(r1); \
|
|
|
|
|
mtspr SPRN_MAS0,r9; \
|
|
|
|
|
lwz r9,MAS3(r1); \
|
|
|
|
|
mtspr SPRN_MAS1,r10; \
|
|
|
|
|
lwz r10,MAS6(r1); \
|
|
|
|
|
mtspr SPRN_MAS2,r11; \
|
|
|
|
|
mtspr SPRN_MAS3,r9; \
|
|
|
|
|
mtspr SPRN_MAS6,r10; \
|
|
|
|
|
RESTORE_MAS7;
|
|
|
|
|
#elif defined(CONFIG_44x)
|
|
|
|
|
#define RESTORE_MMU_REGS \
|
|
|
|
|
lwz r9,MMUCR(r1); \
|
|
|
|
|
mtspr SPRN_MMUCR,r9;
|
|
|
|
|
#else
|
|
|
|
|
#define RESTORE_MMU_REGS
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_40x
|
2005-10-10 20:36:14 +08:00
|
|
|
.globl ret_from_crit_exc
|
|
|
|
|
ret_from_crit_exc:
|
2008-04-30 18:23:21 +08:00
|
|
|
lis r9,crit_srr0@ha;
|
|
|
|
|
lwz r9,crit_srr0@l(r9);
|
|
|
|
|
lis r10,crit_srr1@ha;
|
|
|
|
|
lwz r10,crit_srr1@l(r10);
|
|
|
|
|
mtspr SPRN_SRR0,r9;
|
|
|
|
|
mtspr SPRN_SRR1,r10;
|
2009-02-11 04:10:44 +08:00
|
|
|
RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
|
2020-04-01 00:03:47 +08:00
|
|
|
_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
|
2008-04-30 18:23:21 +08:00
|
|
|
#endif /* CONFIG_40x */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
2008-04-30 18:23:21 +08:00
|
|
|
.globl ret_from_crit_exc
|
|
|
|
|
ret_from_crit_exc:
|
|
|
|
|
RESTORE_xSRR(SRR0,SRR1);
|
|
|
|
|
RESTORE_MMU_REGS;
|
2009-02-11 04:10:44 +08:00
|
|
|
RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
|
2020-04-01 00:03:47 +08:00
|
|
|
_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
|
2008-04-30 18:23:21 +08:00
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
.globl ret_from_debug_exc
|
|
|
|
|
ret_from_debug_exc:
|
2008-04-30 18:23:21 +08:00
|
|
|
RESTORE_xSRR(SRR0,SRR1);
|
|
|
|
|
RESTORE_xSRR(CSRR0,CSRR1);
|
|
|
|
|
RESTORE_MMU_REGS;
|
2009-02-11 04:10:44 +08:00
|
|
|
RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
|
2020-04-01 00:03:47 +08:00
|
|
|
_ASM_NOKPROBE_SYMBOL(ret_from_debug_exc)
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
.globl ret_from_mcheck_exc
|
|
|
|
|
ret_from_mcheck_exc:
|
2008-04-30 18:23:21 +08:00
|
|
|
RESTORE_xSRR(SRR0,SRR1);
|
|
|
|
|
RESTORE_xSRR(CSRR0,CSRR1);
|
|
|
|
|
RESTORE_xSRR(DSRR0,DSRR1);
|
|
|
|
|
RESTORE_MMU_REGS;
|
2009-02-11 04:10:44 +08:00
|
|
|
RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
|
2020-04-01 00:03:47 +08:00
|
|
|
_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
|
2005-10-10 20:36:14 +08:00
|
|
|
#endif /* CONFIG_BOOKE */
|
|
|
|
|
#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PROM code for specific machines follows. Put it
|
|
|
|
|
* here so it's easy to add arch-specific sections later.
|
|
|
|
|
* -- Cort
|
|
|
|
|
*/
|
2005-10-26 15:05:24 +08:00
|
|
|
#ifdef CONFIG_PPC_RTAS
|
2005-10-10 20:36:14 +08:00
|
|
|
/*
|
|
|
|
|
* On CHRP, the Run-Time Abstraction Services (RTAS) have to be
|
|
|
|
|
* called with the MMU off.
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(enter_rtas)
|
|
|
|
|
stwu r1,-INT_FRAME_SIZE(r1)
|
|
|
|
|
mflr r0
|
|
|
|
|
stw r0,INT_FRAME_SIZE+4(r1)
|
2006-01-13 11:56:25 +08:00
|
|
|
LOAD_REG_ADDR(r4, rtas)
|
2005-10-10 20:36:14 +08:00
|
|
|
lis r6,1f@ha /* physical return address for rtas */
|
|
|
|
|
addi r6,r6,1f@l
|
|
|
|
|
tophys(r6,r6)
|
2005-10-26 15:05:24 +08:00
|
|
|
lwz r8,RTASENTRY(r4)
|
|
|
|
|
lwz r4,RTASBASE(r4)
|
2005-10-10 20:36:14 +08:00
|
|
|
mfmsr r9
|
|
|
|
|
stw r9,8(r1)
|
2019-08-20 22:34:13 +08:00
|
|
|
LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
|
2020-09-29 14:48:34 +08:00
|
|
|
mtmsr r0 /* disable interrupts so SRR0/1 don't get trashed */
|
2005-10-10 20:36:14 +08:00
|
|
|
li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
|
|
|
|
|
mtlr r6
|
2021-03-12 20:50:22 +08:00
|
|
|
stw r1, THREAD + RTAS_SP(r2)
|
2005-10-10 20:36:14 +08:00
|
|
|
mtspr SPRN_SRR0,r8
|
|
|
|
|
mtspr SPRN_SRR1,r9
|
2020-11-09 00:57:36 +08:00
|
|
|
rfi
|
2021-03-12 20:50:22 +08:00
|
|
|
1:
|
2021-03-12 20:50:24 +08:00
|
|
|
lis r8, 1f@h
|
|
|
|
|
ori r8, r8, 1f@l
|
|
|
|
|
LOAD_REG_IMMEDIATE(r9,MSR_KERNEL)
|
|
|
|
|
mtspr SPRN_SRR0,r8
|
|
|
|
|
mtspr SPRN_SRR1,r9
|
|
|
|
|
rfi /* Reactivate MMU translation */
|
|
|
|
|
1:
|
2021-03-12 20:50:22 +08:00
|
|
|
lwz r8,INT_FRAME_SIZE+4(r1) /* get return address */
|
|
|
|
|
lwz r9,8(r1) /* original msr value */
|
2005-10-10 20:36:14 +08:00
|
|
|
addi r1,r1,INT_FRAME_SIZE
|
|
|
|
|
li r0,0
|
2021-03-12 20:50:22 +08:00
|
|
|
stw r0, THREAD + RTAS_SP(r2)
|
2021-03-12 20:50:24 +08:00
|
|
|
mtlr r8
|
|
|
|
|
mtmsr r9
|
|
|
|
|
blr /* return to caller */
|
2020-04-01 00:03:44 +08:00
|
|
|
_ASM_NOKPROBE_SYMBOL(enter_rtas)
|
2005-10-26 15:05:24 +08:00
|
|
|
#endif /* CONFIG_PPC_RTAS */
|