2020-10-14 15:28:37 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2020, Jordan Niethe, IBM Corporation.
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*
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* This file contains low level CPU setup functions.
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* Originally written in assembly by Benjamin Herrenschmidt & various other
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* authors.
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*/
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#include <asm/reg.h>
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#include <asm/synch.h>
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#include <linux/bitops.h>
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#include <asm/cputable.h>
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#include <asm/cpu_setup_power.h>
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/* Disable CPU_FTR_HVMODE and return false if MSR:HV is not set */
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static bool init_hvmode_206(struct cpu_spec *t)
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{
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u64 msr;
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msr = mfmsr();
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if (msr & MSR_HV)
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return true;
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t->cpu_features &= ~(CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST);
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return false;
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}
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static void init_LPCR_ISA300(u64 lpcr, u64 lpes)
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{
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/* POWER9 has no VRMASD */
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lpcr |= (lpes << LPCR_LPES_SH) & LPCR_LPES;
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lpcr |= LPCR_PECE0|LPCR_PECE1|LPCR_PECE2;
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lpcr |= (4ull << LPCR_DPFD_SH) & LPCR_DPFD;
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lpcr &= ~LPCR_HDICE; /* clear HDICE */
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lpcr |= (4ull << LPCR_VC_SH);
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mtspr(SPRN_LPCR, lpcr);
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isync();
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}
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/*
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* Setup a sane LPCR:
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* Called with initial LPCR and desired LPES 2-bit value
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*
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* LPES = 0b01 (HSRR0/1 used for 0x500)
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* PECE = 0b111
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* DPFD = 4
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* HDICE = 0
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* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
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* VRMASD = 0b10000 (L=1, LP=00)
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*
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* Other bits untouched for now
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*/
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static void init_LPCR_ISA206(u64 lpcr, u64 lpes)
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{
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lpcr |= (0x10ull << LPCR_VRMASD_SH) & LPCR_VRMASD;
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init_LPCR_ISA300(lpcr, lpes);
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}
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static void init_FSCR(void)
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{
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u64 fscr;
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fscr = mfspr(SPRN_FSCR);
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fscr |= FSCR_TAR|FSCR_EBB;
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mtspr(SPRN_FSCR, fscr);
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}
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static void init_FSCR_power9(void)
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{
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u64 fscr;
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fscr = mfspr(SPRN_FSCR);
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fscr |= FSCR_SCV;
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mtspr(SPRN_FSCR, fscr);
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init_FSCR();
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}
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static void init_FSCR_power10(void)
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{
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u64 fscr;
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fscr = mfspr(SPRN_FSCR);
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fscr |= FSCR_PREFIX;
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mtspr(SPRN_FSCR, fscr);
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init_FSCR_power9();
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}
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static void init_HFSCR(void)
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{
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u64 hfscr;
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hfscr = mfspr(SPRN_HFSCR);
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hfscr |= HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|HFSCR_DSCR|\
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HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP;
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mtspr(SPRN_HFSCR, hfscr);
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}
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static void init_PMU_HV(void)
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{
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mtspr(SPRN_MMCRC, 0);
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}
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static void init_PMU_HV_ISA207(void)
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{
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mtspr(SPRN_MMCRH, 0);
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}
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static void init_PMU(void)
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{
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mtspr(SPRN_MMCRA, 0);
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2021-11-23 17:51:49 +08:00
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mtspr(SPRN_MMCR0, MMCR0_FC);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_MMCR1, 0);
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mtspr(SPRN_MMCR2, 0);
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}
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static void init_PMU_ISA207(void)
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{
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mtspr(SPRN_MMCRS, 0);
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}
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static void init_PMU_ISA31(void)
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{
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mtspr(SPRN_MMCR3, 0);
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mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
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2021-11-23 17:51:49 +08:00
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mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMCCEXT);
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2020-10-14 15:28:37 +08:00
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}
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/*
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* Note that we can be called twice of pseudo-PVRs.
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* The parameter offset is not used.
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*/
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void __setup_cpu_power7(unsigned long offset, struct cpu_spec *t)
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{
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if (!init_hvmode_206(t))
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return;
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mtspr(SPRN_LPID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
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}
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void __restore_cpu_power7(void)
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{
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u64 msr;
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msr = mfmsr();
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if (!(msr & MSR_HV))
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return;
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mtspr(SPRN_LPID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
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}
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void __setup_cpu_power8(unsigned long offset, struct cpu_spec *t)
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{
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init_FSCR();
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init_PMU();
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init_PMU_ISA207();
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if (!init_hvmode_206(t))
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return;
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mtspr(SPRN_LPID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
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init_HFSCR();
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init_PMU_HV();
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init_PMU_HV_ISA207();
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}
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void __restore_cpu_power8(void)
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{
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u64 msr;
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init_FSCR();
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init_PMU();
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init_PMU_ISA207();
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msr = mfmsr();
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if (!(msr & MSR_HV))
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return;
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mtspr(SPRN_LPID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
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init_HFSCR();
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init_PMU_HV();
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init_PMU_HV_ISA207();
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}
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void __setup_cpu_power9(unsigned long offset, struct cpu_spec *t)
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{
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init_FSCR_power9();
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init_PMU();
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if (!init_hvmode_206(t))
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return;
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mtspr(SPRN_PSSCR, 0);
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_PID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
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LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
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init_HFSCR();
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init_PMU_HV();
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}
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void __restore_cpu_power9(void)
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{
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u64 msr;
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init_FSCR_power9();
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init_PMU();
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msr = mfmsr();
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if (!(msr & MSR_HV))
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return;
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mtspr(SPRN_PSSCR, 0);
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_PID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
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LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
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init_HFSCR();
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init_PMU_HV();
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}
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void __setup_cpu_power10(unsigned long offset, struct cpu_spec *t)
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{
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init_FSCR_power10();
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init_PMU();
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init_PMU_ISA31();
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if (!init_hvmode_206(t))
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return;
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mtspr(SPRN_PSSCR, 0);
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_PID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
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LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
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init_HFSCR();
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init_PMU_HV();
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}
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void __restore_cpu_power10(void)
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{
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u64 msr;
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init_FSCR_power10();
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init_PMU();
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init_PMU_ISA31();
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msr = mfmsr();
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if (!(msr & MSR_HV))
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return;
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mtspr(SPRN_PSSCR, 0);
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_PID, 0);
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2021-11-23 17:51:47 +08:00
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mtspr(SPRN_AMOR, ~0);
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2020-10-14 15:28:37 +08:00
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
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LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
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init_HFSCR();
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init_PMU_HV();
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}
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