2019-05-19 20:07:45 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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2012-11-26 17:16:10 +08:00
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config HAVE_NET_DSA
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def_bool y
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2017-01-10 05:49:26 +08:00
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depends on INET && NETDEVICES && !S390
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2012-11-26 17:16:10 +08:00
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# Drivers must select NET_DSA and the appropriate tagging format
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2019-04-29 01:37:23 +08:00
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menuconfig NET_DSA
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2015-03-21 09:31:03 +08:00
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tristate "Distributed Switch Architecture"
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2019-02-26 11:34:02 +08:00
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depends on HAVE_NET_DSA
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2017-11-11 23:29:41 +08:00
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depends on BRIDGE || BRIDGE=n
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2017-01-10 05:49:26 +08:00
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select NET_SWITCHDEV
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2018-05-11 04:17:32 +08:00
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select PHYLINK
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2019-03-24 18:14:38 +08:00
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select NET_DEVLINK
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2015-03-21 09:31:03 +08:00
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---help---
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Say Y if you want to enable support for the hardware switches supported
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by the Distributed Switch Architecture.
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net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
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2012-11-26 17:16:10 +08:00
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if NET_DSA
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net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
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net: dsa: Optional VLAN-based port separation for switches without tagging
This patch provides generic DSA code for using VLAN (802.1Q) tags for
the same purpose as a dedicated switch tag for injection/extraction.
It is based on the discussions and interest that has been so far
expressed in https://www.spinics.net/lists/netdev/msg556125.html.
Unlike all other DSA-supported tagging protocols, CONFIG_NET_DSA_TAG_8021Q
does not offer a complete solution for drivers (nor can it). Instead, it
provides generic code that driver can opt into calling:
- dsa_8021q_xmit: Inserts a VLAN header with the specified contents.
Can be called from another tagging protocol's xmit function.
Currently the LAN9303 driver is inserting headers that are simply
802.1Q with custom fields, so this is an opportunity for code reuse.
- dsa_8021q_rcv: Retrieves the TPID and TCI from a VLAN-tagged skb.
Removing the VLAN header is left as a decision for the caller to make.
- dsa_port_setup_8021q_tagging: For each user port, installs an Rx VID
and a Tx VID, for proper untagged traffic identification on ingress
and steering on egress. Also sets up the VLAN trunk on the upstream
(CPU or DSA) port. Drivers are intentionally left to call this
function explicitly, depending on the context and hardware support.
The expected switch behavior and VLAN semantics should not be violated
under any conditions. That is, after calling
dsa_port_setup_8021q_tagging, the hardware should still pass all
ingress traffic, be it tagged or untagged.
For uniformity with the other tagging protocols, a module for the
dsa_8021q_netdev_ops structure is registered, but the typical usage is
to set up another tagging protocol which selects CONFIG_NET_DSA_TAG_8021Q,
and calls the API from tag_8021q.h. Null function definitions are also
provided so that a "depends on" is not forced in the Kconfig.
This tagging protocol only works when switch ports are standalone, or
when they are added to a VLAN-unaware bridge. It will probably remain
this way for the reasons below.
When added to a bridge that has vlan_filtering 1, the bridge core will
install its own VLANs and reset the pvids through switchdev. For the
bridge core, switchdev is a write-only pipe. All VLAN-related state is
kept in the bridge core and nothing is read from DSA/switchdev or from
the driver. So the bridge core will break this port separation because
it will install the vlan_default_pvid into all switchdev ports.
Even if we could teach the bridge driver about switchdev preference of a
certain vlan_default_pvid (task difficult in itself since the current
setting is per-bridge but we would need it per-port), there would still
exist many other challenges.
Firstly, in the DSA rcv callback, a driver would have to perform an
iterative reverse lookup to find the correct switch port. That is
because the port is a bridge slave, so its Rx VID (port PVID) is subject
to user configuration. How would we ensure that the user doesn't reset
the pvid to a different value (which would make an O(1) translation
impossible), or to a non-unique value within this DSA switch tree (which
would make any translation impossible)?
Finally, not all switch ports are equal in DSA, and that makes it
difficult for the bridge to be completely aware of this anyway.
The CPU port needs to transmit tagged packets (VLAN trunk) in order for
the DSA rcv code to be able to decode source information.
But the bridge code has absolutely no idea which switch port is the CPU
port, if nothing else then just because there is no netdevice registered
by DSA for the CPU port.
Also DSA does not currently allow the user to specify that they want the
CPU port to do VLAN trunking anyway. VLANs are added to the CPU port
using the same flags as they were added on the user port.
So the VLANs installed by dsa_port_setup_8021q_tagging per driver
request should remain private from the bridge's and user's perspective,
and should not alter the VLAN semantics observed by the user.
In the current implementation a VLAN range ending at 4095 (VLAN_N_VID)
is reserved for this purpose. Each port receives a unique Rx VLAN and a
unique Tx VLAN. Separate VLANs are needed for Rx and Tx because they
serve different purposes: on Rx the switch must process traffic as
untagged and process it with a port-based VLAN, but with care not to
hinder bridging. On the other hand, the Tx VLAN is where the
reachability restrictions are imposed, since by tagging frames in the
xmit callback we are telling the switch onto which port to steer the
frame.
Some general guidance on how this support might be employed for
real-life hardware (some comments made by Florian Fainelli):
- If the hardware supports VLAN tag stacking, it should somehow back
up its private VLAN settings when the bridge tries to override them.
Then the driver could re-apply them as outer tags. Dedicating an outer
tag per bridge device would allow identical inner tag VID numbers to
co-exist, yet preserve broadcast domain isolation.
- If the switch cannot handle VLAN tag stacking, it should disable this
port separation when added as slave to a vlan_filtering bridge, in
that case having reduced functionality.
- Drivers for old switches that don't support the entire VLAN_N_VID
range will need to rework the current range selection mechanism.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-05-05 18:19:22 +08:00
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# tagging formats
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config NET_DSA_TAG_8021Q
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tristate "Tag driver for switches using custom 802.1Q VLAN headers"
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select VLAN_8021Q
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help
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Unlike the other tagging protocols, the 802.1Q config option simply
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provides helpers for other tagging implementations that might rely on
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VLAN in one way or another. It is not a complete solution.
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Drivers which use these helpers should select this as dependency.
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2019-04-29 01:37:23 +08:00
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config NET_DSA_TAG_BRCM_COMMON
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tristate
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default n
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2014-08-28 08:04:55 +08:00
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config NET_DSA_TAG_BRCM
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2019-04-29 01:37:23 +08:00
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tristate "Tag driver for Broadcom switches using in-frame headers"
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select NET_DSA_TAG_BRCM_COMMON
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help
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Say Y if you want to enable support for tagging frames for the
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Broadcom switches which place the tag after the MAC source address.
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2014-08-28 08:04:55 +08:00
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2017-11-11 07:22:54 +08:00
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config NET_DSA_TAG_BRCM_PREPEND
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2019-04-29 01:37:23 +08:00
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tristate "Tag driver for Broadcom switches using prepended headers"
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select NET_DSA_TAG_BRCM_COMMON
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help
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Say Y if you want to enable support for tagging frames for the
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Broadcom switches which places the tag before the Ethernet header
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(prepended).
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config NET_DSA_TAG_GSWIP
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tristate "Tag driver for Lantiq / Intel GSWIP switches"
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help
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Say Y or M if you want to enable support for tagging frames for the
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Lantiq / Intel GSWIP switches.
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2017-11-11 07:22:54 +08:00
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2008-10-07 21:45:02 +08:00
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config NET_DSA_TAG_DSA
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2019-04-29 01:37:23 +08:00
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tristate "Tag driver for Marvell switches using DSA headers"
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help
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Say Y or M if you want to enable support for tagging frames for the
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Marvell switches which use DSA headers.
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2008-10-07 21:45:02 +08:00
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net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
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config NET_DSA_TAG_EDSA
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2019-04-29 01:37:23 +08:00
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tristate "Tag driver for Marvell switches using EtherType DSA headers"
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help
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Say Y or M if you want to enable support for tagging frames for the
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Marvell switches which use EtherType DSA headers.
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net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
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2019-04-29 01:37:23 +08:00
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config NET_DSA_TAG_MTK
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tristate "Tag driver for Mediatek switches"
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help
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Say Y or M if you want to enable support for tagging frames for
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Mediatek switches.
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config NET_DSA_TAG_KSZ_COMMON
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tristate
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default n
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2018-09-10 04:16:43 +08:00
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2017-06-01 04:19:06 +08:00
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config NET_DSA_TAG_KSZ
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2019-04-29 01:37:23 +08:00
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tristate "Tag driver for Microchip 9893 family of switches"
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select NET_DSA_TAG_KSZ_COMMON
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help
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Say Y if you want to enable support for tagging frames for the
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Microchip 9893 family of switches.
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2017-06-01 04:19:06 +08:00
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2018-12-15 08:58:04 +08:00
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config NET_DSA_TAG_KSZ9477
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2019-04-29 01:37:23 +08:00
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tristate "Tag driver for Microchip 9477 family of switches"
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select NET_DSA_TAG_KSZ_COMMON
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help
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Say Y if you want to enable support for tagging frames for the
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Microchip 9477 family of switches.
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2018-12-15 08:58:04 +08:00
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2019-04-29 01:37:23 +08:00
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config NET_DSA_TAG_QCA
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tristate "Tag driver for Qualcomm Atheros QCA8K switches"
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help
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Say Y or M if you want to enable support for tagging frames for
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the Qualcomm Atheros QCA8K switches.
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2012-11-26 17:16:10 +08:00
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2019-04-29 01:37:23 +08:00
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config NET_DSA_TAG_LAN9303
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tristate "Tag driver for SMSC/Microchip LAN9303 family of switches"
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help
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Say Y or M if you want to enable support for tagging frames for the
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SMSC/Microchip LAN9303 family of switches.
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2016-09-15 22:26:40 +08:00
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2019-05-05 18:19:27 +08:00
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config NET_DSA_TAG_SJA1105
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tristate "Tag driver for NXP SJA1105 switches"
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select NET_DSA_TAG_8021Q
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2019-06-12 02:47:45 +08:00
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select PACKING
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2019-05-05 18:19:27 +08:00
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help
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Say Y or M if you want to enable support for tagging frames with the
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NXP SJA1105 switch family. Both the native tagging protocol (which
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is only for link-local traffic) as well as non-native tagging (based
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on a custom 802.1Q VLAN header) are available.
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2017-05-17 04:40:07 +08:00
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config NET_DSA_TAG_TRAILER
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2019-04-29 01:37:23 +08:00
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tristate "Tag driver for switches using a trailer tag"
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help
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Say Y or M if you want to enable support for tagging frames at
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with a trailed. e.g. Marvell 88E6060.
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2017-04-18 16:48:24 +08:00
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2012-11-26 17:16:10 +08:00
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endif
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