2019-05-27 14:55:06 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2013-06-18 04:29:23 +08:00
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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2014-10-16 01:23:00 +08:00
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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2013-06-18 04:29:23 +08:00
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2014-10-16 01:23:03 +08:00
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#include <linux/reset.h>
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#include <linux/cpu.h>
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2013-06-18 04:29:23 +08:00
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#include <asm/cacheflush.h>
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2014-07-19 21:03:26 +08:00
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#include <asm/cp15.h>
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2013-06-18 04:29:23 +08:00
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/map.h>
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#include "core.h"
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static void __iomem *scu_base_addr;
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static void __iomem *sram_base_addr;
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static int ncores;
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#define PMU_PWRDN_CON 0x08
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#define PMU_PWRDN_ST 0x0c
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#define PMU_PWRDN_SCU 4
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2014-10-16 01:23:00 +08:00
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static struct regmap *pmu;
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2015-11-04 20:25:16 +08:00
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static int has_pmu = true;
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2013-06-18 04:29:23 +08:00
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2014-10-16 01:23:00 +08:00
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static int pmu_power_domain_is_on(int pd)
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2013-06-18 04:29:23 +08:00
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{
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2014-10-16 01:23:00 +08:00
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u32 val;
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int ret;
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ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
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if (ret < 0)
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return ret;
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return !(val & BIT(pd));
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2013-06-18 04:29:23 +08:00
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}
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2015-03-02 07:12:03 +08:00
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static struct reset_control *rockchip_get_core_reset(int cpu)
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2014-10-16 01:23:03 +08:00
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{
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struct device *dev = get_cpu_device(cpu);
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struct device_node *np;
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/* The cpu device is only available after the initial core bringup */
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if (dev)
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np = dev->of_node;
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else
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2016-03-17 21:43:11 +08:00
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np = of_get_cpu_node(cpu, NULL);
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2014-10-16 01:23:03 +08:00
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2017-07-19 23:25:05 +08:00
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return of_reset_control_get_exclusive(np, NULL);
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2014-10-16 01:23:03 +08:00
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}
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2014-10-16 01:23:00 +08:00
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static int pmu_set_power_domain(int pd, bool on)
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2013-06-18 04:29:23 +08:00
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{
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2014-10-16 01:23:00 +08:00
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u32 val = (on) ? 0 : BIT(pd);
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ARM: rockchip: fix the CPU soft reset
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 10000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducable log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
.......
or others similar log:
.......
[ 4072.454453] CPU1: shutdown
[ 4072.504436] CPU2: shutdown
[ 4072.554426] CPU3: shutdown
[ 4072.577827] CPU1: Booted secondary processor
[ 4072.582611] CPU2: Booted secondary processor
<hang>
Tested by cpu up/down scripts, the results told us need delay more time
before write the sram. The wait time is affected by many aspects
(e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
Although the cpus other than cpu0 will write the sram, the speedy is
no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.....
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 3ee851e212d0 ("ARM: rockchip: add basic smp support for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-06-09 17:49:57 +08:00
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struct reset_control *rstc = rockchip_get_core_reset(pd);
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2014-10-16 01:23:00 +08:00
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int ret;
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ARM: rockchip: fix the CPU soft reset
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 10000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducable log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
.......
or others similar log:
.......
[ 4072.454453] CPU1: shutdown
[ 4072.504436] CPU2: shutdown
[ 4072.554426] CPU3: shutdown
[ 4072.577827] CPU1: Booted secondary processor
[ 4072.582611] CPU2: Booted secondary processor
<hang>
Tested by cpu up/down scripts, the results told us need delay more time
before write the sram. The wait time is affected by many aspects
(e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
Although the cpus other than cpu0 will write the sram, the speedy is
no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.....
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 3ee851e212d0 ("ARM: rockchip: add basic smp support for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-06-09 17:49:57 +08:00
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if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
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pr_err("%s: could not get reset control for core %d\n",
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__func__, pd);
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return PTR_ERR(rstc);
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}
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2014-10-16 01:23:03 +08:00
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/*
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* We need to soft reset the cpu when we turn off the cpu power domain,
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* or else the active processors might be stalled when the individual
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* processor is powered down.
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*/
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ARM: rockchip: fix the CPU soft reset
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 10000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducable log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
.......
or others similar log:
.......
[ 4072.454453] CPU1: shutdown
[ 4072.504436] CPU2: shutdown
[ 4072.554426] CPU3: shutdown
[ 4072.577827] CPU1: Booted secondary processor
[ 4072.582611] CPU2: Booted secondary processor
<hang>
Tested by cpu up/down scripts, the results told us need delay more time
before write the sram. The wait time is affected by many aspects
(e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
Although the cpus other than cpu0 will write the sram, the speedy is
no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.....
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 3ee851e212d0 ("ARM: rockchip: add basic smp support for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-06-09 17:49:57 +08:00
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if (!IS_ERR(rstc) && !on)
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reset_control_assert(rstc);
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2014-10-16 01:23:03 +08:00
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2015-11-04 20:25:16 +08:00
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if (has_pmu) {
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ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
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2014-10-16 01:23:00 +08:00
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if (ret < 0) {
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2015-11-04 20:25:16 +08:00
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pr_err("%s: could not update power domain\n",
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2015-06-09 17:49:59 +08:00
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__func__);
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2014-10-16 01:23:00 +08:00
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return ret;
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}
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2015-11-04 20:25:16 +08:00
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ret = -1;
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while (ret != on) {
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ret = pmu_power_domain_is_on(pd);
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if (ret < 0) {
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pr_err("%s: could not read power domain state\n",
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__func__);
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return ret;
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}
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}
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2014-10-16 01:23:00 +08:00
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}
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ARM: rockchip: fix the CPU soft reset
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 10000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducable log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
.......
or others similar log:
.......
[ 4072.454453] CPU1: shutdown
[ 4072.504436] CPU2: shutdown
[ 4072.554426] CPU3: shutdown
[ 4072.577827] CPU1: Booted secondary processor
[ 4072.582611] CPU2: Booted secondary processor
<hang>
Tested by cpu up/down scripts, the results told us need delay more time
before write the sram. The wait time is affected by many aspects
(e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
Although the cpus other than cpu0 will write the sram, the speedy is
no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.....
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 3ee851e212d0 ("ARM: rockchip: add basic smp support for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-06-09 17:49:57 +08:00
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if (!IS_ERR(rstc)) {
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if (on)
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reset_control_deassert(rstc);
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reset_control_put(rstc);
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}
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2014-10-16 01:23:00 +08:00
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return 0;
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2013-06-18 04:29:23 +08:00
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}
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/*
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* Handling of CPU cores
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*/
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2015-01-18 05:48:41 +08:00
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static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
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2013-06-18 04:29:23 +08:00
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{
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2014-10-16 01:23:03 +08:00
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int ret;
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2015-11-04 20:25:16 +08:00
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if (!sram_base_addr || (has_pmu && !pmu)) {
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2013-06-18 04:29:23 +08:00
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pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
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return -ENXIO;
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}
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if (cpu >= ncores) {
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pr_err("%s: cpu %d outside maximum number of cpus %d\n",
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2015-06-09 17:49:59 +08:00
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__func__, cpu, ncores);
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2013-06-18 04:29:23 +08:00
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return -ENXIO;
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}
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/* start the core */
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2014-10-16 01:23:03 +08:00
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ret = pmu_set_power_domain(0 + cpu, true);
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if (ret < 0)
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return ret;
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if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
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2015-06-09 17:49:59 +08:00
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/*
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* We communicate with the bootrom to active the cpus other
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2014-10-16 01:23:03 +08:00
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* than cpu0, after a blob of initialize code, they will
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* stay at wfe state, once they are actived, they will check
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* the mailbox:
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* sram_base_addr + 4: 0xdeadbeaf
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* sram_base_addr + 8: start address for pc
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ARM: rockchip: fix the CPU soft reset
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 10000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducable log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
.......
or others similar log:
.......
[ 4072.454453] CPU1: shutdown
[ 4072.504436] CPU2: shutdown
[ 4072.554426] CPU3: shutdown
[ 4072.577827] CPU1: Booted secondary processor
[ 4072.582611] CPU2: Booted secondary processor
<hang>
Tested by cpu up/down scripts, the results told us need delay more time
before write the sram. The wait time is affected by many aspects
(e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
Although the cpus other than cpu0 will write the sram, the speedy is
no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.....
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 3ee851e212d0 ("ARM: rockchip: add basic smp support for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-06-09 17:49:57 +08:00
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|
|
* The cpu0 need to wait the other cpus other than cpu0 entering
|
|
|
|
* the wfe state.The wait time is affected by many aspects.
|
|
|
|
* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
|
2015-06-09 17:49:59 +08:00
|
|
|
*/
|
ARM: rockchip: fix the CPU soft reset
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 10000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducable log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
.......
or others similar log:
.......
[ 4072.454453] CPU1: shutdown
[ 4072.504436] CPU2: shutdown
[ 4072.554426] CPU3: shutdown
[ 4072.577827] CPU1: Booted secondary processor
[ 4072.582611] CPU2: Booted secondary processor
<hang>
Tested by cpu up/down scripts, the results told us need delay more time
before write the sram. The wait time is affected by many aspects
(e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
Although the cpus other than cpu0 will write the sram, the speedy is
no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.....
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 3ee851e212d0 ("ARM: rockchip: add basic smp support for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-06-09 17:49:57 +08:00
|
|
|
mdelay(1); /* ensure the cpus other than cpu0 to startup */
|
|
|
|
|
2017-01-15 10:59:29 +08:00
|
|
|
writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
|
2014-10-16 01:23:03 +08:00
|
|
|
writel(0xDEADBEAF, sram_base_addr + 4);
|
|
|
|
dsb_sev();
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2013-06-18 04:29:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* rockchip_smp_prepare_sram - populate necessary sram block
|
|
|
|
* Starting cores execute the code residing at the start of the on-chip sram
|
|
|
|
* after power-on. Therefore make sure, this sram region is reserved and
|
|
|
|
* big enough. After this check, copy the trampoline code that directs the
|
|
|
|
* core to the real startup code in ram into the sram-region.
|
|
|
|
* @node: mmio-sram device node
|
|
|
|
*/
|
|
|
|
static int __init rockchip_smp_prepare_sram(struct device_node *node)
|
|
|
|
{
|
|
|
|
unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
|
|
|
|
&rockchip_secondary_trampoline;
|
|
|
|
struct resource res;
|
|
|
|
unsigned int rsize;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
|
|
if (ret < 0) {
|
2017-07-22 03:28:32 +08:00
|
|
|
pr_err("%s: could not get address for node %pOF\n",
|
|
|
|
__func__, node);
|
2013-06-18 04:29:23 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
rsize = resource_size(&res);
|
|
|
|
if (rsize < trampoline_sz) {
|
|
|
|
pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
|
|
|
|
__func__, rsize, trampoline_sz);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set the boot function for the sram code */
|
2017-01-15 10:59:29 +08:00
|
|
|
rockchip_boot_fn = __pa_symbol(secondary_startup);
|
2013-06-18 04:29:23 +08:00
|
|
|
|
|
|
|
/* copy the trampoline to sram, that runs during startup of the core */
|
|
|
|
memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
|
|
|
|
flush_cache_all();
|
|
|
|
outer_clean_range(0, trampoline_sz);
|
|
|
|
|
|
|
|
dsb_sev();
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-02 07:12:03 +08:00
|
|
|
static const struct regmap_config rockchip_pmu_regmap_config = {
|
2018-03-12 17:51:42 +08:00
|
|
|
.name = "rockchip-pmu",
|
2014-10-16 01:23:00 +08:00
|
|
|
.reg_bits = 32,
|
|
|
|
.val_bits = 32,
|
|
|
|
.reg_stride = 4,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init rockchip_smp_prepare_pmu(void)
|
|
|
|
{
|
|
|
|
struct device_node *node;
|
|
|
|
void __iomem *pmu_base;
|
|
|
|
|
2014-10-16 01:23:01 +08:00
|
|
|
/*
|
|
|
|
* This function is only called via smp_ops->smp_prepare_cpu().
|
|
|
|
* That only happens if a "/cpus" device tree node exists
|
|
|
|
* and has an "enable-method" property that selects the SMP
|
|
|
|
* operations defined herein.
|
|
|
|
*/
|
|
|
|
node = of_find_node_by_path("/cpus");
|
|
|
|
|
|
|
|
pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
|
|
|
|
of_node_put(node);
|
|
|
|
if (!IS_ERR(pmu))
|
|
|
|
return 0;
|
|
|
|
|
2014-10-16 01:23:00 +08:00
|
|
|
pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
|
|
|
|
if (!IS_ERR(pmu))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* fallback, create our own regmap for the pmu area */
|
|
|
|
pmu = NULL;
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
|
|
|
|
if (!node) {
|
|
|
|
pr_err("%s: could not find pmu dt node\n", __func__);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
pmu_base = of_iomap(node, 0);
|
2019-03-05 19:32:56 +08:00
|
|
|
of_node_put(node);
|
2014-10-16 01:23:00 +08:00
|
|
|
if (!pmu_base) {
|
|
|
|
pr_err("%s: could not map pmu registers\n", __func__);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
|
|
|
|
if (IS_ERR(pmu)) {
|
|
|
|
int ret = PTR_ERR(pmu);
|
|
|
|
|
|
|
|
iounmap(pmu_base);
|
|
|
|
pmu = NULL;
|
|
|
|
pr_err("%s: regmap init failed\n", __func__);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-06-18 04:29:23 +08:00
|
|
|
static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
|
|
|
{
|
|
|
|
struct device_node *node;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
|
|
|
|
if (!node) {
|
|
|
|
pr_err("%s: could not find sram dt node\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-10-16 01:23:03 +08:00
|
|
|
sram_base_addr = of_iomap(node, 0);
|
|
|
|
if (!sram_base_addr) {
|
|
|
|
pr_err("%s: could not map sram registers\n", __func__);
|
2019-04-26 15:08:08 +08:00
|
|
|
of_node_put(node);
|
2013-06-18 04:29:23 +08:00
|
|
|
return;
|
2014-10-16 01:23:03 +08:00
|
|
|
}
|
2013-06-18 04:29:23 +08:00
|
|
|
|
2019-04-26 15:08:08 +08:00
|
|
|
if (has_pmu && rockchip_smp_prepare_pmu()) {
|
|
|
|
of_node_put(node);
|
2013-06-18 04:29:23 +08:00
|
|
|
return;
|
2019-04-26 15:08:08 +08:00
|
|
|
}
|
2013-06-18 04:29:23 +08:00
|
|
|
|
2014-10-16 01:23:03 +08:00
|
|
|
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
|
2019-04-26 15:08:08 +08:00
|
|
|
if (rockchip_smp_prepare_sram(node)) {
|
|
|
|
of_node_put(node);
|
2014-10-16 01:23:03 +08:00
|
|
|
return;
|
2019-04-26 15:08:08 +08:00
|
|
|
}
|
2013-06-18 04:29:23 +08:00
|
|
|
|
2014-10-16 01:23:03 +08:00
|
|
|
/* enable the SCU power domain */
|
|
|
|
pmu_set_power_domain(PMU_PWRDN_SCU, true);
|
|
|
|
|
2019-04-26 15:08:08 +08:00
|
|
|
of_node_put(node);
|
2014-10-16 01:23:03 +08:00
|
|
|
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
|
|
|
|
if (!node) {
|
|
|
|
pr_err("%s: missing scu\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
2013-06-18 04:29:23 +08:00
|
|
|
|
2014-10-16 01:23:03 +08:00
|
|
|
scu_base_addr = of_iomap(node, 0);
|
|
|
|
if (!scu_base_addr) {
|
|
|
|
pr_err("%s: could not map scu registers\n", __func__);
|
2019-04-26 15:08:08 +08:00
|
|
|
of_node_put(node);
|
2014-10-16 01:23:03 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* While the number of cpus is gathered from dt, also get the
|
|
|
|
* number of cores from the scu to verify this value when
|
|
|
|
* booting the cores.
|
|
|
|
*/
|
|
|
|
ncores = scu_get_core_count(scu_base_addr);
|
|
|
|
pr_err("%s: ncores %d\n", __func__, ncores);
|
|
|
|
|
|
|
|
scu_enable(scu_base_addr);
|
|
|
|
} else {
|
|
|
|
unsigned int l2ctlr;
|
|
|
|
|
|
|
|
asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
|
|
|
|
ncores = ((l2ctlr >> 24) & 0x3) + 1;
|
|
|
|
}
|
2019-04-26 15:08:08 +08:00
|
|
|
of_node_put(node);
|
2013-06-18 04:29:23 +08:00
|
|
|
|
|
|
|
/* Make sure that all cores except the first are really off */
|
|
|
|
for (i = 1; i < ncores; i++)
|
|
|
|
pmu_set_power_domain(0 + i, false);
|
|
|
|
}
|
|
|
|
|
2015-11-04 20:25:16 +08:00
|
|
|
static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
|
|
|
|
{
|
|
|
|
has_pmu = false;
|
|
|
|
|
|
|
|
rockchip_smp_prepare_cpus(max_cpus);
|
|
|
|
}
|
|
|
|
|
2014-07-19 21:03:26 +08:00
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
static int rockchip_cpu_kill(unsigned int cpu)
|
|
|
|
{
|
2015-06-09 17:49:58 +08:00
|
|
|
/*
|
|
|
|
* We need a delay here to ensure that the dying CPU can finish
|
|
|
|
* executing v7_coherency_exit() and reach the WFI/WFE state
|
|
|
|
* prior to having the power domain disabled.
|
|
|
|
*/
|
|
|
|
mdelay(1);
|
|
|
|
|
2014-07-19 21:03:26 +08:00
|
|
|
pmu_set_power_domain(0 + cpu, false);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rockchip_cpu_die(unsigned int cpu)
|
|
|
|
{
|
|
|
|
v7_exit_coherency_flush(louis);
|
2015-06-09 17:49:59 +08:00
|
|
|
while (1)
|
2014-07-19 21:03:26 +08:00
|
|
|
cpu_do_idle();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2015-12-05 01:04:44 +08:00
|
|
|
static const struct smp_operations rk3036_smp_ops __initconst = {
|
2015-11-04 20:25:16 +08:00
|
|
|
.smp_prepare_cpus = rk3036_smp_prepare_cpus,
|
|
|
|
.smp_boot_secondary = rockchip_boot_secondary,
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
.cpu_kill = rockchip_cpu_kill,
|
|
|
|
.cpu_die = rockchip_cpu_die,
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2015-11-15 09:39:53 +08:00
|
|
|
static const struct smp_operations rockchip_smp_ops __initconst = {
|
2013-06-18 04:29:23 +08:00
|
|
|
.smp_prepare_cpus = rockchip_smp_prepare_cpus,
|
|
|
|
.smp_boot_secondary = rockchip_boot_secondary,
|
2014-07-19 21:03:26 +08:00
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
.cpu_kill = rockchip_cpu_kill,
|
|
|
|
.cpu_die = rockchip_cpu_die,
|
|
|
|
#endif
|
2013-06-18 04:29:23 +08:00
|
|
|
};
|
2015-06-09 17:49:59 +08:00
|
|
|
|
2015-11-04 20:25:16 +08:00
|
|
|
CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
|
2014-03-27 08:06:32 +08:00
|
|
|
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
|