pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/*
|
|
|
|
* PCIe driver for Marvell Armada 370 and Armada XP SoCs
|
|
|
|
*
|
2016-07-03 07:13:28 +08:00
|
|
|
* Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
|
|
*
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/pci.h>
|
|
|
|
#include <linux/clk.h>
|
2013-08-13 20:25:23 +08:00
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/gpio.h>
|
2016-07-03 07:13:28 +08:00
|
|
|
#include <linux/init.h>
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
#include <linux/mbus.h>
|
2013-08-10 04:27:14 +08:00
|
|
|
#include <linux/msi.h>
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
#include <linux/slab.h>
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/of_address.h>
|
|
|
|
#include <linux/of_irq.h>
|
2013-08-13 20:25:23 +08:00
|
|
|
#include <linux/of_gpio.h>
|
|
|
|
#include <linux/of_pci.h>
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
#include <linux/of_platform.h>
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PCIe unit register offsets.
|
|
|
|
*/
|
|
|
|
#define PCIE_DEV_ID_OFF 0x0000
|
|
|
|
#define PCIE_CMD_OFF 0x0004
|
|
|
|
#define PCIE_DEV_REV_OFF 0x0008
|
|
|
|
#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
|
|
|
|
#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
|
2015-10-04 02:13:33 +08:00
|
|
|
#define PCIE_CAP_PCIEXP 0x0060
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
#define PCIE_HEADER_LOG_4_OFF 0x0128
|
|
|
|
#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
|
|
|
|
#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
|
|
|
|
#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
|
|
|
|
#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
|
|
|
|
#define PCIE_WIN5_CTRL_OFF 0x1880
|
|
|
|
#define PCIE_WIN5_BASE_OFF 0x1884
|
|
|
|
#define PCIE_WIN5_REMAP_OFF 0x188c
|
|
|
|
#define PCIE_CONF_ADDR_OFF 0x18f8
|
|
|
|
#define PCIE_CONF_ADDR_EN 0x80000000
|
|
|
|
#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
|
|
|
|
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
|
|
|
|
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
|
|
|
|
#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
|
|
|
|
#define PCIE_CONF_ADDR(bus, devfn, where) \
|
|
|
|
(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
|
|
|
|
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
|
|
|
|
PCIE_CONF_ADDR_EN)
|
|
|
|
#define PCIE_CONF_DATA_OFF 0x18fc
|
|
|
|
#define PCIE_MASK_OFF 0x1910
|
|
|
|
#define PCIE_MASK_ENABLE_INTS 0x0f000000
|
|
|
|
#define PCIE_CTRL_OFF 0x1a00
|
|
|
|
#define PCIE_CTRL_X1_MODE 0x0001
|
|
|
|
#define PCIE_STAT_OFF 0x1a04
|
|
|
|
#define PCIE_STAT_BUS 0xff00
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:51 +08:00
|
|
|
#define PCIE_STAT_DEV 0x1f0000
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
#define PCIE_STAT_LINK_DOWN BIT(0)
|
2015-10-04 02:13:33 +08:00
|
|
|
#define PCIE_RC_RTSTA 0x1a14
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
#define PCIE_DEBUG_CTRL 0x1a60
|
|
|
|
#define PCIE_DEBUG_SOFT_RESET BIT(20)
|
|
|
|
|
2015-10-04 02:13:33 +08:00
|
|
|
enum {
|
|
|
|
PCISWCAP = PCI_BRIDGE_CONTROL + 2,
|
|
|
|
PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID,
|
|
|
|
PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP,
|
|
|
|
PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL,
|
|
|
|
PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP,
|
|
|
|
PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL,
|
|
|
|
PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP,
|
|
|
|
PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL,
|
|
|
|
PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL,
|
|
|
|
PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA,
|
|
|
|
PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2,
|
|
|
|
PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2,
|
|
|
|
PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2,
|
|
|
|
PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2,
|
|
|
|
PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2,
|
|
|
|
PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2,
|
|
|
|
};
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/* PCI configuration space of a PCI-to-PCI bridge */
|
|
|
|
struct mvebu_sw_pci_bridge {
|
|
|
|
u16 vendor;
|
|
|
|
u16 device;
|
|
|
|
u16 command;
|
2015-10-04 02:13:33 +08:00
|
|
|
u16 status;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
u16 class;
|
|
|
|
u8 interface;
|
|
|
|
u8 revision;
|
|
|
|
u8 bist;
|
|
|
|
u8 header_type;
|
|
|
|
u8 latency_timer;
|
|
|
|
u8 cache_line_size;
|
|
|
|
u32 bar[2];
|
|
|
|
u8 primary_bus;
|
|
|
|
u8 secondary_bus;
|
|
|
|
u8 subordinate_bus;
|
|
|
|
u8 secondary_latency_timer;
|
|
|
|
u8 iobase;
|
|
|
|
u8 iolimit;
|
|
|
|
u16 secondary_status;
|
|
|
|
u16 membase;
|
|
|
|
u16 memlimit;
|
|
|
|
u16 iobaseupper;
|
|
|
|
u16 iolimitupper;
|
|
|
|
u32 romaddr;
|
|
|
|
u8 intline;
|
|
|
|
u8 intpin;
|
|
|
|
u16 bridgectrl;
|
2015-10-04 02:13:33 +08:00
|
|
|
|
|
|
|
/* PCI express capability */
|
|
|
|
u32 pcie_sltcap;
|
|
|
|
u16 pcie_devctl;
|
|
|
|
u16 pcie_rtctl;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct mvebu_pcie_port;
|
|
|
|
|
|
|
|
/* Structure representing all PCIe interfaces */
|
|
|
|
struct mvebu_pcie {
|
|
|
|
struct platform_device *pdev;
|
|
|
|
struct mvebu_pcie_port *ports;
|
2014-11-12 08:45:45 +08:00
|
|
|
struct msi_controller *msi;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
struct resource io;
|
|
|
|
struct resource realio;
|
|
|
|
struct resource mem;
|
|
|
|
struct resource busn;
|
|
|
|
int nports;
|
|
|
|
};
|
|
|
|
|
2016-12-13 02:30:20 +08:00
|
|
|
struct mvebu_pcie_window {
|
|
|
|
phys_addr_t base;
|
|
|
|
phys_addr_t remap;
|
|
|
|
size_t size;
|
|
|
|
};
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/* Structure representing one PCIe interface */
|
|
|
|
struct mvebu_pcie_port {
|
|
|
|
char *name;
|
|
|
|
void __iomem *base;
|
|
|
|
u32 port;
|
|
|
|
u32 lane;
|
|
|
|
int devfn;
|
2013-07-26 21:17:48 +08:00
|
|
|
unsigned int mem_target;
|
|
|
|
unsigned int mem_attr;
|
|
|
|
unsigned int io_target;
|
|
|
|
unsigned int io_attr;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
struct clk *clk;
|
2015-10-04 02:13:22 +08:00
|
|
|
struct gpio_desc *reset_gpio;
|
2013-08-13 20:25:23 +08:00
|
|
|
char *reset_name;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
struct mvebu_sw_pci_bridge bridge;
|
|
|
|
struct device_node *dn;
|
|
|
|
struct mvebu_pcie *pcie;
|
2016-12-13 02:30:20 +08:00
|
|
|
struct mvebu_pcie_window memwin;
|
|
|
|
struct mvebu_pcie_window iowin;
|
2015-03-17 22:55:45 +08:00
|
|
|
u32 saved_pcie_stat;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
};
|
|
|
|
|
2013-10-04 17:58:15 +08:00
|
|
|
static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
|
|
|
|
{
|
|
|
|
writel(val, port->base + reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
|
|
|
|
{
|
|
|
|
return readl(port->base + reg);
|
|
|
|
}
|
|
|
|
|
2013-11-27 02:02:55 +08:00
|
|
|
static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
|
|
|
|
{
|
|
|
|
return port->io_target != -1 && port->io_attr != -1;
|
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
|
|
|
|
{
|
2013-10-04 17:58:15 +08:00
|
|
|
return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
|
|
|
|
{
|
|
|
|
u32 stat;
|
|
|
|
|
2013-10-04 17:58:15 +08:00
|
|
|
stat = mvebu_readl(port, PCIE_STAT_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
stat &= ~PCIE_STAT_BUS;
|
|
|
|
stat |= nr << 8;
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, stat, PCIE_STAT_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:51 +08:00
|
|
|
static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
|
|
|
|
{
|
|
|
|
u32 stat;
|
|
|
|
|
2013-10-04 17:58:15 +08:00
|
|
|
stat = mvebu_readl(port, PCIE_STAT_OFF);
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:51 +08:00
|
|
|
stat &= ~PCIE_STAT_DEV;
|
|
|
|
stat |= nr << 16;
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, stat, PCIE_STAT_OFF);
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:51 +08:00
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/*
|
|
|
|
* Setup PCIE BARs and Address Decode Wins:
|
|
|
|
* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
|
|
|
|
* WIN[0-3] -> DRAM bank[0-3]
|
|
|
|
*/
|
2013-08-13 20:25:22 +08:00
|
|
|
static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
|
|
|
const struct mbus_dram_target_info *dram;
|
|
|
|
u32 size;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dram = mv_mbus_dram_info();
|
|
|
|
|
|
|
|
/* First, disable and clear BARs and windows. */
|
|
|
|
for (i = 1; i < 3; i++) {
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 5; i++) {
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
|
|
|
/* Setup windows for DDR banks. Count total DDR size on the fly. */
|
|
|
|
size = 0;
|
|
|
|
for (i = 0; i < dram->num_cs; i++) {
|
|
|
|
const struct mbus_dram_window *cs = dram->cs + i;
|
|
|
|
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, cs->base & 0xffff0000,
|
|
|
|
PCIE_WIN04_BASE_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
|
|
|
|
mvebu_writel(port,
|
|
|
|
((cs->size - 1) & 0xffff0000) |
|
|
|
|
(cs->mbus_attr << 8) |
|
|
|
|
(dram->mbus_dram_target_id << 4) | 1,
|
|
|
|
PCIE_WIN04_CTRL_OFF(i));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
|
|
|
size += cs->size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Round up 'size' to the nearest power of two. */
|
|
|
|
if ((size & (size - 1)) != 0)
|
|
|
|
size = 1 << fls(size);
|
|
|
|
|
|
|
|
/* Setup BAR[1] to all DRAM banks. */
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
|
|
|
|
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
|
|
|
|
mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
|
|
|
|
PCIE_BAR_CTRL_OFF(1));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
2013-08-13 20:25:22 +08:00
|
|
|
static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
2013-10-04 17:58:15 +08:00
|
|
|
u32 cmd, mask;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
|
|
|
/* Point PCIe unit MBUS decode windows to DRAM space. */
|
|
|
|
mvebu_pcie_setup_wins(port);
|
|
|
|
|
|
|
|
/* Master + slave enable. */
|
2013-10-04 17:58:15 +08:00
|
|
|
cmd = mvebu_readl(port, PCIE_CMD_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
cmd |= PCI_COMMAND_IO;
|
|
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
|
|
cmd |= PCI_COMMAND_MASTER;
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, cmd, PCIE_CMD_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
|
|
|
/* Enable interrupt lines A-D. */
|
2013-10-04 17:58:15 +08:00
|
|
|
mask = mvebu_readl(port, PCIE_MASK_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
mask |= PCIE_MASK_ENABLE_INTS;
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, mask, PCIE_MASK_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
|
|
|
|
struct pci_bus *bus,
|
|
|
|
u32 devfn, int where, int size, u32 *val)
|
|
|
|
{
|
PCI: mvebu: Use exact config access size; don't read/modify/write
The idea that you can arbitarily read 32-bits from PCI configuration space,
modify a sub-field (like the command register) and write it back without
consequence is deeply flawed.
Status registers (such as the status register, PCIe device status register,
etc) contain status bits which are read, write-one-to-clear.
What this means is that reading 32-bits from the command register,
modifying the command register, and then writing it back has the effect of
clearing any status bits that were indicating at that time. Same for the
PCIe device control register clearing bits in the PCIe device status
register.
Since the Armada chips support byte, 16-bit and 32-bit accesses to the
registers (unless otherwise stated) and the PCI configuration data register
does not specify otherwise, it seems logical that the chip can indeed
generate the proper configuration access cycles down to byte level.
Testing with an ASM1062 PCIe to SATA mini-PCIe card on Armada 388. PCIe
capability at 0x80, DevCtl at 0x88, DevSta at 0x8a.
Before:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - Write DevCtl only
/# setpci -s 1:0.0 0x88.l - CorrErr cleared - FAIL
00002810
After:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - check DevCtl only write
/# setpci -s 1:0.0 0x88.l - CorErr remains set
00012810
/# setpci -s 1:0.0 0x88.w=0x281f - check DevCtl write works
/# setpci -s 1:0.0 0x88.l - devctl field updated
0001281f
/# setpci -s 1:0.0 0x8a.w=0xffff - clear DevSta
/# setpci -s 1:0.0 0x88.l - CorrErr now cleared
0000281f
/# setpci -s 1:0.0 0x88.w=0x2810 - restore DevCtl
/# setpci -s 1:0.0 0x88.l - check
00002810
[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2015-09-24 01:17:32 +08:00
|
|
|
void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
|
|
|
|
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
|
|
|
|
PCIE_CONF_ADDR_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
PCI: mvebu: Use exact config access size; don't read/modify/write
The idea that you can arbitarily read 32-bits from PCI configuration space,
modify a sub-field (like the command register) and write it back without
consequence is deeply flawed.
Status registers (such as the status register, PCIe device status register,
etc) contain status bits which are read, write-one-to-clear.
What this means is that reading 32-bits from the command register,
modifying the command register, and then writing it back has the effect of
clearing any status bits that were indicating at that time. Same for the
PCIe device control register clearing bits in the PCIe device status
register.
Since the Armada chips support byte, 16-bit and 32-bit accesses to the
registers (unless otherwise stated) and the PCI configuration data register
does not specify otherwise, it seems logical that the chip can indeed
generate the proper configuration access cycles down to byte level.
Testing with an ASM1062 PCIe to SATA mini-PCIe card on Armada 388. PCIe
capability at 0x80, DevCtl at 0x88, DevSta at 0x8a.
Before:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - Write DevCtl only
/# setpci -s 1:0.0 0x88.l - CorrErr cleared - FAIL
00002810
After:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - check DevCtl only write
/# setpci -s 1:0.0 0x88.l - CorErr remains set
00012810
/# setpci -s 1:0.0 0x88.w=0x281f - check DevCtl write works
/# setpci -s 1:0.0 0x88.l - devctl field updated
0001281f
/# setpci -s 1:0.0 0x8a.w=0xffff - clear DevSta
/# setpci -s 1:0.0 0x88.l - CorrErr now cleared
0000281f
/# setpci -s 1:0.0 0x88.w=0x2810 - restore DevCtl
/# setpci -s 1:0.0 0x88.l - check
00002810
[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2015-09-24 01:17:32 +08:00
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
*val = readb_relaxed(conf_data + (where & 3));
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
*val = readw_relaxed(conf_data + (where & 2));
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
*val = readl_relaxed(conf_data);
|
|
|
|
break;
|
|
|
|
}
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
|
|
|
|
struct pci_bus *bus,
|
|
|
|
u32 devfn, int where, int size, u32 val)
|
|
|
|
{
|
PCI: mvebu: Use exact config access size; don't read/modify/write
The idea that you can arbitarily read 32-bits from PCI configuration space,
modify a sub-field (like the command register) and write it back without
consequence is deeply flawed.
Status registers (such as the status register, PCIe device status register,
etc) contain status bits which are read, write-one-to-clear.
What this means is that reading 32-bits from the command register,
modifying the command register, and then writing it back has the effect of
clearing any status bits that were indicating at that time. Same for the
PCIe device control register clearing bits in the PCIe device status
register.
Since the Armada chips support byte, 16-bit and 32-bit accesses to the
registers (unless otherwise stated) and the PCI configuration data register
does not specify otherwise, it seems logical that the chip can indeed
generate the proper configuration access cycles down to byte level.
Testing with an ASM1062 PCIe to SATA mini-PCIe card on Armada 388. PCIe
capability at 0x80, DevCtl at 0x88, DevSta at 0x8a.
Before:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - Write DevCtl only
/# setpci -s 1:0.0 0x88.l - CorrErr cleared - FAIL
00002810
After:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - check DevCtl only write
/# setpci -s 1:0.0 0x88.l - CorErr remains set
00012810
/# setpci -s 1:0.0 0x88.w=0x281f - check DevCtl write works
/# setpci -s 1:0.0 0x88.l - devctl field updated
0001281f
/# setpci -s 1:0.0 0x8a.w=0xffff - clear DevSta
/# setpci -s 1:0.0 0x88.l - CorrErr now cleared
0000281f
/# setpci -s 1:0.0 0x88.w=0x2810 - restore DevCtl
/# setpci -s 1:0.0 0x88.l - check
00002810
[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2015-09-24 01:17:32 +08:00
|
|
|
void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2013-10-04 17:58:15 +08:00
|
|
|
mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
|
|
|
|
PCIE_CONF_ADDR_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
PCI: mvebu: Use exact config access size; don't read/modify/write
The idea that you can arbitarily read 32-bits from PCI configuration space,
modify a sub-field (like the command register) and write it back without
consequence is deeply flawed.
Status registers (such as the status register, PCIe device status register,
etc) contain status bits which are read, write-one-to-clear.
What this means is that reading 32-bits from the command register,
modifying the command register, and then writing it back has the effect of
clearing any status bits that were indicating at that time. Same for the
PCIe device control register clearing bits in the PCIe device status
register.
Since the Armada chips support byte, 16-bit and 32-bit accesses to the
registers (unless otherwise stated) and the PCI configuration data register
does not specify otherwise, it seems logical that the chip can indeed
generate the proper configuration access cycles down to byte level.
Testing with an ASM1062 PCIe to SATA mini-PCIe card on Armada 388. PCIe
capability at 0x80, DevCtl at 0x88, DevSta at 0x8a.
Before:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - Write DevCtl only
/# setpci -s 1:0.0 0x88.l - CorrErr cleared - FAIL
00002810
After:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - check DevCtl only write
/# setpci -s 1:0.0 0x88.l - CorErr remains set
00012810
/# setpci -s 1:0.0 0x88.w=0x281f - check DevCtl write works
/# setpci -s 1:0.0 0x88.l - devctl field updated
0001281f
/# setpci -s 1:0.0 0x8a.w=0xffff - clear DevSta
/# setpci -s 1:0.0 0x88.l - CorrErr now cleared
0000281f
/# setpci -s 1:0.0 0x88.w=0x2810 - restore DevCtl
/# setpci -s 1:0.0 0x88.l - check
00002810
[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2015-09-24 01:17:32 +08:00
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
writeb(val, conf_data + (where & 3));
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
writew(val, conf_data + (where & 2));
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
writel(val, conf_data);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
}
|
2013-10-04 17:58:15 +08:00
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
2014-04-18 20:19:53 +08:00
|
|
|
/*
|
|
|
|
* Remove windows, starting from the largest ones to the smallest
|
|
|
|
* ones.
|
|
|
|
*/
|
|
|
|
static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
|
|
|
|
phys_addr_t base, size_t size)
|
|
|
|
{
|
|
|
|
while (size) {
|
|
|
|
size_t sz = 1 << (fls(size) - 1);
|
|
|
|
|
|
|
|
mvebu_mbus_del_window(base, sz);
|
|
|
|
base += sz;
|
|
|
|
size -= sz;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* MBus windows can only have a power of two size, but PCI BARs do not
|
|
|
|
* have this constraint. Therefore, we have to split the PCI BAR into
|
|
|
|
* areas each having a power of two size. We start from the largest
|
|
|
|
* one (i.e highest order bit set in the size).
|
|
|
|
*/
|
|
|
|
static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
|
|
|
|
unsigned int target, unsigned int attribute,
|
|
|
|
phys_addr_t base, size_t size,
|
|
|
|
phys_addr_t remap)
|
|
|
|
{
|
|
|
|
size_t size_mapped = 0;
|
|
|
|
|
|
|
|
while (size) {
|
|
|
|
size_t sz = 1 << (fls(size) - 1);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
|
|
|
|
sz, remap);
|
|
|
|
if (ret) {
|
2014-04-29 20:58:07 +08:00
|
|
|
phys_addr_t end = base + sz - 1;
|
|
|
|
|
2014-04-18 20:19:53 +08:00
|
|
|
dev_err(&port->pcie->pdev->dev,
|
2014-04-29 20:58:07 +08:00
|
|
|
"Could not create MBus window at [mem %pa-%pa]: %d\n",
|
|
|
|
&base, &end, ret);
|
2014-04-18 20:19:53 +08:00
|
|
|
mvebu_pcie_del_windows(port, base - size_mapped,
|
|
|
|
size_mapped);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
size -= sz;
|
|
|
|
size_mapped += sz;
|
|
|
|
base += sz;
|
|
|
|
if (remap != MVEBU_MBUS_NO_REMAP)
|
|
|
|
remap += sz;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-12-13 02:30:20 +08:00
|
|
|
static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
|
|
|
|
unsigned int target, unsigned int attribute,
|
|
|
|
const struct mvebu_pcie_window *desired,
|
|
|
|
struct mvebu_pcie_window *cur)
|
|
|
|
{
|
|
|
|
if (desired->base == cur->base && desired->remap == cur->remap &&
|
|
|
|
desired->size == cur->size)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (cur->size != 0) {
|
|
|
|
mvebu_pcie_del_windows(port, cur->base, cur->size);
|
|
|
|
cur->size = 0;
|
|
|
|
cur->base = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If something tries to change the window while it is enabled
|
|
|
|
* the change will not be done atomically. That would be
|
|
|
|
* difficult to do in the general case.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
if (desired->size == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
mvebu_pcie_add_windows(port, target, attribute, desired->base,
|
|
|
|
desired->size, desired->remap);
|
|
|
|
*cur = *desired;
|
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
|
|
|
|
{
|
2016-12-13 02:30:20 +08:00
|
|
|
struct mvebu_pcie_window desired = {};
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
|
|
|
/* Are the new iobase/iolimit values invalid? */
|
|
|
|
if (port->bridge.iolimit < port->bridge.iobase ||
|
2013-11-27 02:02:54 +08:00
|
|
|
port->bridge.iolimitupper < port->bridge.iobaseupper ||
|
|
|
|
!(port->bridge.command & PCI_COMMAND_IO)) {
|
2016-12-13 02:30:20 +08:00
|
|
|
mvebu_pcie_set_window(port, port->io_target, port->io_attr,
|
|
|
|
&desired, &port->iowin);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-11-27 02:02:55 +08:00
|
|
|
if (!mvebu_has_ioport(port)) {
|
|
|
|
dev_WARN(&port->pcie->pdev->dev,
|
|
|
|
"Attempt to set IO when IO is disabled\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/*
|
|
|
|
* We read the PCI-to-PCI bridge emulated registers, and
|
|
|
|
* calculate the base address and size of the address decoding
|
|
|
|
* window to setup, according to the PCI-to-PCI bridge
|
|
|
|
* specifications. iobase is the bus address, port->iowin_base
|
|
|
|
* is the CPU address.
|
|
|
|
*/
|
2016-12-13 02:30:20 +08:00
|
|
|
desired.remap = ((port->bridge.iobase & 0xF0) << 8) |
|
|
|
|
(port->bridge.iobaseupper << 16);
|
|
|
|
desired.base = port->pcie->io.start + desired.remap;
|
|
|
|
desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
|
|
|
|
(port->bridge.iolimitupper << 16)) -
|
|
|
|
desired.remap) +
|
|
|
|
1;
|
|
|
|
|
|
|
|
mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
|
|
|
|
&port->iowin);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
|
|
|
|
{
|
2016-12-13 02:30:20 +08:00
|
|
|
struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/* Are the new membase/memlimit values invalid? */
|
2013-11-27 02:02:54 +08:00
|
|
|
if (port->bridge.memlimit < port->bridge.membase ||
|
|
|
|
!(port->bridge.command & PCI_COMMAND_MEMORY)) {
|
2016-12-13 02:30:20 +08:00
|
|
|
mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
|
|
|
|
&desired, &port->memwin);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We read the PCI-to-PCI bridge emulated registers, and
|
|
|
|
* calculate the base address and size of the address decoding
|
|
|
|
* window to setup, according to the PCI-to-PCI bridge
|
|
|
|
* specifications.
|
|
|
|
*/
|
2016-12-13 02:30:20 +08:00
|
|
|
desired.base = ((port->bridge.membase & 0xFFF0) << 16);
|
|
|
|
desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
|
|
|
|
desired.base + 1;
|
|
|
|
|
|
|
|
mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
|
|
|
|
&port->memwin);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the configuration space of the PCI-to-PCI bridge
|
|
|
|
* associated with the given PCIe interface.
|
|
|
|
*/
|
|
|
|
static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
|
|
|
|
{
|
|
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
|
|
|
|
|
|
memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
|
|
|
|
|
|
|
|
bridge->class = PCI_CLASS_BRIDGE_PCI;
|
|
|
|
bridge->vendor = PCI_VENDOR_ID_MARVELL;
|
2014-02-05 18:55:49 +08:00
|
|
|
bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
|
|
|
|
bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
|
|
|
|
bridge->cache_line_size = 0x10;
|
|
|
|
|
|
|
|
/* We support 32 bits I/O addressing */
|
|
|
|
bridge->iobase = PCI_IO_RANGE_TYPE_32;
|
|
|
|
bridge->iolimit = PCI_IO_RANGE_TYPE_32;
|
2015-10-04 02:13:33 +08:00
|
|
|
|
|
|
|
/* Add capabilities */
|
|
|
|
bridge->status = PCI_STATUS_CAP_LIST;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read the configuration space of the PCI-to-PCI bridge associated to
|
|
|
|
* the given PCIe interface.
|
|
|
|
*/
|
|
|
|
static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
|
|
|
|
unsigned int where, int size, u32 *value)
|
|
|
|
{
|
|
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
|
|
|
|
|
|
switch (where & ~3) {
|
|
|
|
case PCI_VENDOR_ID:
|
|
|
|
*value = bridge->device << 16 | bridge->vendor;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_COMMAND:
|
2015-10-04 02:13:33 +08:00
|
|
|
*value = bridge->command | bridge->status << 16;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_CLASS_REVISION:
|
|
|
|
*value = bridge->class << 16 | bridge->interface << 8 |
|
|
|
|
bridge->revision;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_CACHE_LINE_SIZE:
|
|
|
|
*value = bridge->bist << 24 | bridge->header_type << 16 |
|
|
|
|
bridge->latency_timer << 8 | bridge->cache_line_size;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
|
|
|
|
*value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_PRIMARY_BUS:
|
|
|
|
*value = (bridge->secondary_latency_timer << 24 |
|
|
|
|
bridge->subordinate_bus << 16 |
|
|
|
|
bridge->secondary_bus << 8 |
|
|
|
|
bridge->primary_bus);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE:
|
2013-11-27 02:02:55 +08:00
|
|
|
if (!mvebu_has_ioport(port))
|
|
|
|
*value = bridge->secondary_status << 16;
|
|
|
|
else
|
|
|
|
*value = (bridge->secondary_status << 16 |
|
|
|
|
bridge->iolimit << 8 |
|
|
|
|
bridge->iobase);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_MEMORY_BASE:
|
|
|
|
*value = (bridge->memlimit << 16 | bridge->membase);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_PREF_MEMORY_BASE:
|
2013-08-01 21:44:19 +08:00
|
|
|
*value = 0;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE_UPPER16:
|
|
|
|
*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
|
|
|
|
break;
|
|
|
|
|
2015-10-04 02:13:33 +08:00
|
|
|
case PCI_CAPABILITY_LIST:
|
|
|
|
*value = PCISWCAP;
|
|
|
|
break;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
case PCI_ROM_ADDRESS1:
|
|
|
|
*value = 0;
|
|
|
|
break;
|
|
|
|
|
2013-11-27 02:27:28 +08:00
|
|
|
case PCI_INTERRUPT_LINE:
|
|
|
|
/* LINE PIN MIN_GNT MAX_LAT */
|
|
|
|
*value = 0;
|
|
|
|
break;
|
|
|
|
|
2015-10-04 02:13:33 +08:00
|
|
|
case PCISWCAP_EXP_LIST_ID:
|
|
|
|
/* Set PCIe v2, root port, slot support */
|
|
|
|
*value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
|
|
|
|
PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_DEVCAP:
|
|
|
|
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_DEVCTL:
|
|
|
|
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
|
|
|
|
~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
|
|
|
|
PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
|
|
|
|
*value |= bridge->pcie_devctl;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_LNKCAP:
|
|
|
|
/*
|
|
|
|
* PCIe requires the clock power management capability to be
|
|
|
|
* hard-wired to zero for downstream ports
|
|
|
|
*/
|
|
|
|
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
|
|
|
|
~PCI_EXP_LNKCAP_CLKPM;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_LNKCTL:
|
|
|
|
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_SLTCAP:
|
|
|
|
*value = bridge->pcie_sltcap;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_SLTCTL:
|
|
|
|
*value = PCI_EXP_SLTSTA_PDS << 16;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_RTCTL:
|
|
|
|
*value = bridge->pcie_rtctl;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_RTSTA:
|
|
|
|
*value = mvebu_readl(port, PCIE_RC_RTSTA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* PCIe requires the v2 fields to be hard-wired to zero */
|
|
|
|
case PCISWCAP_EXP_DEVCAP2:
|
|
|
|
case PCISWCAP_EXP_DEVCTL2:
|
|
|
|
case PCISWCAP_EXP_LNKCAP2:
|
|
|
|
case PCISWCAP_EXP_LNKCTL2:
|
|
|
|
case PCISWCAP_EXP_SLTCAP2:
|
|
|
|
case PCISWCAP_EXP_SLTCTL2:
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
default:
|
2015-09-24 01:17:26 +08:00
|
|
|
/*
|
|
|
|
* PCI defines configuration read accesses to reserved or
|
|
|
|
* unimplemented registers to read as zero and complete
|
|
|
|
* normally.
|
|
|
|
*/
|
|
|
|
*value = 0;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (size == 2)
|
|
|
|
*value = (*value >> (8 * (where & 3))) & 0xffff;
|
|
|
|
else if (size == 1)
|
|
|
|
*value = (*value >> (8 * (where & 3))) & 0xff;
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write to the PCI-to-PCI bridge configuration space */
|
|
|
|
static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
|
|
|
|
unsigned int where, int size, u32 value)
|
|
|
|
{
|
|
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
|
|
u32 mask, reg;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (size == 4)
|
|
|
|
mask = 0x0;
|
|
|
|
else if (size == 2)
|
|
|
|
mask = ~(0xffff << ((where & 3) * 8));
|
|
|
|
else if (size == 1)
|
|
|
|
mask = ~(0xff << ((where & 3) * 8));
|
|
|
|
else
|
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
|
|
|
|
err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
value = (reg & mask) | value << ((where & 3) * 8);
|
|
|
|
|
|
|
|
switch (where & ~3) {
|
|
|
|
case PCI_COMMAND:
|
2013-11-27 02:02:54 +08:00
|
|
|
{
|
|
|
|
u32 old = bridge->command;
|
|
|
|
|
2013-11-27 02:02:55 +08:00
|
|
|
if (!mvebu_has_ioport(port))
|
|
|
|
value &= ~PCI_COMMAND_IO;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
bridge->command = value & 0xffff;
|
2013-11-27 02:02:54 +08:00
|
|
|
if ((old ^ bridge->command) & PCI_COMMAND_IO)
|
|
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
|
|
if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
|
|
|
|
mvebu_pcie_handle_membase_change(port);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
break;
|
2013-11-27 02:02:54 +08:00
|
|
|
}
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
|
|
|
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
|
|
|
|
bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE:
|
|
|
|
/*
|
|
|
|
* We also keep bit 1 set, it is a read-only bit that
|
|
|
|
* indicates we support 32 bits addressing for the
|
|
|
|
* I/O
|
|
|
|
*/
|
|
|
|
bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
|
|
|
|
bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
|
|
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_MEMORY_BASE:
|
|
|
|
bridge->membase = value & 0xffff;
|
|
|
|
bridge->memlimit = value >> 16;
|
|
|
|
mvebu_pcie_handle_membase_change(port);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE_UPPER16:
|
|
|
|
bridge->iobaseupper = value & 0xffff;
|
|
|
|
bridge->iolimitupper = value >> 16;
|
|
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_PRIMARY_BUS:
|
|
|
|
bridge->primary_bus = value & 0xff;
|
|
|
|
bridge->secondary_bus = (value >> 8) & 0xff;
|
|
|
|
bridge->subordinate_bus = (value >> 16) & 0xff;
|
|
|
|
bridge->secondary_latency_timer = (value >> 24) & 0xff;
|
|
|
|
mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
|
|
|
|
break;
|
|
|
|
|
2015-10-04 02:13:33 +08:00
|
|
|
case PCISWCAP_EXP_DEVCTL:
|
|
|
|
/*
|
|
|
|
* Armada370 data says these bits must always
|
|
|
|
* be zero when in root complex mode.
|
|
|
|
*/
|
|
|
|
value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
|
|
|
|
PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the mask is 0xffff0000, then we only want to write
|
|
|
|
* the device control register, rather than clearing the
|
|
|
|
* RW1C bits in the device status register. Mask out the
|
|
|
|
* status register bits.
|
|
|
|
*/
|
|
|
|
if (mask == 0xffff0000)
|
|
|
|
value &= 0xffff;
|
|
|
|
|
|
|
|
mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_LNKCTL:
|
|
|
|
/*
|
|
|
|
* If we don't support CLKREQ, we must ensure that the
|
|
|
|
* CLKREQ enable bit always reads zero. Since we haven't
|
|
|
|
* had this capability, and it's dependent on board wiring,
|
|
|
|
* disable it for the time being.
|
|
|
|
*/
|
|
|
|
value &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the mask is 0xffff0000, then we only want to write
|
|
|
|
* the link control register, rather than clearing the
|
|
|
|
* RW1C bits in the link status register. Mask out the
|
2017-01-18 05:40:52 +08:00
|
|
|
* RW1C status register bits.
|
2015-10-04 02:13:33 +08:00
|
|
|
*/
|
|
|
|
if (mask == 0xffff0000)
|
2017-01-18 05:40:52 +08:00
|
|
|
value &= ~((PCI_EXP_LNKSTA_LABS |
|
|
|
|
PCI_EXP_LNKSTA_LBMS) << 16);
|
2015-10-04 02:13:33 +08:00
|
|
|
|
|
|
|
mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCISWCAP_EXP_RTSTA:
|
|
|
|
mvebu_writel(port, value, PCIE_RC_RTSTA);
|
|
|
|
break;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
|
|
|
|
{
|
|
|
|
return sys->private_data;
|
|
|
|
}
|
|
|
|
|
2014-04-19 08:13:49 +08:00
|
|
|
static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
|
|
|
|
struct pci_bus *bus,
|
|
|
|
int devfn)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
2014-11-12 11:27:54 +08:00
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
if (bus->number == 0 && port->devfn == devfn)
|
|
|
|
return port;
|
|
|
|
if (bus->number != 0 &&
|
pci: mvebu: allow the enumeration of devices beyond physical bridges
Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.
However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.
This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.
Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:
-[0000:00]-+-01.0-[01]----00.0
+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
| +-05.0-[05]--
| +-07.0-[06]--
| \-09.0-[07]----00.0
\-0a.0-[08]----00.0
Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:52 +08:00
|
|
|
bus->number >= port->bridge.secondary_bus &&
|
|
|
|
bus->number <= port->bridge.subordinate_bus)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
return port;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCI configuration space write function */
|
|
|
|
static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
|
|
int where, int size, u32 val)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
|
|
|
|
struct mvebu_pcie_port *port;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
|
|
|
if (!port)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
|
|
|
/* Access the emulated PCI-to-PCI bridge */
|
|
|
|
if (bus->number == 0)
|
|
|
|
return mvebu_sw_pci_bridge_write(port, where, size, val);
|
|
|
|
|
2013-10-02 01:58:00 +08:00
|
|
|
if (!mvebu_pcie_link_up(port))
|
pci: mvebu: allow the enumeration of devices beyond physical bridges
Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.
However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.
This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.
Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:
-[0000:00]-+-01.0-[01]----00.0
+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
| +-05.0-[05]--
| +-07.0-[06]--
| \-09.0-[07]----00.0
\-0a.0-[08]----00.0
Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:52 +08:00
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/* Access the real PCIe interface */
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:51 +08:00
|
|
|
ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
where, size, val);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCI configuration space read function */
|
|
|
|
static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
|
|
int size, u32 *val)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
|
|
|
|
struct mvebu_pcie_port *port;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
|
|
|
if (!port) {
|
|
|
|
*val = 0xffffffff;
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Access the emulated PCI-to-PCI bridge */
|
|
|
|
if (bus->number == 0)
|
|
|
|
return mvebu_sw_pci_bridge_read(port, where, size, val);
|
|
|
|
|
2013-10-02 01:58:00 +08:00
|
|
|
if (!mvebu_pcie_link_up(port)) {
|
pci: mvebu: allow the enumeration of devices beyond physical bridges
Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.
However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.
This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.
Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:
-[0000:00]-+-01.0-[01]----00.0
+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
| +-05.0-[05]--
| +-07.0-[06]--
| \-09.0-[07]----00.0
\-0a.0-[08]----00.0
Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:52 +08:00
|
|
|
*val = 0xffffffff;
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/* Access the real PCIe interface */
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:51 +08:00
|
|
|
ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
where, size, val);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_ops mvebu_pcie_ops = {
|
|
|
|
.read = mvebu_pcie_rd_conf,
|
|
|
|
.write = mvebu_pcie_wr_conf,
|
|
|
|
};
|
|
|
|
|
2013-08-13 20:25:22 +08:00
|
|
|
static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(sys);
|
2016-06-07 04:35:39 +08:00
|
|
|
int err, i;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2014-11-21 19:29:26 +08:00
|
|
|
pcie->mem.name = "PCI MEM";
|
|
|
|
pcie->realio.name = "PCI I/O";
|
2014-02-13 06:57:08 +08:00
|
|
|
|
2016-06-07 04:35:39 +08:00
|
|
|
if (resource_size(&pcie->realio) != 0)
|
2013-11-27 02:02:55 +08:00
|
|
|
pci_add_resource_offset(&sys->resources, &pcie->realio,
|
|
|
|
sys->io_offset);
|
2016-06-07 04:35:39 +08:00
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
|
|
|
|
pci_add_resource(&sys->resources, &pcie->busn);
|
|
|
|
|
2016-06-07 04:35:39 +08:00
|
|
|
err = devm_request_pci_bus_resources(&pcie->pdev->dev, &sys->resources);
|
|
|
|
if (err)
|
|
|
|
return 0;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
2014-11-12 11:27:54 +08:00
|
|
|
|
2013-07-26 21:17:49 +08:00
|
|
|
if (!port->base)
|
|
|
|
continue;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
mvebu_pcie_setup_hw(port);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2013-09-17 13:26:46 +08:00
|
|
|
static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
|
2014-04-19 08:13:49 +08:00
|
|
|
const struct resource *res,
|
|
|
|
resource_size_t start,
|
|
|
|
resource_size_t size,
|
|
|
|
resource_size_t align)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
|
|
|
if (dev->bus->number != 0)
|
|
|
|
return start;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On the PCI-to-PCI bridge side, the I/O windows must have at
|
2014-04-18 20:19:53 +08:00
|
|
|
* least a 64 KB size and the memory windows must have at
|
|
|
|
* least a 1 MB size. Moreover, MBus windows need to have a
|
|
|
|
* base address aligned on their size, and their size must be
|
|
|
|
* a power of two. This means that if the BAR doesn't have a
|
|
|
|
* power of two size, several MBus windows will actually be
|
|
|
|
* created. We need to ensure that the biggest MBus window
|
|
|
|
* (which will be the first one) is aligned on its size, which
|
|
|
|
* explains the rounddown_pow_of_two() being done here.
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
*/
|
|
|
|
if (res->flags & IORESOURCE_IO)
|
2014-04-18 20:19:53 +08:00
|
|
|
return round_up(start, max_t(resource_size_t, SZ_64K,
|
|
|
|
rounddown_pow_of_two(size)));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
else if (res->flags & IORESOURCE_MEM)
|
2014-04-18 20:19:53 +08:00
|
|
|
return round_up(start, max_t(resource_size_t, SZ_1M,
|
|
|
|
rounddown_pow_of_two(size)));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
else
|
|
|
|
return start;
|
|
|
|
}
|
|
|
|
|
2013-08-13 20:25:22 +08:00
|
|
|
static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
|
|
|
struct hw_pci hw;
|
|
|
|
|
|
|
|
memset(&hw, 0, sizeof(hw));
|
|
|
|
|
2014-11-12 06:44:17 +08:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
hw.msi_ctrl = pcie->msi;
|
|
|
|
#endif
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
hw.nr_controllers = 1;
|
|
|
|
hw.private_data = (void **)&pcie;
|
|
|
|
hw.setup = mvebu_pcie_setup;
|
2013-09-20 05:44:55 +08:00
|
|
|
hw.map_irq = of_irq_parse_and_map_pci;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
hw.ops = &mvebu_pcie_ops;
|
|
|
|
hw.align_resource = mvebu_pcie_align_resource;
|
|
|
|
|
2015-04-28 15:01:35 +08:00
|
|
|
pci_common_init_dev(&pcie->pdev->dev, &hw);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Looks up the list of register addresses encoded into the reg =
|
|
|
|
* <...> property for one that matches the given port/lane. Once
|
|
|
|
* found, maps it.
|
|
|
|
*/
|
2013-08-13 20:25:22 +08:00
|
|
|
static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
|
2014-04-19 08:13:49 +08:00
|
|
|
struct device_node *np,
|
|
|
|
struct mvebu_pcie_port *port)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
|
|
|
struct resource regs;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = of_address_to_resource(np, 0, ®s);
|
|
|
|
if (ret)
|
2013-06-17 17:16:13 +08:00
|
|
|
return ERR_PTR(ret);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2013-06-17 17:16:13 +08:00
|
|
|
return devm_ioremap_resource(&pdev->dev, ®s);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
}
|
|
|
|
|
2013-07-26 21:17:48 +08:00
|
|
|
#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
|
|
|
|
#define DT_TYPE_IO 0x1
|
|
|
|
#define DT_TYPE_MEM32 0x2
|
|
|
|
#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
|
|
|
|
#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
|
|
|
|
|
|
|
|
static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
|
2013-11-27 02:02:55 +08:00
|
|
|
unsigned long type,
|
|
|
|
unsigned int *tgt,
|
|
|
|
unsigned int *attr)
|
2013-07-26 21:17:48 +08:00
|
|
|
{
|
|
|
|
const int na = 3, ns = 2;
|
|
|
|
const __be32 *range;
|
|
|
|
int rlen, nranges, rangesz, pna, i;
|
|
|
|
|
2013-11-27 02:02:55 +08:00
|
|
|
*tgt = -1;
|
|
|
|
*attr = -1;
|
|
|
|
|
2013-07-26 21:17:48 +08:00
|
|
|
range = of_get_property(np, "ranges", &rlen);
|
|
|
|
if (!range)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pna = of_n_addr_cells(np);
|
|
|
|
rangesz = pna + na + ns;
|
|
|
|
nranges = rlen / sizeof(__be32) / rangesz;
|
|
|
|
|
2014-09-17 23:58:27 +08:00
|
|
|
for (i = 0; i < nranges; i++, range += rangesz) {
|
2013-07-26 21:17:48 +08:00
|
|
|
u32 flags = of_read_number(range, 1);
|
2014-02-15 02:46:15 +08:00
|
|
|
u32 slot = of_read_number(range + 1, 1);
|
2013-07-26 21:17:48 +08:00
|
|
|
u64 cpuaddr = of_read_number(range + na, pna);
|
|
|
|
unsigned long rtype;
|
|
|
|
|
|
|
|
if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
|
|
|
|
rtype = IORESOURCE_IO;
|
|
|
|
else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
|
|
|
|
rtype = IORESOURCE_MEM;
|
2014-09-17 23:58:27 +08:00
|
|
|
else
|
|
|
|
continue;
|
2013-07-26 21:17:48 +08:00
|
|
|
|
|
|
|
if (slot == PCI_SLOT(devfn) && type == rtype) {
|
|
|
|
*tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
|
|
|
|
*attr = DT_CPUADDR_TO_ATTR(cpuaddr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
2016-03-16 17:59:41 +08:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2015-03-17 22:55:45 +08:00
|
|
|
static int mvebu_pcie_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
pcie = dev_get_drvdata(dev);
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
|
|
struct mvebu_pcie_port *port = pcie->ports + i;
|
|
|
|
port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mvebu_pcie_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
pcie = dev_get_drvdata(dev);
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
|
|
struct mvebu_pcie_port *port = pcie->ports + i;
|
|
|
|
mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
|
|
|
|
mvebu_pcie_setup_hw(port);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2016-03-16 17:59:41 +08:00
|
|
|
#endif
|
2015-03-17 22:55:45 +08:00
|
|
|
|
2015-10-04 02:13:02 +08:00
|
|
|
static void mvebu_pcie_port_clk_put(void *data)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie_port *port = data;
|
|
|
|
|
|
|
|
clk_put(port->clk);
|
|
|
|
}
|
|
|
|
|
2015-10-04 02:12:57 +08:00
|
|
|
static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
|
|
|
|
struct mvebu_pcie_port *port, struct device_node *child)
|
|
|
|
{
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
|
|
|
enum of_gpio_flags flags;
|
2015-10-04 02:13:22 +08:00
|
|
|
int reset_gpio, ret;
|
2015-10-04 02:12:57 +08:00
|
|
|
|
|
|
|
port->pcie = pcie;
|
|
|
|
|
|
|
|
if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
|
|
|
|
dev_warn(dev, "ignoring %s, missing pcie-port property\n",
|
|
|
|
of_node_full_name(child));
|
|
|
|
goto skip;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
|
|
|
|
port->lane = 0;
|
|
|
|
|
2015-10-04 02:13:02 +08:00
|
|
|
port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
|
|
|
|
port->lane);
|
|
|
|
if (!port->name) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
2015-10-04 02:12:57 +08:00
|
|
|
|
|
|
|
port->devfn = of_pci_get_devfn(child);
|
|
|
|
if (port->devfn < 0)
|
|
|
|
goto skip;
|
|
|
|
|
|
|
|
ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
|
|
|
|
&port->mem_target, &port->mem_attr);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
|
|
|
|
port->name);
|
|
|
|
goto skip;
|
|
|
|
}
|
|
|
|
|
2015-10-04 02:13:02 +08:00
|
|
|
if (resource_size(&pcie->io) != 0) {
|
2015-10-04 02:12:57 +08:00
|
|
|
mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
|
|
|
|
&port->io_target, &port->io_attr);
|
2015-10-04 02:13:02 +08:00
|
|
|
} else {
|
2015-10-04 02:12:57 +08:00
|
|
|
port->io_target = -1;
|
|
|
|
port->io_attr = -1;
|
|
|
|
}
|
|
|
|
|
2015-10-04 02:13:22 +08:00
|
|
|
reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
|
|
|
|
if (reset_gpio == -EPROBE_DEFER) {
|
|
|
|
ret = reset_gpio;
|
2015-10-04 02:13:02 +08:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2015-10-04 02:13:22 +08:00
|
|
|
if (gpio_is_valid(reset_gpio)) {
|
|
|
|
unsigned long gpio_flags;
|
|
|
|
|
2015-10-04 02:13:02 +08:00
|
|
|
port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
|
|
|
|
port->name);
|
|
|
|
if (!port->reset_name) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
2015-10-04 02:12:57 +08:00
|
|
|
|
2015-10-04 02:13:22 +08:00
|
|
|
if (flags & OF_GPIO_ACTIVE_LOW) {
|
|
|
|
dev_info(dev, "%s: reset gpio is active low\n",
|
|
|
|
of_node_full_name(child));
|
|
|
|
gpio_flags = GPIOF_ACTIVE_LOW |
|
|
|
|
GPIOF_OUT_INIT_LOW;
|
|
|
|
} else {
|
|
|
|
gpio_flags = GPIOF_OUT_INIT_HIGH;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags,
|
|
|
|
port->reset_name);
|
2015-10-04 02:12:57 +08:00
|
|
|
if (ret) {
|
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
goto err;
|
|
|
|
goto skip;
|
|
|
|
}
|
2015-10-04 02:13:22 +08:00
|
|
|
|
|
|
|
port->reset_gpio = gpio_to_desc(reset_gpio);
|
2015-10-04 02:12:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
port->clk = of_clk_get_by_name(child, NULL);
|
|
|
|
if (IS_ERR(port->clk)) {
|
|
|
|
dev_err(dev, "%s: cannot get clock\n", port->name);
|
|
|
|
goto skip;
|
|
|
|
}
|
|
|
|
|
2015-10-04 02:13:02 +08:00
|
|
|
ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
|
|
|
|
if (ret < 0) {
|
|
|
|
clk_put(port->clk);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2015-10-04 02:12:57 +08:00
|
|
|
return 1;
|
|
|
|
|
|
|
|
skip:
|
|
|
|
ret = 0;
|
2015-10-04 02:13:02 +08:00
|
|
|
|
|
|
|
/* In the case of skipping, we need to free these */
|
|
|
|
devm_kfree(dev, port->reset_name);
|
|
|
|
port->reset_name = NULL;
|
|
|
|
devm_kfree(dev, port->name);
|
|
|
|
port->name = NULL;
|
|
|
|
|
2015-10-04 02:12:57 +08:00
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-10-04 02:13:27 +08:00
|
|
|
/*
|
|
|
|
* Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
|
|
|
|
* prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
|
|
|
|
* of the PCI Express Card Electromechanical Specification, 1.1.
|
|
|
|
*/
|
|
|
|
static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(port->clk);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (port->reset_gpio) {
|
2017-02-03 01:15:31 +08:00
|
|
|
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
|
2015-10-04 02:13:27 +08:00
|
|
|
|
|
|
|
of_property_read_u32(port->dn, "reset-delay-us",
|
|
|
|
&reset_udelay);
|
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
|
|
|
gpiod_set_value_cansleep(port->reset_gpio, 0);
|
|
|
|
msleep(reset_udelay / 1000);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Power down a PCIe port. Strictly, PCIe requires us to place the card
|
|
|
|
* in D3hot state before asserting PERST#.
|
|
|
|
*/
|
|
|
|
static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
|
|
|
|
{
|
|
|
|
if (port->reset_gpio)
|
|
|
|
gpiod_set_value_cansleep(port->reset_gpio, 1);
|
|
|
|
|
|
|
|
clk_disable_unprepare(port->clk);
|
|
|
|
}
|
|
|
|
|
2013-08-13 20:25:22 +08:00
|
|
|
static int mvebu_pcie_probe(struct platform_device *pdev)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{
|
2016-10-07 02:38:58 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
struct mvebu_pcie *pcie;
|
2016-10-07 02:38:58 +08:00
|
|
|
struct device_node *np = dev->of_node;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
struct device_node *child;
|
2015-09-24 01:17:37 +08:00
|
|
|
int num, i, ret;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2016-10-07 02:38:58 +08:00
|
|
|
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
if (!pcie)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
pcie->pdev = pdev;
|
2013-08-13 20:25:22 +08:00
|
|
|
platform_set_drvdata(pdev, pcie);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2013-07-26 21:17:48 +08:00
|
|
|
/* Get the PCIe memory and I/O aperture */
|
|
|
|
mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
|
|
|
|
if (resource_size(&pcie->mem) == 0) {
|
2016-10-07 02:38:58 +08:00
|
|
|
dev_err(dev, "invalid memory aperture size\n");
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
return -EINVAL;
|
2013-07-26 21:17:48 +08:00
|
|
|
}
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2013-07-26 21:17:48 +08:00
|
|
|
mvebu_mbus_get_pcie_io_aperture(&pcie->io);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2013-11-27 02:02:55 +08:00
|
|
|
if (resource_size(&pcie->io) != 0) {
|
|
|
|
pcie->realio.flags = pcie->io.flags;
|
|
|
|
pcie->realio.start = PCIBIOS_MIN_IO;
|
|
|
|
pcie->realio.end = min_t(resource_size_t,
|
|
|
|
IO_SPACE_LIMIT,
|
|
|
|
resource_size(&pcie->io));
|
|
|
|
} else
|
|
|
|
pcie->realio = pcie->io;
|
2013-07-26 21:17:48 +08:00
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
/* Get the bus range */
|
|
|
|
ret = of_pci_parse_bus_range(np, &pcie->busn);
|
|
|
|
if (ret) {
|
2016-10-07 02:38:58 +08:00
|
|
|
dev_err(dev, "failed to parse bus-range property: %d\n", ret);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-10-12 12:19:05 +08:00
|
|
|
num = of_get_available_child_count(np);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2016-10-07 02:38:58 +08:00
|
|
|
pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
if (!pcie->ports)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
i = 0;
|
2016-10-12 12:19:05 +08:00
|
|
|
for_each_available_child_of_node(np, child) {
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
|
|
|
|
2015-10-04 02:12:57 +08:00
|
|
|
ret = mvebu_pcie_parse_port(pcie, port, child);
|
2015-10-04 02:13:02 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
of_node_put(child);
|
2015-10-04 02:12:57 +08:00
|
|
|
return ret;
|
2015-10-04 02:13:02 +08:00
|
|
|
} else if (ret == 0) {
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
continue;
|
2015-10-04 02:13:02 +08:00
|
|
|
}
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2015-10-04 02:13:07 +08:00
|
|
|
port->dn = child;
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
pcie->nports = i;
|
|
|
|
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
|
|
|
|
|
|
|
child = port->dn;
|
|
|
|
if (!child)
|
|
|
|
continue;
|
|
|
|
|
2015-10-04 02:13:27 +08:00
|
|
|
ret = mvebu_pcie_powerup(port);
|
|
|
|
if (ret < 0)
|
2013-08-13 20:25:20 +08:00
|
|
|
continue;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
port->base = mvebu_pcie_map_registers(pdev, child, port);
|
2013-06-17 17:16:13 +08:00
|
|
|
if (IS_ERR(port->base)) {
|
2016-10-07 02:38:58 +08:00
|
|
|
dev_err(dev, "%s: cannot map registers\n", port->name);
|
2013-06-17 17:16:13 +08:00
|
|
|
port->base = NULL;
|
2015-10-04 02:13:27 +08:00
|
|
|
mvebu_pcie_powerdown(port);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 22:32:51 +08:00
|
|
|
mvebu_pcie_set_local_dev_nr(port, 1);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
mvebu_sw_pci_bridge_init(port);
|
|
|
|
}
|
|
|
|
|
2013-08-13 20:25:21 +08:00
|
|
|
pcie->nports = i;
|
2013-12-26 23:52:41 +08:00
|
|
|
|
|
|
|
for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
|
|
|
|
pci_ioremap_io(i, pcie->io.start + i);
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
mvebu_pcie_enable(pcie);
|
|
|
|
|
2015-03-17 22:55:45 +08:00
|
|
|
platform_set_drvdata(pdev, pcie);
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id mvebu_pcie_of_match_table[] = {
|
|
|
|
{ .compatible = "marvell,armada-xp-pcie", },
|
|
|
|
{ .compatible = "marvell,armada-370-pcie", },
|
2013-08-13 20:25:24 +08:00
|
|
|
{ .compatible = "marvell,dove-pcie", },
|
2013-05-15 21:36:54 +08:00
|
|
|
{ .compatible = "marvell,kirkwood-pcie", },
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
2016-03-16 17:59:40 +08:00
|
|
|
static const struct dev_pm_ops mvebu_pcie_pm_ops = {
|
2016-03-16 17:59:41 +08:00
|
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume)
|
2015-03-17 22:55:45 +08:00
|
|
|
};
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
static struct platform_driver mvebu_pcie_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "mvebu-pcie",
|
2013-12-19 17:04:59 +08:00
|
|
|
.of_match_table = mvebu_pcie_of_match_table,
|
2013-08-13 20:25:22 +08:00
|
|
|
/* driver unloading/unbinding currently not supported */
|
|
|
|
.suppress_bind_attrs = true,
|
2015-03-17 22:55:45 +08:00
|
|
|
.pm = &mvebu_pcie_pm_ops,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
},
|
2013-08-13 20:25:22 +08:00
|
|
|
.probe = mvebu_pcie_probe,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
};
|
2016-07-03 07:13:28 +08:00
|
|
|
builtin_platform_driver(mvebu_pcie_driver);
|