2020-03-06 12:28:19 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
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2022-10-01 06:45:49 +08:00
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* Copyright (C) 2018-2022 Linaro Ltd.
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2020-03-06 12:28:19 +08:00
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*/
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/* DOC: IPA Interrupts
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*
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* The IPA has an interrupt line distinct from the interrupt used by the GSI
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* code. Whereas GSI interrupts are generally related to channel events (like
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* transfer completions), IPA interrupts are related to other events related
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* to the IPA. Some of the IPA interrupts come from a microcontroller
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* embedded in the IPA. Each IPA interrupt type can be both masked and
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* acknowledged independent of the others.
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*
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* Two of the IPA interrupts are initiated by the microcontroller. A third
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* can be generated to signal the need for a wakeup/resume when an IPA
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* endpoint has been suspended. There are other IPA events, but at this
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* time only these three are supported.
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*/
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#include <linux/types.h>
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#include <linux/interrupt.h>
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2021-08-20 06:19:27 +08:00
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#include <linux/pm_runtime.h>
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2023-01-28 04:27:58 +08:00
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#include <linux/pm_wakeirq.h>
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2020-03-06 12:28:19 +08:00
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#include "ipa.h"
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#include "ipa_reg.h"
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#include "ipa_endpoint.h"
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2023-01-05 01:52:31 +08:00
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#include "ipa_power.h"
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#include "ipa_uc.h"
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2020-03-06 12:28:19 +08:00
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#include "ipa_interrupt.h"
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/**
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* struct ipa_interrupt - IPA interrupt information
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* @ipa: IPA pointer
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* @irq: Linux IRQ number used for IPA interrupts
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* @enabled: Mask indicating which interrupts are enabled
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*/
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struct ipa_interrupt {
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struct ipa *ipa;
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u32 irq;
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u32 enabled;
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};
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/* Process a particular interrupt type that has been received */
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static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id)
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{
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struct ipa *ipa = interrupt->ipa;
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net: ipa: start generalizing "ipa_reg"
IPA register definitions have evolved with each new version. The
changes required to support more than 32 endpoints in IPA v5.0 made
it best to define a unified mechanism for defining registers and
their fields.
GSI register definitions, meanwhile, have remained fairly stable.
And even as the total number of IPA endpoints goes beyond 32, the
number of GSI channels on a given EE that underly endpoints still
remains 32 or less.
Despite that, GSI v3.0 (which is used with IPA v5.0) extends the
number of channels (and events) it supports to be about 256, and as
a result, many GSI register definitions must change significantly.
To address this, we'll use the same "ipa_reg" mechanism to define
the GSI registers.
As a first step in generalizing the "ipa_reg" to also support GSI
registers, isolate the definitions of the "ipa_reg" and "ipa_regs"
structure types (and some supporting macros) into a new header file,
and remove the "ipa_" and "IPA_" from symbol names.
Separate the IPA register ID validity checking from the generic
check that a register ID is in range. Aside from that, this is
intended to have no functional effect on the code.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-02-09 04:56:51 +08:00
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const struct reg *reg;
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2020-03-06 12:28:19 +08:00
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u32 mask = BIT(irq_id);
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2021-03-25 22:44:34 +08:00
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u32 offset;
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2020-03-06 12:28:19 +08:00
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2022-09-27 06:09:21 +08:00
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reg = ipa_reg(ipa, IPA_IRQ_CLR);
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2023-02-09 04:56:52 +08:00
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offset = reg_offset(reg);
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2020-03-06 12:28:19 +08:00
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2023-01-05 01:52:33 +08:00
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switch (irq_id) {
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case IPA_IRQ_UC_0:
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case IPA_IRQ_UC_1:
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/* For microcontroller interrupts, clear the interrupt right
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* away, "to avoid clearing unhandled interrupts."
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*/
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iowrite32(mask, ipa->reg_virt + offset);
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ipa_uc_interrupt_handler(ipa, irq_id);
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break;
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case IPA_IRQ_TX_SUSPEND:
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/* Clearing the SUSPEND_TX interrupt also clears the
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* register that tells us which suspended endpoint(s)
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* caused the interrupt, so defer clearing until after
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* the handler has been called.
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*/
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ipa_power_suspend_handler(ipa, irq_id);
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fallthrough;
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default: /* Silently ignore (and clear) any other condition */
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2021-03-25 22:44:34 +08:00
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iowrite32(mask, ipa->reg_virt + offset);
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2023-01-05 01:52:33 +08:00
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break;
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}
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2020-03-06 12:28:19 +08:00
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}
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2021-07-28 03:46:29 +08:00
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/* IPA IRQ handler is threaded */
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static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
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2020-03-06 12:28:19 +08:00
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{
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2021-07-28 03:46:29 +08:00
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struct ipa_interrupt *interrupt = dev_id;
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2020-03-06 12:28:19 +08:00
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struct ipa *ipa = interrupt->ipa;
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u32 enabled = interrupt->enabled;
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net: ipa: start generalizing "ipa_reg"
IPA register definitions have evolved with each new version. The
changes required to support more than 32 endpoints in IPA v5.0 made
it best to define a unified mechanism for defining registers and
their fields.
GSI register definitions, meanwhile, have remained fairly stable.
And even as the total number of IPA endpoints goes beyond 32, the
number of GSI channels on a given EE that underly endpoints still
remains 32 or less.
Despite that, GSI v3.0 (which is used with IPA v5.0) extends the
number of channels (and events) it supports to be about 256, and as
a result, many GSI register definitions must change significantly.
To address this, we'll use the same "ipa_reg" mechanism to define
the GSI registers.
As a first step in generalizing the "ipa_reg" to also support GSI
registers, isolate the definitions of the "ipa_reg" and "ipa_regs"
structure types (and some supporting macros) into a new header file,
and remove the "ipa_" and "IPA_" from symbol names.
Separate the IPA register ID validity checking from the generic
check that a register ID is in range. Aside from that, this is
intended to have no functional effect on the code.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-02-09 04:56:51 +08:00
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const struct reg *reg;
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2021-08-20 06:19:27 +08:00
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struct device *dev;
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2021-07-28 03:46:27 +08:00
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u32 pending;
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2021-03-25 22:44:34 +08:00
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u32 offset;
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2020-03-06 12:28:19 +08:00
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u32 mask;
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net: ipa: have ipa_clock_get() return a value
We currently assume no errors occur when enabling or disabling the
IPA core clock and interconnects. And although this commit exposes
errors that could occur, we generally assume this won't happen in
practice.
This commit changes ipa_clock_get() and ipa_clock_put() so each
returns a value. The values returned are meant to mimic what the
runtime power management functions return, so we can set up error
handling here before we make the switch. Have ipa_clock_get()
increment the reference count even if it returns an error, to match
the behavior of pm_runtime_get().
More details follow.
When taking a reference in ipa_clock_get(), return 0 for the first
reference, 1 for subsequent references, or a negative error code if
an error occurs. Note that if ipa_clock_get() returns an error, we
must not touch hardware; in some cases such errors now cause entire
blocks of code to be skipped.
When dropping a reference in ipa_clock_put(), we return 0 or an
error code. The error would come from ipa_clock_disable(), which
now returns what ipa_interconnect_disable() returns (either 0 or a
negative error code). For now, callers ignore the return value;
if an error occurs, a message will have already been logged, and
little more can actually be done to improve the situation.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-11 03:26:58 +08:00
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int ret;
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2020-03-06 12:28:19 +08:00
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2021-08-20 06:19:27 +08:00
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dev = &ipa->pdev->dev;
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ret = pm_runtime_get_sync(dev);
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net: ipa: have ipa_clock_get() return a value
We currently assume no errors occur when enabling or disabling the
IPA core clock and interconnects. And although this commit exposes
errors that could occur, we generally assume this won't happen in
practice.
This commit changes ipa_clock_get() and ipa_clock_put() so each
returns a value. The values returned are meant to mimic what the
runtime power management functions return, so we can set up error
handling here before we make the switch. Have ipa_clock_get()
increment the reference count even if it returns an error, to match
the behavior of pm_runtime_get().
More details follow.
When taking a reference in ipa_clock_get(), return 0 for the first
reference, 1 for subsequent references, or a negative error code if
an error occurs. Note that if ipa_clock_get() returns an error, we
must not touch hardware; in some cases such errors now cause entire
blocks of code to be skipped.
When dropping a reference in ipa_clock_put(), we return 0 or an
error code. The error would come from ipa_clock_disable(), which
now returns what ipa_interconnect_disable() returns (either 0 or a
negative error code). For now, callers ignore the return value;
if an error occurs, a message will have already been logged, and
little more can actually be done to improve the situation.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-11 03:26:58 +08:00
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if (WARN_ON(ret < 0))
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2021-08-20 06:19:27 +08:00
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goto out_power_put;
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2021-07-28 03:46:29 +08:00
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2020-03-06 12:28:19 +08:00
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/* The status register indicates which conditions are present,
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* including conditions whose interrupt is not enabled. Handle
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* only the enabled ones.
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*/
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2022-09-27 06:09:21 +08:00
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reg = ipa_reg(ipa, IPA_IRQ_STTS);
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2023-02-09 04:56:52 +08:00
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offset = reg_offset(reg);
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2021-07-28 03:46:27 +08:00
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pending = ioread32(ipa->reg_virt + offset);
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while ((mask = pending & enabled)) {
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2020-03-06 12:28:19 +08:00
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do {
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u32 irq_id = __ffs(mask);
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mask ^= BIT(irq_id);
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ipa_interrupt_process(interrupt, irq_id);
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} while (mask);
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2021-07-28 03:46:27 +08:00
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pending = ioread32(ipa->reg_virt + offset);
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}
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/* If any disabled interrupts are pending, clear them */
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if (pending) {
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dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n",
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pending);
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2022-09-27 06:09:21 +08:00
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reg = ipa_reg(ipa, IPA_IRQ_CLR);
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2023-02-09 04:56:52 +08:00
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iowrite32(pending, ipa->reg_virt + reg_offset(reg));
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2020-03-06 12:28:19 +08:00
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}
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2021-08-20 06:19:27 +08:00
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out_power_put:
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2021-08-21 00:01:27 +08:00
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pm_runtime_mark_last_busy(dev);
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(void)pm_runtime_put_autosuspend(dev);
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2021-07-28 03:46:26 +08:00
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2020-03-06 12:28:19 +08:00
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return IRQ_HANDLED;
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}
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2023-01-05 01:52:29 +08:00
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static void ipa_interrupt_enabled_update(struct ipa *ipa)
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{
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net: ipa: start generalizing "ipa_reg"
IPA register definitions have evolved with each new version. The
changes required to support more than 32 endpoints in IPA v5.0 made
it best to define a unified mechanism for defining registers and
their fields.
GSI register definitions, meanwhile, have remained fairly stable.
And even as the total number of IPA endpoints goes beyond 32, the
number of GSI channels on a given EE that underly endpoints still
remains 32 or less.
Despite that, GSI v3.0 (which is used with IPA v5.0) extends the
number of channels (and events) it supports to be about 256, and as
a result, many GSI register definitions must change significantly.
To address this, we'll use the same "ipa_reg" mechanism to define
the GSI registers.
As a first step in generalizing the "ipa_reg" to also support GSI
registers, isolate the definitions of the "ipa_reg" and "ipa_regs"
structure types (and some supporting macros) into a new header file,
and remove the "ipa_" and "IPA_" from symbol names.
Separate the IPA register ID validity checking from the generic
check that a register ID is in range. Aside from that, this is
intended to have no functional effect on the code.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-02-09 04:56:51 +08:00
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const struct reg *reg = ipa_reg(ipa, IPA_IRQ_EN);
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2023-01-05 01:52:29 +08:00
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2023-02-09 04:56:52 +08:00
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iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg));
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2023-01-05 01:52:29 +08:00
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}
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/* Enable an IPA interrupt type */
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2023-01-05 01:52:30 +08:00
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void ipa_interrupt_enable(struct ipa *ipa, enum ipa_irq_id ipa_irq)
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2023-01-05 01:52:29 +08:00
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{
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/* Update the IPA interrupt mask to enable it */
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ipa->interrupt->enabled |= BIT(ipa_irq);
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ipa_interrupt_enabled_update(ipa);
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}
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/* Disable an IPA interrupt type */
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2023-01-05 01:52:30 +08:00
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void ipa_interrupt_disable(struct ipa *ipa, enum ipa_irq_id ipa_irq)
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2023-01-05 01:52:29 +08:00
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{
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/* Update the IPA interrupt mask to disable it */
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ipa->interrupt->enabled &= ~BIT(ipa_irq);
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ipa_interrupt_enabled_update(ipa);
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}
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2023-01-16 01:59:24 +08:00
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void ipa_interrupt_irq_disable(struct ipa *ipa)
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{
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disable_irq(ipa->interrupt->irq);
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}
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void ipa_interrupt_irq_enable(struct ipa *ipa)
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{
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enable_irq(ipa->interrupt->irq);
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}
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2020-03-06 12:28:19 +08:00
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/* Common function used to enable/disable TX_SUSPEND for an endpoint */
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static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
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u32 endpoint_id, bool enable)
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{
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struct ipa *ipa = interrupt->ipa;
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2022-12-31 06:33:04 +08:00
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u32 mask = BIT(endpoint_id % 32);
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2022-11-03 06:11:34 +08:00
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u32 unit = endpoint_id / 32;
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net: ipa: start generalizing "ipa_reg"
IPA register definitions have evolved with each new version. The
changes required to support more than 32 endpoints in IPA v5.0 made
it best to define a unified mechanism for defining registers and
their fields.
GSI register definitions, meanwhile, have remained fairly stable.
And even as the total number of IPA endpoints goes beyond 32, the
number of GSI channels on a given EE that underly endpoints still
remains 32 or less.
Despite that, GSI v3.0 (which is used with IPA v5.0) extends the
number of channels (and events) it supports to be about 256, and as
a result, many GSI register definitions must change significantly.
To address this, we'll use the same "ipa_reg" mechanism to define
the GSI registers.
As a first step in generalizing the "ipa_reg" to also support GSI
registers, isolate the definitions of the "ipa_reg" and "ipa_regs"
structure types (and some supporting macros) into a new header file,
and remove the "ipa_" and "IPA_" from symbol names.
Separate the IPA register ID validity checking from the generic
check that a register ID is in range. Aside from that, this is
intended to have no functional effect on the code.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-02-09 04:56:51 +08:00
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const struct reg *reg;
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2021-03-25 22:44:34 +08:00
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u32 offset;
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2020-03-06 12:28:19 +08:00
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u32 val;
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2022-11-03 06:11:36 +08:00
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WARN_ON(!test_bit(endpoint_id, ipa->available));
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2021-03-25 22:44:34 +08:00
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/* IPA version 3.0 does not support TX_SUSPEND interrupt control */
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if (ipa->version == IPA_VERSION_3_0)
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return;
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2022-09-27 06:09:21 +08:00
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reg = ipa_reg(ipa, IRQ_SUSPEND_EN);
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2023-02-09 04:56:52 +08:00
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offset = reg_n_offset(reg, unit);
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2021-03-25 22:44:34 +08:00
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val = ioread32(ipa->reg_virt + offset);
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2022-11-03 06:11:36 +08:00
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2020-03-06 12:28:19 +08:00
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if (enable)
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val |= mask;
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else
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val &= ~mask;
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2022-11-03 06:11:36 +08:00
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2021-03-25 22:44:34 +08:00
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iowrite32(val, ipa->reg_virt + offset);
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2020-03-06 12:28:19 +08:00
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}
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/* Enable TX_SUSPEND for an endpoint */
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void
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ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id)
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{
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ipa_interrupt_suspend_control(interrupt, endpoint_id, true);
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}
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/* Disable TX_SUSPEND for an endpoint */
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void
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ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id)
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{
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ipa_interrupt_suspend_control(interrupt, endpoint_id, false);
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}
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/* Clear the suspend interrupt for all endpoints that signaled it */
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void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt)
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{
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struct ipa *ipa = interrupt->ipa;
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2022-11-03 06:11:34 +08:00
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u32 unit_count;
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u32 unit;
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2020-03-06 12:28:19 +08:00
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2022-11-03 06:11:34 +08:00
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unit_count = roundup(ipa->endpoint_count, 32);
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|
|
|
for (unit = 0; unit < unit_count; unit++) {
|
net: ipa: start generalizing "ipa_reg"
IPA register definitions have evolved with each new version. The
changes required to support more than 32 endpoints in IPA v5.0 made
it best to define a unified mechanism for defining registers and
their fields.
GSI register definitions, meanwhile, have remained fairly stable.
And even as the total number of IPA endpoints goes beyond 32, the
number of GSI channels on a given EE that underly endpoints still
remains 32 or less.
Despite that, GSI v3.0 (which is used with IPA v5.0) extends the
number of channels (and events) it supports to be about 256, and as
a result, many GSI register definitions must change significantly.
To address this, we'll use the same "ipa_reg" mechanism to define
the GSI registers.
As a first step in generalizing the "ipa_reg" to also support GSI
registers, isolate the definitions of the "ipa_reg" and "ipa_regs"
structure types (and some supporting macros) into a new header file,
and remove the "ipa_" and "IPA_" from symbol names.
Separate the IPA register ID validity checking from the generic
check that a register ID is in range. Aside from that, this is
intended to have no functional effect on the code.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-02-09 04:56:51 +08:00
|
|
|
const struct reg *reg;
|
2022-11-03 06:11:34 +08:00
|
|
|
u32 val;
|
2021-03-25 22:44:34 +08:00
|
|
|
|
2022-11-03 06:11:34 +08:00
|
|
|
reg = ipa_reg(ipa, IRQ_SUSPEND_INFO);
|
2023-02-09 04:56:52 +08:00
|
|
|
val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit));
|
2022-11-03 06:11:34 +08:00
|
|
|
|
|
|
|
/* SUSPEND interrupt status isn't cleared on IPA version 3.0 */
|
|
|
|
if (ipa->version == IPA_VERSION_3_0)
|
|
|
|
continue;
|
2021-03-25 22:44:34 +08:00
|
|
|
|
2022-11-03 06:11:34 +08:00
|
|
|
reg = ipa_reg(ipa, IRQ_SUSPEND_CLR);
|
2023-02-09 04:56:52 +08:00
|
|
|
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, unit));
|
2022-11-03 06:11:34 +08:00
|
|
|
}
|
2020-03-06 12:28:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Simulate arrival of an IPA TX_SUSPEND interrupt */
|
|
|
|
void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt)
|
|
|
|
{
|
|
|
|
ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND);
|
|
|
|
}
|
|
|
|
|
2021-07-27 04:11:34 +08:00
|
|
|
/* Configure the IPA interrupt framework */
|
|
|
|
struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa)
|
2020-03-06 12:28:19 +08:00
|
|
|
{
|
|
|
|
struct device *dev = &ipa->pdev->dev;
|
|
|
|
struct ipa_interrupt *interrupt;
|
net: ipa: start generalizing "ipa_reg"
IPA register definitions have evolved with each new version. The
changes required to support more than 32 endpoints in IPA v5.0 made
it best to define a unified mechanism for defining registers and
their fields.
GSI register definitions, meanwhile, have remained fairly stable.
And even as the total number of IPA endpoints goes beyond 32, the
number of GSI channels on a given EE that underly endpoints still
remains 32 or less.
Despite that, GSI v3.0 (which is used with IPA v5.0) extends the
number of channels (and events) it supports to be about 256, and as
a result, many GSI register definitions must change significantly.
To address this, we'll use the same "ipa_reg" mechanism to define
the GSI registers.
As a first step in generalizing the "ipa_reg" to also support GSI
registers, isolate the definitions of the "ipa_reg" and "ipa_regs"
structure types (and some supporting macros) into a new header file,
and remove the "ipa_" and "IPA_" from symbol names.
Separate the IPA register ID validity checking from the generic
check that a register ID is in range. Aside from that, this is
intended to have no functional effect on the code.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-02-09 04:56:51 +08:00
|
|
|
const struct reg *reg;
|
2020-03-06 12:28:19 +08:00
|
|
|
unsigned int irq;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = platform_get_irq_byname(ipa->pdev, "ipa");
|
|
|
|
if (ret <= 0) {
|
|
|
|
dev_err(dev, "DT error %d getting \"ipa\" IRQ property\n",
|
|
|
|
ret);
|
|
|
|
return ERR_PTR(ret ? : -EINVAL);
|
|
|
|
}
|
|
|
|
irq = ret;
|
|
|
|
|
|
|
|
interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL);
|
|
|
|
if (!interrupt)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
interrupt->ipa = ipa;
|
|
|
|
interrupt->irq = irq;
|
|
|
|
|
|
|
|
/* Start with all IPA interrupts disabled */
|
2022-09-27 06:09:21 +08:00
|
|
|
reg = ipa_reg(ipa, IPA_IRQ_EN);
|
2023-02-09 04:56:52 +08:00
|
|
|
iowrite32(0, ipa->reg_virt + reg_offset(reg));
|
2020-03-06 12:28:19 +08:00
|
|
|
|
2021-07-28 03:46:26 +08:00
|
|
|
ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT,
|
2020-03-06 12:28:19 +08:00
|
|
|
"ipa", interrupt);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "error %d requesting \"ipa\" IRQ\n", ret);
|
|
|
|
goto err_kfree;
|
|
|
|
}
|
|
|
|
|
2023-01-28 04:27:58 +08:00
|
|
|
ret = dev_pm_set_wake_irq(dev, irq);
|
2020-09-18 01:39:25 +08:00
|
|
|
if (ret) {
|
2023-01-28 04:27:58 +08:00
|
|
|
dev_err(dev, "error %d registering \"ipa\" IRQ as wakeirq\n", ret);
|
2020-09-18 01:39:25 +08:00
|
|
|
goto err_free_irq;
|
|
|
|
}
|
|
|
|
|
2020-03-06 12:28:19 +08:00
|
|
|
return interrupt;
|
|
|
|
|
2020-09-18 01:39:25 +08:00
|
|
|
err_free_irq:
|
|
|
|
free_irq(interrupt->irq, interrupt);
|
2020-03-06 12:28:19 +08:00
|
|
|
err_kfree:
|
|
|
|
kfree(interrupt);
|
|
|
|
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
2021-07-27 04:11:34 +08:00
|
|
|
/* Inverse of ipa_interrupt_config() */
|
|
|
|
void ipa_interrupt_deconfig(struct ipa_interrupt *interrupt)
|
2020-03-06 12:28:19 +08:00
|
|
|
{
|
2020-09-18 01:39:25 +08:00
|
|
|
struct device *dev = &interrupt->ipa->pdev->dev;
|
|
|
|
|
2023-01-28 04:27:58 +08:00
|
|
|
dev_pm_clear_wake_irq(dev);
|
2020-03-06 12:28:19 +08:00
|
|
|
free_irq(interrupt->irq, interrupt);
|
|
|
|
kfree(interrupt);
|
|
|
|
}
|