2019-06-04 16:11:33 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-10-03 05:19:52 +08:00
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/*
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* Interface for functions that need to be run in internal SRAM
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*/
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2010-10-09 01:00:19 +08:00
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2012-10-03 05:19:52 +08:00
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#ifndef __ASSEMBLY__
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2012-10-30 04:54:06 +08:00
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#include <plat/sram.h>
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2012-10-03 05:19:52 +08:00
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extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock);
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extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern void omap3_sram_restore_context(void);
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/* Do not use these */
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extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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extern unsigned long omap24xx_sram_reprogram_clock_sz;
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extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock);
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extern unsigned long omap242x_sram_ddr_init_sz;
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extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
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int bypass);
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extern unsigned long omap242x_sram_set_prcm_sz;
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extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern unsigned long omap242x_sram_reprogram_sdrc_sz;
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extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock);
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extern unsigned long omap243x_sram_ddr_init_sz;
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extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
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int bypass);
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extern unsigned long omap243x_sram_set_prcm_sz;
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extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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#ifdef CONFIG_PM
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extern void omap_push_sram_idle(void);
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#else
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static inline void omap_push_sram_idle(void) {}
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#endif /* CONFIG_PM */
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#endif /* __ASSEMBLY__ */
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/*
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* OMAP2+: define the SRAM PA addresses.
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* Used by the SRAM management code and the idle sleep code.
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*/
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#define OMAP2_SRAM_PA 0x40200000
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#define OMAP3_SRAM_PA 0x40200000
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