2018-01-22 00:50:33 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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2017-02-26 11:09:57 +08:00
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/*
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* Actions Semi Owl Smart Power System (SPS)
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*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2017 Andreas Färber
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*/
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_domain.h>
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2017-06-06 03:04:21 +08:00
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#include <linux/soc/actions/owl-sps.h>
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2017-02-26 11:09:57 +08:00
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#include <dt-bindings/power/owl-s500-powergate.h>
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2017-09-10 09:39:27 +08:00
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#include <dt-bindings/power/owl-s700-powergate.h>
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2018-04-12 00:40:35 +08:00
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#include <dt-bindings/power/owl-s900-powergate.h>
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2017-02-26 11:09:57 +08:00
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struct owl_sps_domain_info {
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const char *name;
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int pwr_bit;
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int ack_bit;
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unsigned int genpd_flags;
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};
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struct owl_sps_info {
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unsigned num_domains;
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const struct owl_sps_domain_info *domains;
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};
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struct owl_sps {
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struct device *dev;
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const struct owl_sps_info *info;
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void __iomem *base;
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struct genpd_onecell_data genpd_data;
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struct generic_pm_domain *domains[];
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};
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#define to_owl_pd(gpd) container_of(gpd, struct owl_sps_domain, genpd)
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struct owl_sps_domain {
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struct generic_pm_domain genpd;
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const struct owl_sps_domain_info *info;
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struct owl_sps *sps;
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};
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static int owl_sps_set_power(struct owl_sps_domain *pd, bool enable)
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{
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2017-06-06 03:04:21 +08:00
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u32 pwr_mask, ack_mask;
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2017-02-26 11:09:57 +08:00
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ack_mask = BIT(pd->info->ack_bit);
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pwr_mask = BIT(pd->info->pwr_bit);
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2017-06-06 03:04:21 +08:00
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return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable);
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2017-02-26 11:09:57 +08:00
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}
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static int owl_sps_power_on(struct generic_pm_domain *domain)
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{
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struct owl_sps_domain *pd = to_owl_pd(domain);
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dev_dbg(pd->sps->dev, "%s power on", pd->info->name);
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return owl_sps_set_power(pd, true);
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}
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static int owl_sps_power_off(struct generic_pm_domain *domain)
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{
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struct owl_sps_domain *pd = to_owl_pd(domain);
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dev_dbg(pd->sps->dev, "%s power off", pd->info->name);
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return owl_sps_set_power(pd, false);
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}
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static int owl_sps_init_domain(struct owl_sps *sps, int index)
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{
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struct owl_sps_domain *pd;
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pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->info = &sps->info->domains[index];
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pd->sps = sps;
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pd->genpd.name = pd->info->name;
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pd->genpd.power_on = owl_sps_power_on;
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pd->genpd.power_off = owl_sps_power_off;
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pd->genpd.flags = pd->info->genpd_flags;
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pm_genpd_init(&pd->genpd, NULL, false);
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sps->genpd_data.domains[index] = &pd->genpd;
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return 0;
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}
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static int owl_sps_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct owl_sps_info *sps_info;
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struct owl_sps *sps;
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int i, ret;
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "no device node\n");
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return -ENODEV;
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}
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match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev);
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if (!match || !match->data) {
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dev_err(&pdev->dev, "unknown compatible or missing data\n");
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return -EINVAL;
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}
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sps_info = match->data;
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treewide: Use struct_size() for devm_kmalloc() and friends
Replaces open-coded struct size calculations with struct_size() for
devm_*, f2fs_*, and sock_* allocations. Automatically generated (and
manually adjusted) from the following Coccinelle script:
// Direct reference to struct field.
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identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@
- alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP)
+ alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)
// mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
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identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@
- alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP)
+ alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)
// Same pattern, but can't trivially locate the trailing element name,
// or variable name.
@@
identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
expression SOMETHING, COUNT, ELEMENT;
@@
- alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP)
+ alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-05-09 07:08:53 +08:00
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sps = devm_kzalloc(&pdev->dev,
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struct_size(sps, domains, sps_info->num_domains),
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2017-02-26 11:09:57 +08:00
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GFP_KERNEL);
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if (!sps)
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return -ENOMEM;
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sps->base = of_io_request_and_map(pdev->dev.of_node, 0, "owl-sps");
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if (IS_ERR(sps->base)) {
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dev_err(&pdev->dev, "failed to map sps registers\n");
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return PTR_ERR(sps->base);
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}
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sps->dev = &pdev->dev;
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sps->info = sps_info;
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sps->genpd_data.domains = sps->domains;
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sps->genpd_data.num_domains = sps_info->num_domains;
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for (i = 0; i < sps_info->num_domains; i++) {
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ret = owl_sps_init_domain(sps, i);
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if (ret)
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return ret;
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}
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ret = of_genpd_add_provider_onecell(pdev->dev.of_node, &sps->genpd_data);
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if (ret) {
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dev_err(&pdev->dev, "failed to add provider (%d)", ret);
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return ret;
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}
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return 0;
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}
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static const struct owl_sps_domain_info s500_sps_domains[] = {
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[S500_PD_VDE] = {
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.name = "VDE",
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.pwr_bit = 0,
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.ack_bit = 16,
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},
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[S500_PD_VCE_SI] = {
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.name = "VCE_SI",
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.pwr_bit = 1,
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.ack_bit = 17,
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},
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[S500_PD_USB2_1] = {
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.name = "USB2_1",
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.pwr_bit = 2,
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.ack_bit = 18,
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},
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[S500_PD_CPU2] = {
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.name = "CPU2",
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.pwr_bit = 5,
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.ack_bit = 21,
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.genpd_flags = GENPD_FLAG_ALWAYS_ON,
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},
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[S500_PD_CPU3] = {
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.name = "CPU3",
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.pwr_bit = 6,
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.ack_bit = 22,
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.genpd_flags = GENPD_FLAG_ALWAYS_ON,
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},
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[S500_PD_DMA] = {
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.name = "DMA",
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.pwr_bit = 8,
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.ack_bit = 12,
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},
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[S500_PD_DS] = {
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.name = "DS",
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.pwr_bit = 9,
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.ack_bit = 13,
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},
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[S500_PD_USB3] = {
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.name = "USB3",
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.pwr_bit = 10,
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.ack_bit = 14,
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},
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[S500_PD_USB2_0] = {
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.name = "USB2_0",
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.pwr_bit = 11,
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.ack_bit = 15,
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},
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};
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static const struct owl_sps_info s500_sps_info = {
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.num_domains = ARRAY_SIZE(s500_sps_domains),
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.domains = s500_sps_domains,
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};
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2017-09-10 09:39:27 +08:00
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static const struct owl_sps_domain_info s700_sps_domains[] = {
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[S700_PD_VDE] = {
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.name = "VDE",
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.pwr_bit = 0,
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},
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[S700_PD_VCE_SI] = {
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.name = "VCE_SI",
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.pwr_bit = 1,
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},
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[S700_PD_USB2_1] = {
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.name = "USB2_1",
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.pwr_bit = 2,
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},
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[S700_PD_HDE] = {
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.name = "HDE",
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.pwr_bit = 7,
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},
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[S700_PD_DMA] = {
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.name = "DMA",
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.pwr_bit = 8,
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},
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[S700_PD_DS] = {
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.name = "DS",
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.pwr_bit = 9,
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},
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[S700_PD_USB3] = {
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.name = "USB3",
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.pwr_bit = 10,
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},
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[S700_PD_USB2_0] = {
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.name = "USB2_0",
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.pwr_bit = 11,
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},
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};
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static const struct owl_sps_info s700_sps_info = {
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.num_domains = ARRAY_SIZE(s700_sps_domains),
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.domains = s700_sps_domains,
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};
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2018-04-12 00:40:35 +08:00
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static const struct owl_sps_domain_info s900_sps_domains[] = {
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[S900_PD_GPU_B] = {
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.name = "GPU_B",
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.pwr_bit = 3,
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},
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[S900_PD_VCE] = {
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.name = "VCE",
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.pwr_bit = 4,
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},
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[S900_PD_SENSOR] = {
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.name = "SENSOR",
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.pwr_bit = 5,
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},
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[S900_PD_VDE] = {
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.name = "VDE",
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.pwr_bit = 6,
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},
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[S900_PD_HDE] = {
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.name = "HDE",
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.pwr_bit = 7,
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},
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[S900_PD_USB3] = {
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.name = "USB3",
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.pwr_bit = 8,
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},
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[S900_PD_DDR0] = {
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.name = "DDR0",
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.pwr_bit = 9,
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},
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[S900_PD_DDR1] = {
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.name = "DDR1",
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.pwr_bit = 10,
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},
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[S900_PD_DE] = {
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.name = "DE",
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.pwr_bit = 13,
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},
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[S900_PD_NAND] = {
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.name = "NAND",
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.pwr_bit = 14,
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},
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[S900_PD_USB2_H0] = {
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.name = "USB2_H0",
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.pwr_bit = 15,
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},
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[S900_PD_USB2_H1] = {
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.name = "USB2_H1",
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.pwr_bit = 16,
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},
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};
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static const struct owl_sps_info s900_sps_info = {
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.num_domains = ARRAY_SIZE(s900_sps_domains),
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.domains = s900_sps_domains,
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};
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2017-02-26 11:09:57 +08:00
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static const struct of_device_id owl_sps_of_matches[] = {
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{ .compatible = "actions,s500-sps", .data = &s500_sps_info },
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2017-09-10 09:39:27 +08:00
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{ .compatible = "actions,s700-sps", .data = &s700_sps_info },
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2018-04-12 00:40:35 +08:00
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{ .compatible = "actions,s900-sps", .data = &s900_sps_info },
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2017-02-26 11:09:57 +08:00
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{ }
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};
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static struct platform_driver owl_sps_platform_driver = {
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.probe = owl_sps_probe,
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.driver = {
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.name = "owl-sps",
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.of_match_table = owl_sps_of_matches,
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.suppress_bind_attrs = true,
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},
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};
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static int __init owl_sps_init(void)
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{
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return platform_driver_register(&owl_sps_platform_driver);
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}
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postcore_initcall(owl_sps_init);
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