104 lines
2.7 KiB
ReStructuredText
104 lines
2.7 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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=================
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PCI Test Function
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=================
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:Author: Kishon Vijay Abraham I <kishon@ti.com>
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Traditionally PCI RC has always been validated by using standard
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PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
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However with the addition of EP-core in linux kernel, it is possible
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to configure a PCI controller that can operate in EP mode to work as
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a test device.
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The PCI endpoint test device is a virtual device (defined in software)
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used to test the endpoint functionality and serve as a sample driver
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for other PCI endpoint devices (to use the EP framework).
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The PCI endpoint test device has the following registers:
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1) PCI_ENDPOINT_TEST_MAGIC
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2) PCI_ENDPOINT_TEST_COMMAND
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3) PCI_ENDPOINT_TEST_STATUS
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4) PCI_ENDPOINT_TEST_SRC_ADDR
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5) PCI_ENDPOINT_TEST_DST_ADDR
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6) PCI_ENDPOINT_TEST_SIZE
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7) PCI_ENDPOINT_TEST_CHECKSUM
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8) PCI_ENDPOINT_TEST_IRQ_TYPE
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9) PCI_ENDPOINT_TEST_IRQ_NUMBER
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* PCI_ENDPOINT_TEST_MAGIC
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This register will be used to test BAR0. A known pattern will be written
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and read back from MAGIC register to verify BAR0.
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* PCI_ENDPOINT_TEST_COMMAND
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This register will be used by the host driver to indicate the function
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that the endpoint device must perform.
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======== ================================================================
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Bitfield Description
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======== ================================================================
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Bit 0 raise legacy IRQ
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Bit 1 raise MSI IRQ
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Bit 2 raise MSI-X IRQ
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Bit 3 read command (read data from RC buffer)
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Bit 4 write command (write data to RC buffer)
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Bit 5 copy command (copy data from one RC buffer to another RC buffer)
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======== ================================================================
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* PCI_ENDPOINT_TEST_STATUS
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This register reflects the status of the PCI endpoint device.
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======== ==============================
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Bitfield Description
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======== ==============================
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Bit 0 read success
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Bit 1 read fail
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Bit 2 write success
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Bit 3 write fail
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Bit 4 copy success
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Bit 5 copy fail
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Bit 6 IRQ raised
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Bit 7 source address is invalid
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Bit 8 destination address is invalid
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======== ==============================
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* PCI_ENDPOINT_TEST_SRC_ADDR
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This register contains the source address (RC buffer address) for the
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COPY/READ command.
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* PCI_ENDPOINT_TEST_DST_ADDR
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This register contains the destination address (RC buffer address) for
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the COPY/WRITE command.
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* PCI_ENDPOINT_TEST_IRQ_TYPE
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This register contains the interrupt type (Legacy/MSI) triggered
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for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
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Possible types:
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====== ==
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Legacy 0
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MSI 1
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MSI-X 2
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====== ==
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* PCI_ENDPOINT_TEST_IRQ_NUMBER
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This register contains the triggered ID interrupt.
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Admissible values:
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====== ===========
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Legacy 0
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MSI [1 .. 32]
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MSI-X [1 .. 2048]
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====== ===========
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