206 lines
7.7 KiB
C
206 lines
7.7 KiB
C
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/*
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*
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Copyright (c) Eicon Networks, 2002.
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*
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This source file is supplied for the use with
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Eicon Networks range of DIVA Server Adapters.
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*
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Eicon File Revision : 2.1
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*
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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*
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY OF ANY KIND WHATSOEVER INCLUDING ANY
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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*
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include "platform.h"
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#include "di_defs.h"
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#include "pc.h"
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#include "pr_pc.h"
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#include "di.h"
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#include "mi_pc.h"
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#include "pc_maint.h"
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#include "divasync.h"
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#include "io.h"
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#include "helpers.h"
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#include "dsrv_pri.h"
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#include "dsp_defs.h"
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/*****************************************************************************/
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#define MAX_XLOG_SIZE (64 * 1024)
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/* -------------------------------------------------------------------------
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Does return offset between ADAPTER->ram and real begin of memory
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------------------------------------------------------------------------- */
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static dword pri_ram_offset (ADAPTER* a) {
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return ((dword)MP_SHARED_RAM_OFFSET);
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}
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/* -------------------------------------------------------------------------
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Recovery XLOG buffer from the card
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------------------------------------------------------------------------- */
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static void pri_cpu_trapped (PISDN_ADAPTER IoAdapter) {
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byte __iomem *base ;
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word *Xlog ;
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dword regs[4], TrapID, size ;
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Xdesc xlogDesc ;
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/*
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* check for trapped MIPS 46xx CPU, dump exception frame
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*/
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base = DIVA_OS_MEM_ATTACH_ADDRESS(IoAdapter);
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TrapID = READ_DWORD(&base[0x80]) ;
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if ( (TrapID == 0x99999999) || (TrapID == 0x99999901) )
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{
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dump_trap_frame (IoAdapter, &base[0x90]) ;
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IoAdapter->trapped = 1 ;
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}
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regs[0] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x70]);
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regs[1] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x74]);
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regs[2] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x78]);
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regs[3] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x7c]);
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regs[0] &= IoAdapter->MemorySize - 1 ;
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if ( (regs[0] < IoAdapter->MemorySize - 1) )
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{
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if ( !(Xlog = (word *)diva_os_malloc (0, MAX_XLOG_SIZE)) ) {
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DIVA_OS_MEM_DETACH_ADDRESS(IoAdapter, base);
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return ;
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}
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size = IoAdapter->MemorySize - regs[0] ;
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if ( size > MAX_XLOG_SIZE )
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size = MAX_XLOG_SIZE ;
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memcpy_fromio(Xlog, &base[regs[0]], size) ;
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xlogDesc.buf = Xlog ;
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xlogDesc.cnt = READ_WORD(&base[regs[1] & (IoAdapter->MemorySize - 1)]) ;
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xlogDesc.out = READ_WORD(&base[regs[2] & (IoAdapter->MemorySize - 1)]) ;
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dump_xlog_buffer (IoAdapter, &xlogDesc) ;
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diva_os_free (0, Xlog) ;
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IoAdapter->trapped = 2 ;
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}
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DIVA_OS_MEM_DETACH_ADDRESS(IoAdapter, base);
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}
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/* -------------------------------------------------------------------------
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Hardware reset of PRI card
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------------------------------------------------------------------------- */
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static void reset_pri_hardware (PISDN_ADAPTER IoAdapter) {
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byte __iomem *p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
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WRITE_BYTE(p, _MP_RISC_RESET | _MP_LED1 | _MP_LED2);
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diva_os_wait (50) ;
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WRITE_BYTE(p, 0x00);
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diva_os_wait (50) ;
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DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
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}
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/* -------------------------------------------------------------------------
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Stop Card Hardware
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------------------------------------------------------------------------- */
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static void stop_pri_hardware (PISDN_ADAPTER IoAdapter) {
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dword i;
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byte __iomem *p;
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dword volatile __iomem *cfgReg = (void __iomem *)DIVA_OS_MEM_ATTACH_CFG(IoAdapter);
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WRITE_DWORD(&cfgReg[3], 0);
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WRITE_DWORD(&cfgReg[1], 0);
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DIVA_OS_MEM_DETACH_CFG(IoAdapter, cfgReg);
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IoAdapter->a.ram_out (&IoAdapter->a, &RAM->SWReg, SWREG_HALT_CPU) ;
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i = 0 ;
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while ( (i < 100) && (IoAdapter->a.ram_in (&IoAdapter->a, &RAM->SWReg) != 0) )
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{
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diva_os_wait (1) ;
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i++ ;
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}
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DBG_TRC(("%s: PRI stopped (%d)", IoAdapter->Name, i))
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cfgReg = (void __iomem *)DIVA_OS_MEM_ATTACH_CFG(IoAdapter);
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WRITE_DWORD(&cfgReg[0],((dword)(~0x03E00000)));
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DIVA_OS_MEM_DETACH_CFG(IoAdapter, cfgReg);
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diva_os_wait (1) ;
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p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
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WRITE_BYTE(p, _MP_RISC_RESET | _MP_LED1 | _MP_LED2);
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DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
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}
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static int load_pri_hardware (PISDN_ADAPTER IoAdapter) {
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return (0);
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}
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/* --------------------------------------------------------------------------
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PRI Adapter interrupt Service Routine
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-------------------------------------------------------------------------- */
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static int pri_ISR (struct _ISDN_ADAPTER* IoAdapter) {
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byte __iomem *cfg = DIVA_OS_MEM_ATTACH_CFG(IoAdapter);
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if ( !(READ_DWORD(cfg) & 0x80000000) ) {
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DIVA_OS_MEM_DETACH_CFG(IoAdapter, cfg);
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return (0) ;
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}
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/*
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clear interrupt line
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*/
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WRITE_DWORD(cfg, (dword)~0x03E00000) ;
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DIVA_OS_MEM_DETACH_CFG(IoAdapter, cfg);
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IoAdapter->IrqCount++ ;
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if ( IoAdapter->Initialized )
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{
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diva_os_schedule_soft_isr (&IoAdapter->isr_soft_isr);
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}
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return (1) ;
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}
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/* -------------------------------------------------------------------------
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Disable interrupt in the card hardware
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------------------------------------------------------------------------- */
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static void disable_pri_interrupt (PISDN_ADAPTER IoAdapter) {
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dword volatile __iomem *cfgReg = (dword volatile __iomem *)DIVA_OS_MEM_ATTACH_CFG(IoAdapter) ;
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WRITE_DWORD(&cfgReg[3], 0);
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WRITE_DWORD(&cfgReg[1], 0);
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WRITE_DWORD(&cfgReg[0], (dword)(~0x03E00000)) ;
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DIVA_OS_MEM_DETACH_CFG(IoAdapter, cfgReg);
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}
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/* -------------------------------------------------------------------------
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Install entry points for PRI Adapter
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------------------------------------------------------------------------- */
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static void prepare_common_pri_functions (PISDN_ADAPTER IoAdapter) {
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ADAPTER *a = &IoAdapter->a ;
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a->ram_in = mem_in ;
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a->ram_inw = mem_inw ;
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a->ram_in_buffer = mem_in_buffer ;
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a->ram_look_ahead = mem_look_ahead ;
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a->ram_out = mem_out ;
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a->ram_outw = mem_outw ;
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a->ram_out_buffer = mem_out_buffer ;
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a->ram_inc = mem_inc ;
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a->ram_offset = pri_ram_offset ;
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a->ram_out_dw = mem_out_dw;
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a->ram_in_dw = mem_in_dw;
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a->istream_wakeup = pr_stream;
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IoAdapter->out = pr_out ;
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IoAdapter->dpc = pr_dpc ;
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IoAdapter->tst_irq = scom_test_int ;
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IoAdapter->clr_irq = scom_clear_int ;
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IoAdapter->pcm = (struct pc_maint *)(MIPS_MAINT_OFFS
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- MP_SHARED_RAM_OFFSET) ;
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IoAdapter->load = load_pri_hardware ;
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IoAdapter->disIrq = disable_pri_interrupt ;
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IoAdapter->rstFnc = reset_pri_hardware ;
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IoAdapter->stop = stop_pri_hardware ;
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IoAdapter->trapFnc = pri_cpu_trapped ;
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IoAdapter->diva_isr_handler = pri_ISR;
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}
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/* -------------------------------------------------------------------------
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Install entry points for PRI Adapter
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------------------------------------------------------------------------- */
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void prepare_pri_functions (PISDN_ADAPTER IoAdapter) {
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IoAdapter->MemorySize = MP_MEMORY_SIZE ;
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prepare_common_pri_functions (IoAdapter) ;
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diva_os_prepare_pri_functions (IoAdapter);
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}
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/* -------------------------------------------------------------------------
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Install entry points for PRI Rev.2 Adapter
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------------------------------------------------------------------------- */
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void prepare_pri2_functions (PISDN_ADAPTER IoAdapter) {
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IoAdapter->MemorySize = MP2_MEMORY_SIZE ;
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prepare_common_pri_functions (IoAdapter) ;
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diva_os_prepare_pri2_functions (IoAdapter);
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}
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/* ------------------------------------------------------------------------- */
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