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OpenCloudOS-Kernel/arch/arm/boot/dts/sun4i-a10.dtsi

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ARM: sunxi: Add missing sun4i.dtsi file Patch f055f1f6 [ARM: sunxi: Add sun4i and cubieboard support] missed this sun4i.dtsi include file. This patch finally brings it upstream enabling support for sun4i boards. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-26 22:46:12 +08:00
/*
* Copyright 2012 Stefan Roese
* Stefan Roese <sr@denx.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
/include/ "skeleton.dtsi"
ARM: sunxi: Add missing sun4i.dtsi file Patch f055f1f6 [ARM: sunxi: Add sun4i and cubieboard support] missed this sun4i.dtsi include file. This patch finally brings it upstream enabling support for sun4i boards. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-26 22:46:12 +08:00
/ {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
interrupt-parent = <&intc>;
ARM: sunxi: dt: add EMAC aliases U-Boot uses the ethernet0 alias to locate the right node to fill in the MAC address of the first ethernet interface. This patch adds the alias on all the sunxi SoCs with EMAC. In this way, people using ethernet in U-Boot (eg, for tftp) can keep a consistent address on both U-Boot and Linux with no additional effort. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-11-17 02:17:29 +08:00
aliases {
ethernet0 = &emac;
ARM: sun4i: dt: Move the aliases to the DTSI The aliases are shared across boards are really belong to the DTSI. Move them there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-11-17 17:03:04 +08:00
serial0 = &uart0;
serial1 = &uart1;
ARM: sun4i: a10: Add missing serial aliases Some UART aliases have been defined, but not all of them. Add the remaining ones to be consistent and to ease the parsing of the DT by the bootloaders. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-01-03 05:05:04 +08:00
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
ARM: sunxi: dt: add EMAC aliases U-Boot uses the ethernet0 alias to locate the right node to fill in the MAC address of the first ethernet interface. This patch adds the alias on all the sunxi SoCs with EMAC. In this way, people using ethernet in U-Boot (eg, for tftp) can keep a consistent address on both U-Boot and Linux with no additional effort. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-11-17 02:17:29 +08:00
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
cpus {
ARM: dts: add missing cpu #address-cell values A recent series has added CPU numbers to a lot of dts files, but unfortunately in a few cases the #address-cells and #size-cells values are missing, which causes build warnings. This adds the missing ones for sunxi and sama5 that I found through build testing. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2013-06-10 22:48:36 +08:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
cpu@0 {
ARM: dts: sunxi: cpus/cpu nodes dts updates This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 01:41:57 +08:00
device_type = "cpu";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
compatible = "arm,cortex-a8";
ARM: dts: sunxi: cpus/cpu nodes dts updates This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 01:41:57 +08:00
reg = <0x0>;
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
};
ARM: sunxi: Add missing sun4i.dtsi file Patch f055f1f6 [ARM: sunxi: Add sun4i and cubieboard support] missed this sun4i.dtsi include file. This patch finally brings it upstream enabling support for sun4i boards. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-26 22:46:12 +08:00
memory {
reg = <0x40000000 0x80000000>;
};
ARM: sunxi: Add the sun4i pinctrl and gpio nodes Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-26 22:36:54 +08:00
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
dummy: dummy {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
osc24M: clk@01c20050 {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-osc-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20050 0x4>;
ARM: sunxi: unify osc24M_fixed and osc24M Now that the clock driver supports the gatable oscillator as one single clock, drop osc24M_fixed and move the relevant properties to osc24M Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-09 21:48:04 +08:00
clock-frequency = <24000000>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "osc24M";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
osc32k: clk@0 {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "osc32k";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
pll1: clk@01c20000 {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-pll1-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "pll1";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
pll4: clk@01c20018 {
ARM: sunxi: add PLL4 support This commit adds the PLL4 definition to the sun4i, sun5i and sun7i device trees. PLL4 is compatible with PLL1. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:35 +08:00
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-pll1-clk";
ARM: sunxi: add PLL4 support This commit adds the PLL4 definition to the sun4i, sun5i and sun7i device trees. PLL4 is compatible with PLL1. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:35 +08:00
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "pll4";
ARM: sunxi: add PLL4 support This commit adds the PLL4 definition to the sun4i, sun5i and sun7i device trees. PLL4 is compatible with PLL1. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:35 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
pll5: clk@01c20020 {
ARM: sunxi: add PLL5 and PLL6 support This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:38 +08:00
#clock-cells = <1>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-pll5-clk";
ARM: sunxi: add PLL5 and PLL6 support This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:38 +08:00
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
pll6: clk@01c20028 {
ARM: sunxi: add PLL5 and PLL6 support This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:38 +08:00
#clock-cells = <1>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-pll6-clk";
ARM: sunxi: add PLL5 and PLL6 support This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:38 +08:00
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-cpu-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "cpu";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
axi: axi@01c20054 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-axi-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "axi";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
axi_gates: clk@01c2005c {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
#clock-cells = <1>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-axi-gates-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-output-names = "axi_dram";
};
ahb: ahb@01c20054 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-ahb-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20054 0x4>;
clocks = <&axi>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "ahb";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
ahb_gates: clk@01c20060 {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
#clock-cells = <1>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
"ahb_de_fe1", "ahb_mp", "ahb_mali400";
};
apb0: apb0@01c20054 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-apb0-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "apb0";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
apb0_gates: clk@01c20068 {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
#clock-cells = <1>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
"apb0_ir1", "apb0_keypad";
};
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20058 0x4>;
ARM: sunxi: add PLL5 and PLL6 support This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:38 +08:00
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "apb1_mux";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-apb1-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
clock-output-names = "apb1";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: dts: sun4i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 09:51:41 +08:00
apb1_gates: clk@01c2006c {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
#clock-cells = <1>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-apb1-gates-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_can", "apb1_scr",
"apb1_ps20", "apb1_ps21", "apb1_uart0",
"apb1_uart1", "apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5", "apb1_uart6",
"apb1_uart7";
};
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
nand_clk: clk@01c20080 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
};
ms_clk: clk@01c20084 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c20084 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ms";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
};
mmc3_clk: clk@01c20094 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc3";
};
ts_clk: clk@01c20098 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c20098 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ts";
};
ss_clk: clk@01c2009c {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ss";
};
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi0";
};
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi1";
};
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi2";
};
pata_clk: clk@01c200ac {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c200ac 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "pata";
};
ir0_clk: clk@01c200b0 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c200b0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir0";
};
ir1_clk: clk@01c200b4 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c200b4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir1";
};
ARM: sun4i: dt: Add bindings for USB clocks Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-07 23:21:51 +08:00
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun4i-a10-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&pll6 1>;
clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
};
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
spi3_clk: clk@01c200d4 {
#clock-cells = <0>;
ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-06 16:55:58 +08:00
compatible = "allwinner,sun4i-a10-mod0-clk";
ARM: sun4i: dt: mod0 clocks This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 11:32:41 +08:00
reg = <0x01c200d4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi3";
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
};
ARM: sun4i: dt: Fix A10 SoC bus base address There was a typo in the base address used for the soc node in the A10 device tree. Fix it with the proper base address. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-03 22:07:36 +08:00
soc@01c00000 {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ARM: dt: sun4i: Add A10 SPI controller nodes The A10 has 4 SPI controllers that are now supported. Add them in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-23 05:35:55 +08:00
spi0: spi@01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
clocks = <&ahb_gates 20>, <&spi0_clk>;
clock-names = "ahb", "mod";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@01c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ARM: sunxi: Add EMAC controller node to sun4i DTSI Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-05-30 11:49:23 +08:00
emac: ethernet@01c0b000 {
ARM: sunxi: dt: Convert to the new net compatibles Switch the device tree to the new compatibles introduced in the ethernet and mdio drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-02-02 21:49:13 +08:00
compatible = "allwinner,sun4i-a10-emac";
ARM: sunxi: Add EMAC controller node to sun4i DTSI Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-05-30 11:49:23 +08:00
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
clocks = <&ahb_gates 17>;
status = "disabled";
};
mdio@01c0b080 {
ARM: sunxi: dt: Convert to the new net compatibles Switch the device tree to the new compatibles introduced in the ethernet and mdio drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-02-02 21:49:13 +08:00
compatible = "allwinner,sun4i-a10-mdio";
ARM: sunxi: Add EMAC controller node to sun4i DTSI Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-05-30 11:49:23 +08:00
reg = <0x01c0b080 0x14>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ARM: sun4i: dt: Add USB host bindings Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-03-02 03:26:23 +08:00
usbphy: phy@01c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun4i-a10-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
reg-names = "phy_ctrl", "pmu1", "pmu2";
clocks = <&usb_clk 8>;
clock-names = "usb_phy";
resets = <&usb_clk 1>, <&usb_clk 2>;
reset-names = "usb1_reset", "usb2_reset";
status = "disabled";
};
ehci0: usb@01c14000 {
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
reg = <0x01c14000 0x100>;
interrupts = <39>;
clocks = <&ahb_gates 1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci0: usb@01c14400 {
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
reg = <0x01c14400 0x100>;
interrupts = <64>;
clocks = <&usb_clk 6>, <&ahb_gates 2>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ARM: dt: sun4i: Add A10 SPI controller nodes The A10 has 4 SPI controllers that are now supported. Add them in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-23 05:35:55 +08:00
spi2: spi@01c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <12>;
clocks = <&ahb_gates 22>, <&spi2_clk>;
clock-names = "ahb", "mod";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ARM: sun4i: dt: Add ahci / sata support This patch adds sunxi sata support to A10 boards that have such a connector. Some boards also feature a regulator via a GPIO and support for this is also added. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-03-02 03:26:21 +08:00
ahci: sata@01c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <56>;
clocks = <&pll6 0>, <&ahb_gates 25>;
status = "disabled";
};
ARM: sun4i: dt: Add USB host bindings Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-03-02 03:26:23 +08:00
ehci1: usb@01c1c000 {
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
reg = <0x01c1c000 0x100>;
interrupts = <40>;
clocks = <&ahb_gates 3>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@01c1c400 {
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
reg = <0x01c1c400 0x100>;
interrupts = <65>;
clocks = <&usb_clk 7>, <&ahb_gates 4>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ARM: dt: sun4i: Add A10 SPI controller nodes The A10 has 4 SPI controllers that are now supported. Add them in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-23 05:35:55 +08:00
spi3: spi@01c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
interrupts = <50>;
clocks = <&ahb_gates 23>, <&spi3_clk>;
clock-names = "ahb", "mod";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
intc: interrupt-controller@01c20400 {
ARM: sunxi: dt: Convert to the new irq controller compatibles Switch the device tree to the new compatibles introduced in the irqchip drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-08 04:50:26 +08:00
compatible = "allwinner,sun4i-a10-ic";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
sunxi: dts: Report the pinctrl nodes as gpio-controllers Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-01-28 02:26:05 +08:00
pio: pinctrl@01c20800 {
ARM: sunxi: Add the sun4i pinctrl and gpio nodes Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-26 22:36:54 +08:00
compatible = "allwinner,sun4i-a10-pinctrl";
reg = <0x01c20800 0x400>;
ARM: sunxi: dt: Register the pio node as interrupt controller Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-06 21:00:48 +08:00
interrupts = <28>;
arm: sunxi: Add clock to pinctrl node The port controller needs the apb0_pio clock enabled to be able to work. This commit declares that on the device tree. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-28 05:20:41 +08:00
clocks = <&apb0_gates 5>;
sunxi: dts: Report the pinctrl nodes as gpio-controllers Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-01-28 02:26:05 +08:00
gpio-controller;
ARM: sunxi: dt: Register the pio node as interrupt controller Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-06 21:00:48 +08:00
interrupt-controller;
ARM: sunxi: Add the sun4i pinctrl and gpio nodes Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-26 22:36:54 +08:00
#address-cells = <1>;
#size-cells = <0>;
sunxi: dts: Report the pinctrl nodes as gpio-controllers Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-01-28 02:26:05 +08:00
#gpio-cells = <3>;
ARM: sunxi: Add the pin groups for UART0 and UART1 on sun4i Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-26 22:36:55 +08:00
uart0_pins_a: uart0@0 {
allwinner,pins = "PB22", "PB23";
allwinner,function = "uart0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart0_pins_b: uart0@1 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart1_pins_a: uart1@0 {
allwinner,pins = "PA10", "PA11";
allwinner,function = "uart1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
ARM: sun4i: dt: Add i2c muxing options The i2c controller found on the Allwinner A10 has only one muxing option available for each controller. Add them to the dtsi Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
2013-03-10 20:44:38 +08:00
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
i2c1_pins_a: i2c1@0 {
allwinner,pins = "PB18", "PB19";
allwinner,function = "i2c1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
i2c2_pins_a: i2c2@0 {
allwinner,pins = "PB20", "PB21";
allwinner,function = "i2c2";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next Pull networking updates from David Miller: "This is a re-do of the net-next pull request for the current merge window. The only difference from the one I made the other day is that this has Eliezer's interface renames and the timeout handling changes made based upon your feedback, as well as a few bug fixes that have trickeled in. Highlights: 1) Low latency device polling, eliminating the cost of interrupt handling and context switches. Allows direct polling of a network device from socket operations, such as recvmsg() and poll(). Currently ixgbe, mlx4, and bnx2x support this feature. Full high level description, performance numbers, and design in commit 0a4db187a999 ("Merge branch 'll_poll'") From Eliezer Tamir. 2) With the routing cache removed, ip_check_mc_rcu() gets exercised more than ever before in the case where we have lots of multicast addresses. Use a hash table instead of a simple linked list, from Eric Dumazet. 3) Add driver for Atheros CQA98xx 802.11ac wireless devices, from Bartosz Markowski, Janusz Dziedzic, Kalle Valo, Marek Kwaczynski, Marek Puzyniak, Michal Kazior, and Sujith Manoharan. 4) Support reporting the TUN device persist flag to userspace, from Pavel Emelyanov. 5) Allow controlling network device VF link state using netlink, from Rony Efraim. 6) Support GRE tunneling in openvswitch, from Pravin B Shelar. 7) Adjust SOCK_MIN_RCVBUF and SOCK_MIN_SNDBUF for modern times, from Daniel Borkmann and Eric Dumazet. 8) Allow controlling of TCP quickack behavior on a per-route basis, from Cong Wang. 9) Several bug fixes and improvements to vxlan from Stephen Hemminger, Pravin B Shelar, and Mike Rapoport. In particular, support receiving on multiple UDP ports. 10) Major cleanups, particular in the area of debugging and cookie lifetime handline, to the SCTP protocol code. From Daniel Borkmann. 11) Allow packets to cross network namespaces when traversing tunnel devices. From Nicolas Dichtel. 12) Allow monitoring netlink traffic via AF_PACKET sockets, in a manner akin to how we monitor real network traffic via ptype_all. From Daniel Borkmann. 13) Several bug fixes and improvements for the new alx device driver, from Johannes Berg. 14) Fix scalability issues in the netem packet scheduler's time queue, by using an rbtree. From Eric Dumazet. 15) Several bug fixes in TCP loss recovery handling, from Yuchung Cheng. 16) Add support for GSO segmentation of MPLS packets, from Simon Horman. 17) Make network notifiers have a real data type for the opaque pointer that's passed into them. Use this to properly handle network device flag changes in arp_netdev_event(). From Jiri Pirko and Timo Teräs. 18) Convert several drivers over to module_pci_driver(), from Peter Huewe. 19) tcp_fixup_rcvbuf() can loop 500 times over loopback, just use a O(1) calculation instead. From Eric Dumazet. 20) Support setting of explicit tunnel peer addresses in ipv6, just like ipv4. From Nicolas Dichtel. 21) Protect x86 BPF JIT against spraying attacks, from Eric Dumazet. 22) Prevent a single high rate flow from overruning an individual cpu during RX packet processing via selective flow shedding. From Willem de Bruijn. 23) Don't use spinlocks in TCP md5 signing fast paths, from Eric Dumazet. 24) Don't just drop GSO packets which are above the TBF scheduler's burst limit, chop them up so they are in-bounds instead. Also from Eric Dumazet. 25) VLAN offloads are missed when configured on top of a bridge, fix from Vlad Yasevich. 26) Support IPV6 in ping sockets. From Lorenzo Colitti. 27) Receive flow steering targets should be updated at poll() time too, from David Majnemer. 28) Fix several corner case regressions in PMTU/redirect handling due to the routing cache removal, from Timo Teräs. 29) We have to be mindful of ipv4 mapped ipv6 sockets in upd_v6_push_pending_frames(). From Hannes Frederic Sowa. 30) Fix L2TP sequence number handling bugs, from James Chapman." * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1214 commits) drivers/net: caif: fix wrong rtnl_is_locked() usage drivers/net: enic: release rtnl_lock on error-path vhost-net: fix use-after-free in vhost_net_flush net: mv643xx_eth: do not use port number as platform device id net: sctp: confirm route during forward progress virtio_net: fix race in RX VQ processing virtio: support unlocked queue poll net/cadence/macb: fix bug/typo in extracting gem_irq_read_clear bit Documentation: Fix references to defunct linux-net@vger.kernel.org net/fs: change busy poll time accounting net: rename low latency sockets functions to busy poll bridge: fix some kernel warning in multicast timer sfc: Fix memory leak when discarding scattered packets sit: fix tunnel update via netlink dt:net:stmmac: Add dt specific phy reset callback support. dt:net:stmmac: Add support to dwmac version 3.610 and 3.710 dt:net:stmmac: Allocate platform data only if its NULL. net:stmmac: fix memleak in the open method ipv6: rt6_check_neigh should successfully verify neigh if no NUD information are available net: ipv6: fix wrong ping_v6_sendmsg return value ...
2013-07-10 09:24:39 +08:00
ARM: sun4i: Add muxing options for the ethernet controller The EMAC only has one pinset available for muxing, so hopefully, we cover all cases. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-05-30 11:49:22 +08:00
emac_pins_a: emac0@0 {
allwinner,pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
allwinner,function = "emac";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
ARM: sunxi: Add the sun4i pinctrl and gpio nodes Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-26 22:36:54 +08:00
};
ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi The UART0 is only available on the Allwinner A10 SoCs, and not on the A13, so move the uart0 node to sun4i-a10.dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar> Tested-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:25:03 +08:00
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
timer@01c20c00 {
ARM: sunxi: dt: Convert to the new clocksource compatible Switch the device tree to the new compatibles introduced in the timer driver to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-02-06 17:40:32 +08:00
compatible = "allwinner,sun4i-a10-timer";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20c00 0x90>;
interrupts = <22>;
clocks = <&osc24M>;
};
wdt: watchdog@01c20c90 {
ARM: sunxi: dt: Update the watchdog compatibles The watchdog compatibles were following a different pattern than the one found in the other devices. Now that the driver supports the right pattern, switch to it in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-08 05:29:26 +08:00
compatible = "allwinner,sun4i-a10-wdt";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
reg = <0x01c20c90 0x10>;
};
ARM: dts: sun4i/sun7i: add RTC node Add the RTC node to DTS for Allwinner A10 and Allwinner A20. Signed-off-by: Carlo Caione <carlo.caione@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-10-17 02:30:26 +08:00
rtc: rtc@01c20d00 {
arch/arm/boot/dts/sun4i-a10.dtsi: convert to the new RTC compatibles Switch the device tree to the new compatibles introduced in the RTC drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-04-04 05:50:03 +08:00
compatible = "allwinner,sun4i-a10-rtc";
ARM: dts: sun4i/sun7i: add RTC node Add the RTC node to DTS for Allwinner A10 and Allwinner A20. Signed-off-by: Carlo Caione <carlo.caione@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-10-17 02:30:26 +08:00
reg = <0x01c20d00 0x20>;
interrupts = <24>;
};
ARM: sunxi: dt: Add sunxi-sid to dts for sun4i, sun5i and sun7i This patch shall add support for the sunxi-sid driver to the device tree for A10, A10s, A13 and A20. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-09-03 18:33:28 +08:00
sid: eeprom@01c23800 {
ARM: sunxi: dt: Convert to the new SID compatibles Switch the device tree to the new compatibles introduced in the SID drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-08 05:20:40 +08:00
compatible = "allwinner,sun4i-a10-sid";
ARM: sunxi: dt: Add sunxi-sid to dts for sun4i, sun5i and sun7i This patch shall add support for the sunxi-sid driver to the device tree for A10, A10s, A13 and A20. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-09-03 18:33:28 +08:00
reg = <0x01c23800 0x10>;
};
ARM: dts: sun4i: Add rtp controller node Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-01-01 00:20:50 +08:00
rtp: rtp@01c25000 {
ARM: sunxi: dt: Change the touchscreen compatibles Switch the device tree touchscreen compatibles to have a common pattern accross all Allwinner SoCs. Since the touchscreen driver has not been merged yet, it has no side effect. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-02 21:52:40 +08:00
compatible = "allwinner,sun4i-a10-ts";
ARM: dts: sun4i: Add rtp controller node Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-01-01 00:20:50 +08:00
reg = <0x01c25000 0x100>;
interrupts = <29>;
};
ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi The UART0 is only available on the Allwinner A10 SoCs, and not on the A13, so move the uart0 node to sun4i-a10.dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar> Tested-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:25:03 +08:00
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
arm: sunxi: use the right clock phandles for UARTs All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-28 05:20:39 +08:00
clocks = <&apb1_gates 16>;
ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi The UART0 is only available on the Allwinner A10 SoCs, and not on the A13, so move the uart0 node to sun4i-a10.dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar> Tested-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:25:03 +08:00
status = "disabled";
};
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 17>;
status = "disabled";
};
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
uart2: serial@01c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
arm: sunxi: use the right clock phandles for UARTs All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-28 05:20:39 +08:00
clocks = <&apb1_gates 18>;
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
status = "disabled";
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-14 03:07:37 +08:00
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 19>;
status = "disabled";
};
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
uart4: serial@01c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <17>;
reg-shift = <2>;
reg-io-width = <4>;
arm: sunxi: use the right clock phandles for UARTs All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-28 05:20:39 +08:00
clocks = <&apb1_gates 20>;
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
status = "disabled";
};
uart5: serial@01c29400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29400 0x400>;
interrupts = <18>;
reg-shift = <2>;
reg-io-width = <4>;
arm: sunxi: use the right clock phandles for UARTs All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-28 05:20:39 +08:00
clocks = <&apb1_gates 21>;
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
status = "disabled";
};
uart6: serial@01c29800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29800 0x400>;
interrupts = <19>;
reg-shift = <2>;
reg-io-width = <4>;
arm: sunxi: use the right clock phandles for UARTs All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-28 05:20:39 +08:00
clocks = <&apb1_gates 22>;
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
status = "disabled";
};
uart7: serial@01c29c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29c00 0x400>;
interrupts = <20>;
reg-shift = <2>;
reg-io-width = <4>;
arm: sunxi: use the right clock phandles for UARTs All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-28 05:20:39 +08:00
clocks = <&apb1_gates 23>;
ARM: sunxi: dt: Add A10 UARTs to the dtsi. The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-02-21 09:38:27 +08:00
status = "disabled";
};
ARM: sunxi: dt: Add i2c controller nodes to the DTSI The Allwinner A10 and A13 both have 3 i2c controller embedded. Add those to the common sunxi dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
2013-03-10 20:34:36 +08:00
i2c0: i2c@01c2ac00 {
compatible = "allwinner,sun4i-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
clocks = <&apb1_gates 0>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@01c2b000 {
compatible = "allwinner,sun4i-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <8>;
clocks = <&apb1_gates 1>;
clock-frequency = <100000>;
status = "disabled";
};
i2c2: i2c@01c2b400 {
compatible = "allwinner,sun4i-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <9>;
clocks = <&apb1_gates 2>;
clock-frequency = <100000>;
status = "disabled";
};
ARM: sunxi: Add the sun4i pinctrl and gpio nodes Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-26 22:36:54 +08:00
};
ARM: sunxi: Add missing sun4i.dtsi file Patch f055f1f6 [ARM: sunxi: Add sun4i and cubieboard support] missed this sun4i.dtsi include file. This patch finally brings it upstream enabling support for sun4i boards. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-26 22:46:12 +08:00
};