License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-17 06:20:36 +08:00
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/*
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* linux/arch/alpha/kernel/sys_noritake.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Code supporting the NORITAKE (AlphaServer 1000A),
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* CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A).
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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2012-03-29 01:11:12 +08:00
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#include <asm/mce.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/core_apecs.h>
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#include <asm/core_cia.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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/* Note mask bit is true for ENABLED irqs. */
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static int cached_irq_mask;
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static inline void
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noritake_update_irq_hw(int irq, int mask)
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{
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int port = 0x54a;
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if (irq >= 32) {
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mask >>= 16;
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port = 0x54c;
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}
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outw(mask, port);
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}
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static void
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2011-02-06 22:32:46 +08:00
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noritake_enable_irq(struct irq_data *d)
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2005-04-17 06:20:36 +08:00
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{
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2011-02-06 22:32:46 +08:00
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noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16));
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2005-04-17 06:20:36 +08:00
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}
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static void
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2011-02-06 22:32:46 +08:00
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noritake_disable_irq(struct irq_data *d)
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2005-04-17 06:20:36 +08:00
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{
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2011-02-06 22:32:46 +08:00
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noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16)));
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2005-04-17 06:20:36 +08:00
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}
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2009-06-17 06:33:25 +08:00
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static struct irq_chip noritake_irq_type = {
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2009-12-01 11:51:31 +08:00
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.name = "NORITAKE",
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2011-02-06 22:32:46 +08:00
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.irq_unmask = noritake_enable_irq,
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.irq_mask = noritake_disable_irq,
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.irq_mask_ack = noritake_disable_irq,
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2005-04-17 06:20:36 +08:00
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};
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static void
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2006-10-08 21:36:08 +08:00
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noritake_device_interrupt(unsigned long vector)
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2005-04-17 06:20:36 +08:00
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{
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unsigned long pld;
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unsigned int i;
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/* Read the interrupt summary registers of NORITAKE */
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pld = (((unsigned long) inw(0x54c) << 32)
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| ((unsigned long) inw(0x54a) << 16)
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| ((unsigned long) inb(0xa0) << 8)
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| inb(0x20));
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/*
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* Now for every possible bit set, work through them and call
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* the appropriate interrupt handler.
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*/
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while (pld) {
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i = ffz(~pld);
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pld &= pld - 1; /* clear least bit set */
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if (i < 16) {
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2006-10-08 21:36:08 +08:00
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isa_device_interrupt(vector);
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2005-04-17 06:20:36 +08:00
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} else {
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2006-10-08 21:37:32 +08:00
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handle_irq(i);
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2005-04-17 06:20:36 +08:00
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}
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}
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}
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static void
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2006-10-08 21:36:08 +08:00
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noritake_srm_device_interrupt(unsigned long vector)
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2005-04-17 06:20:36 +08:00
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{
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int irq;
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irq = (vector - 0x800) >> 4;
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/*
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* I really hate to do this, too, but the NORITAKE SRM console also
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* reports PCI vectors *lower* than I expected from the bit numbers
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* in the documentation.
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* But I really don't want to change the fixup code for allocation
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* of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
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* look nice and clean now.
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* So, here's this additional grotty hack... :-(
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*/
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if (irq >= 16)
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irq = irq + 1;
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2006-10-08 21:37:32 +08:00
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handle_irq(irq);
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2005-04-17 06:20:36 +08:00
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}
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static void __init
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noritake_init_irq(void)
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{
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long i;
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if (alpha_using_srm)
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alpha_mv.device_interrupt = noritake_srm_device_interrupt;
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outw(0, 0x54a);
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outw(0, 0x54c);
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for (i = 16; i < 48; ++i) {
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2011-03-26 05:17:31 +08:00
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irq_set_chip_and_handler(i, &noritake_irq_type,
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handle_level_irq);
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2011-02-06 22:32:46 +08:00
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irq_set_status_flags(i, IRQ_LEVEL);
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2005-04-17 06:20:36 +08:00
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}
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init_i8259a_irqs();
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common_init_isa_dma();
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}
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/*
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* PCI Fixup configuration.
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*
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* Summary @ 0x542, summary register #1:
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* Bit Meaning
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* 0 All valid ints from summary regs 2 & 3
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* 1 QLOGIC ISP1020A SCSI
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* 2 Interrupt Line A from slot 0
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* 3 Interrupt Line B from slot 0
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* 4 Interrupt Line A from slot 1
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* 5 Interrupt line B from slot 1
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* 6 Interrupt Line A from slot 2
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* 7 Interrupt Line B from slot 2
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* 8 Interrupt Line A from slot 3
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* 9 Interrupt Line B from slot 3
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*10 Interrupt Line A from slot 4
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*11 Interrupt Line B from slot 4
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*12 Interrupt Line A from slot 5
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*13 Interrupt Line B from slot 5
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*14 Interrupt Line A from slot 6
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*15 Interrupt Line B from slot 6
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*
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* Summary @ 0x544, summary register #2:
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* Bit Meaning
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* 0 OR of all unmasked ints in SR #2
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* 1 OR of secondary bus ints
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* 2 Interrupt Line C from slot 0
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* 3 Interrupt Line D from slot 0
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* 4 Interrupt Line C from slot 1
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* 5 Interrupt line D from slot 1
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* 6 Interrupt Line C from slot 2
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* 7 Interrupt Line D from slot 2
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* 8 Interrupt Line C from slot 3
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* 9 Interrupt Line D from slot 3
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*10 Interrupt Line C from slot 4
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*11 Interrupt Line D from slot 4
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*12 Interrupt Line C from slot 5
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*13 Interrupt Line D from slot 5
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*14 Interrupt Line C from slot 6
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*15 Interrupt Line D from slot 6
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*
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* The device to slot mapping looks like:
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*
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* Slot Device
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* 7 Intel PCI-EISA bridge chip
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* 8 DEC PCI-PCI bridge chip
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* 11 PCI on board slot 0
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* 12 PCI on board slot 1
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* 13 PCI on board slot 2
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*
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*
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* This two layered interrupt approach means that we allocate IRQ 16 and
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* above for PCI interrupts. The IRQ relates to which bit the interrupt
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* comes in on. This makes interrupt processing much easier.
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*/
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2017-10-26 22:54:15 +08:00
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static int
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2011-06-10 22:30:21 +08:00
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noritake_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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2005-04-17 06:20:36 +08:00
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{
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2017-10-26 22:54:15 +08:00
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static char irq_tab[15][5] = {
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2005-04-17 06:20:36 +08:00
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/*INT INTA INTB INTC INTD */
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/* note: IDSELs 16, 17, and 25 are CORELLE only */
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{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */
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{ -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */
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{ -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
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{ -1, -1, -1, -1, -1}, /* IdSel 19, PPB */
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{ -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
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{ -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
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{ 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */
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{ 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */
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{ 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */
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{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */
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/* The following 5 are actually on PCI bus 1, which is
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across the built-in bridge of the NORITAKE only. */
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{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */
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{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */
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{16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */
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{16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */
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{16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */
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};
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const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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2017-10-26 22:54:15 +08:00
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static u8
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2005-04-17 06:20:36 +08:00
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noritake_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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int slot, pin = *pinp;
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if (dev->bus->number == 0) {
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slot = PCI_SLOT(dev->devfn);
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}
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/* Check for the built-in bridge */
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else if (PCI_SLOT(dev->bus->self->devfn) == 8) {
|
|
|
|
|
slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Must be a card-based bridge. */
|
|
|
|
|
do {
|
|
|
|
|
if (PCI_SLOT(dev->bus->self->devfn) == 8) {
|
|
|
|
|
slot = PCI_SLOT(dev->devfn) + 15;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2008-12-10 07:12:07 +08:00
|
|
|
pin = pci_swizzle_interrupt_pin(dev, pin);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* Move up the chain of bridges. */
|
|
|
|
|
dev = dev->bus->self;
|
|
|
|
|
/* Slot of the next bridge. */
|
|
|
|
|
slot = PCI_SLOT(dev->devfn);
|
|
|
|
|
} while (dev->bus->self);
|
|
|
|
|
}
|
|
|
|
|
*pinp = pin;
|
|
|
|
|
return slot;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
|
|
|
|
|
static void
|
2006-10-08 21:44:38 +08:00
|
|
|
noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
#define MCHK_NO_DEVSEL 0x205U
|
|
|
|
|
#define MCHK_NO_TABT 0x204U
|
|
|
|
|
|
|
|
|
|
struct el_common *mchk_header;
|
|
|
|
|
unsigned int code;
|
|
|
|
|
|
|
|
|
|
mchk_header = (struct el_common *)la_ptr;
|
|
|
|
|
|
|
|
|
|
/* Clear the error before any reporting. */
|
|
|
|
|
mb();
|
|
|
|
|
mb(); /* magic */
|
|
|
|
|
draina();
|
|
|
|
|
apecs_pci_clr_err();
|
|
|
|
|
wrmces(0x7);
|
|
|
|
|
mb();
|
|
|
|
|
|
|
|
|
|
code = mchk_header->code;
|
2006-10-08 21:44:38 +08:00
|
|
|
process_mcheck_info(vector, la_ptr, "NORITAKE APECS",
|
2005-04-17 06:20:36 +08:00
|
|
|
(mcheck_expected(0)
|
|
|
|
|
&& (code == MCHK_NO_DEVSEL
|
|
|
|
|
|| code == MCHK_NO_TABT)));
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The System Vectors
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
|
|
|
|
|
struct alpha_machine_vector noritake_mv __initmv = {
|
|
|
|
|
.vector_name = "Noritake",
|
|
|
|
|
DO_EV4_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_APECS_IO,
|
|
|
|
|
.machine_check = noritake_apecs_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = EISA_DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 48,
|
|
|
|
|
.device_interrupt = noritake_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = apecs_init_arch,
|
|
|
|
|
.init_irq = noritake_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = common_init_pci,
|
|
|
|
|
.pci_map_irq = noritake_map_irq,
|
|
|
|
|
.pci_swizzle = noritake_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(noritake)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
|
|
|
|
|
struct alpha_machine_vector noritake_primo_mv __initmv = {
|
|
|
|
|
.vector_name = "Noritake-Primo",
|
|
|
|
|
DO_EV5_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_CIA_IO,
|
|
|
|
|
.machine_check = cia_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = EISA_DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = CIA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 48,
|
|
|
|
|
.device_interrupt = noritake_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = cia_init_arch,
|
|
|
|
|
.init_irq = noritake_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = cia_init_pci,
|
|
|
|
|
.kill_arch = cia_kill_arch,
|
|
|
|
|
.pci_map_irq = noritake_map_irq,
|
|
|
|
|
.pci_swizzle = noritake_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(noritake_primo)
|
|
|
|
|
#endif
|