2018-10-17 16:53:14 +08:00
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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/* Copyright (c) 2018 Mellanox Technologies. All rights reserved */
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#include <linux/netdevice.h>
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#include <linux/netlink.h>
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2018-10-17 16:53:16 +08:00
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#include <linux/random.h>
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#include <net/vxlan.h>
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2018-10-17 16:53:14 +08:00
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2018-10-17 16:53:16 +08:00
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#include "reg.h"
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2018-10-17 16:53:14 +08:00
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#include "spectrum_nve.h"
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2018-10-17 16:53:16 +08:00
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/* Eth (18B) | IPv6 (40B) | UDP (8B) | VxLAN (8B) | Eth (14B) | IPv6 (40B)
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*
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* In the worst case - where we have a VLAN tag on the outer Ethernet
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* header and IPv6 in overlay and underlay - we need to parse 128 bytes
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*/
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#define MLXSW_SP_NVE_VXLAN_PARSING_DEPTH 128
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#define MLXSW_SP_NVE_DEFAULT_PARSING_DEPTH 96
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2018-11-21 16:02:50 +08:00
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#define MLXSW_SP_NVE_VXLAN_SUPPORTED_FLAGS (VXLAN_F_UDP_ZERO_CSUM_TX | \
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VXLAN_F_LEARN)
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2018-10-17 16:53:16 +08:00
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2018-10-17 16:53:14 +08:00
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static bool mlxsw_sp1_nve_vxlan_can_offload(const struct mlxsw_sp_nve *nve,
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const struct net_device *dev,
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struct netlink_ext_ack *extack)
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{
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2018-10-17 16:53:16 +08:00
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struct vxlan_dev *vxlan = netdev_priv(dev);
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struct vxlan_config *cfg = &vxlan->cfg;
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if (cfg->saddr.sa.sa_family != AF_INET) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: Only IPv4 underlay is supported");
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return false;
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}
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if (vxlan_addr_multicast(&cfg->remote_ip)) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: Multicast destination IP is not supported");
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return false;
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}
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if (vxlan_addr_any(&cfg->saddr)) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: Source address must be specified");
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return false;
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}
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if (cfg->remote_ifindex) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: Local interface is not supported");
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return false;
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}
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if (cfg->port_min || cfg->port_max) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: Only default UDP source port range is supported");
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return false;
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}
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if (cfg->tos != 1) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: TOS must be configured to inherit");
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return false;
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}
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if (cfg->flags & VXLAN_F_TTL_INHERIT) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: TTL must not be configured to inherit");
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return false;
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}
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if (!(cfg->flags & VXLAN_F_UDP_ZERO_CSUM_TX)) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: UDP checksum is not supported");
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return false;
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}
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if (cfg->flags & ~MLXSW_SP_NVE_VXLAN_SUPPORTED_FLAGS) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: Unsupported flag");
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return false;
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}
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if (cfg->ttl == 0) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: TTL must not be configured to 0");
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return false;
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}
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if (cfg->label != 0) {
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NL_SET_ERR_MSG_MOD(extack, "VxLAN: Flow label must be configured to 0");
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return false;
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}
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return true;
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2018-10-17 16:53:14 +08:00
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}
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static void mlxsw_sp_nve_vxlan_config(const struct mlxsw_sp_nve *nve,
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const struct net_device *dev,
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struct mlxsw_sp_nve_config *config)
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{
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2018-10-17 16:53:16 +08:00
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struct vxlan_dev *vxlan = netdev_priv(dev);
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struct vxlan_config *cfg = &vxlan->cfg;
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config->type = MLXSW_SP_NVE_TYPE_VXLAN;
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config->ttl = cfg->ttl;
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config->flowlabel = cfg->label;
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config->learning_en = cfg->flags & VXLAN_F_LEARN ? 1 : 0;
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config->ul_tb_id = RT_TABLE_MAIN;
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config->ul_proto = MLXSW_SP_L3_PROTO_IPV4;
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config->ul_sip.addr4 = cfg->saddr.sin.sin_addr.s_addr;
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config->udp_dport = cfg->dst_port;
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}
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static int mlxsw_sp_nve_parsing_set(struct mlxsw_sp *mlxsw_sp,
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unsigned int parsing_depth,
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__be16 udp_dport)
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{
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char mprs_pl[MLXSW_REG_MPRS_LEN];
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mlxsw_reg_mprs_pack(mprs_pl, parsing_depth, be16_to_cpu(udp_dport));
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return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
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}
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2019-01-23 22:32:56 +08:00
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static void
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mlxsw_sp_nve_vxlan_config_prepare(char *tngcr_pl,
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const struct mlxsw_sp_nve_config *config)
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{
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u8 udp_sport;
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mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, true,
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config->ttl);
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/* VxLAN driver's default UDP source port range is 32768 (0x8000)
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* to 60999 (0xee47). Set the upper 8 bits of the UDP source port
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* to a random number between 0x80 and 0xee
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*/
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get_random_bytes(&udp_sport, sizeof(udp_sport));
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udp_sport = (udp_sport % (0xee - 0x80 + 1)) + 0x80;
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mlxsw_reg_tngcr_nve_udp_sport_prefix_set(tngcr_pl, udp_sport);
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mlxsw_reg_tngcr_usipv4_set(tngcr_pl, be32_to_cpu(config->ul_sip.addr4));
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}
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2018-10-17 16:53:16 +08:00
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static int
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mlxsw_sp1_nve_vxlan_config_set(struct mlxsw_sp *mlxsw_sp,
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const struct mlxsw_sp_nve_config *config)
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{
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char tngcr_pl[MLXSW_REG_TNGCR_LEN];
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u16 ul_vr_id;
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int err;
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err = mlxsw_sp_router_tb_id_vr_id(mlxsw_sp, config->ul_tb_id,
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&ul_vr_id);
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if (err)
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return err;
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2019-01-23 22:32:56 +08:00
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mlxsw_sp_nve_vxlan_config_prepare(tngcr_pl, config);
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2018-10-17 16:53:16 +08:00
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mlxsw_reg_tngcr_learn_enable_set(tngcr_pl, config->learning_en);
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mlxsw_reg_tngcr_underlay_virtual_router_set(tngcr_pl, ul_vr_id);
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return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl);
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}
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static void mlxsw_sp1_nve_vxlan_config_clear(struct mlxsw_sp *mlxsw_sp)
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{
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char tngcr_pl[MLXSW_REG_TNGCR_LEN];
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mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, false, 0);
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mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl);
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}
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static int mlxsw_sp1_nve_vxlan_rtdp_set(struct mlxsw_sp *mlxsw_sp,
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unsigned int tunnel_index)
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{
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char rtdp_pl[MLXSW_REG_RTDP_LEN];
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mlxsw_reg_rtdp_pack(rtdp_pl, MLXSW_REG_RTDP_TYPE_NVE, tunnel_index);
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return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rtdp), rtdp_pl);
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2018-10-17 16:53:14 +08:00
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}
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static int mlxsw_sp1_nve_vxlan_init(struct mlxsw_sp_nve *nve,
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const struct mlxsw_sp_nve_config *config)
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{
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2018-10-17 16:53:16 +08:00
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struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp;
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int err;
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err = mlxsw_sp_nve_parsing_set(mlxsw_sp,
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MLXSW_SP_NVE_VXLAN_PARSING_DEPTH,
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config->udp_dport);
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if (err)
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return err;
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err = mlxsw_sp1_nve_vxlan_config_set(mlxsw_sp, config);
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if (err)
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goto err_config_set;
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err = mlxsw_sp1_nve_vxlan_rtdp_set(mlxsw_sp, nve->tunnel_index);
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if (err)
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goto err_rtdp_set;
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err = mlxsw_sp_router_nve_promote_decap(mlxsw_sp, config->ul_tb_id,
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config->ul_proto,
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&config->ul_sip,
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nve->tunnel_index);
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if (err)
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goto err_promote_decap;
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return 0;
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err_promote_decap:
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err_rtdp_set:
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mlxsw_sp1_nve_vxlan_config_clear(mlxsw_sp);
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err_config_set:
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mlxsw_sp_nve_parsing_set(mlxsw_sp, MLXSW_SP_NVE_DEFAULT_PARSING_DEPTH,
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config->udp_dport);
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return err;
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2018-10-17 16:53:14 +08:00
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}
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static void mlxsw_sp1_nve_vxlan_fini(struct mlxsw_sp_nve *nve)
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{
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2018-10-17 16:53:16 +08:00
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struct mlxsw_sp_nve_config *config = &nve->config;
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struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp;
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mlxsw_sp_router_nve_demote_decap(mlxsw_sp, config->ul_tb_id,
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config->ul_proto, &config->ul_sip);
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mlxsw_sp1_nve_vxlan_config_clear(mlxsw_sp);
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mlxsw_sp_nve_parsing_set(mlxsw_sp, MLXSW_SP_NVE_DEFAULT_PARSING_DEPTH,
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config->udp_dport);
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2018-10-17 16:53:14 +08:00
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}
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2018-12-08 03:55:12 +08:00
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static int
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2019-01-17 07:06:52 +08:00
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mlxsw_sp_nve_vxlan_fdb_replay(const struct net_device *nve_dev, __be32 vni,
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struct netlink_ext_ack *extack)
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2018-12-08 03:55:12 +08:00
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{
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if (WARN_ON(!netif_is_vxlan(nve_dev)))
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return -EINVAL;
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2019-01-17 07:06:54 +08:00
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return vxlan_fdb_replay(nve_dev, vni, &mlxsw_sp_switchdev_notifier,
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extack);
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2018-12-08 03:55:12 +08:00
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}
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2018-12-08 03:55:14 +08:00
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static void
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mlxsw_sp_nve_vxlan_clear_offload(const struct net_device *nve_dev, __be32 vni)
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{
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if (WARN_ON(!netif_is_vxlan(nve_dev)))
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return;
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vxlan_fdb_clear_offload(nve_dev, vni);
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}
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2018-10-17 16:53:14 +08:00
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const struct mlxsw_sp_nve_ops mlxsw_sp1_nve_vxlan_ops = {
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.type = MLXSW_SP_NVE_TYPE_VXLAN,
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.can_offload = mlxsw_sp1_nve_vxlan_can_offload,
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.nve_config = mlxsw_sp_nve_vxlan_config,
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.init = mlxsw_sp1_nve_vxlan_init,
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.fini = mlxsw_sp1_nve_vxlan_fini,
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2018-12-08 03:55:12 +08:00
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.fdb_replay = mlxsw_sp_nve_vxlan_fdb_replay,
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2018-12-08 03:55:14 +08:00
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.fdb_clear_offload = mlxsw_sp_nve_vxlan_clear_offload,
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2018-10-17 16:53:14 +08:00
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};
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static bool mlxsw_sp2_nve_vxlan_can_offload(const struct mlxsw_sp_nve *nve,
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const struct net_device *dev,
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struct netlink_ext_ack *extack)
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{
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return false;
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}
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static int mlxsw_sp2_nve_vxlan_init(struct mlxsw_sp_nve *nve,
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const struct mlxsw_sp_nve_config *config)
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{
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return -EOPNOTSUPP;
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}
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static void mlxsw_sp2_nve_vxlan_fini(struct mlxsw_sp_nve *nve)
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{
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}
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const struct mlxsw_sp_nve_ops mlxsw_sp2_nve_vxlan_ops = {
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.type = MLXSW_SP_NVE_TYPE_VXLAN,
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.can_offload = mlxsw_sp2_nve_vxlan_can_offload,
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.nve_config = mlxsw_sp_nve_vxlan_config,
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.init = mlxsw_sp2_nve_vxlan_init,
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.fini = mlxsw_sp2_nve_vxlan_fini,
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2018-12-08 03:55:12 +08:00
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.fdb_replay = mlxsw_sp_nve_vxlan_fdb_replay,
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2018-12-08 03:55:14 +08:00
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.fdb_clear_offload = mlxsw_sp_nve_vxlan_clear_offload,
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2018-10-17 16:53:14 +08:00
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};
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