2019-06-03 13:44:50 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2015-10-02 03:13:58 +08:00
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/*
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* Copyright (C) 2014-2015 ARM Ltd.
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*/
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#ifndef __DMA_IOMMU_H
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#define __DMA_IOMMU_H
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2019-05-20 15:29:26 +08:00
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#include <linux/errno.h>
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2018-05-08 20:14:33 +08:00
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#include <linux/types.h>
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2015-10-02 03:13:58 +08:00
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#ifdef CONFIG_IOMMU_DMA
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2017-04-26 21:46:20 +08:00
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#include <linux/dma-mapping.h>
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2015-10-02 03:13:58 +08:00
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#include <linux/iommu.h>
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2016-09-13 00:13:59 +08:00
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#include <linux/msi.h>
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2015-10-02 03:13:58 +08:00
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/* Domain management interface for IOMMU drivers */
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int iommu_get_dma_cookie(struct iommu_domain *domain);
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2017-01-20 04:57:46 +08:00
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int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base);
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2015-10-02 03:13:58 +08:00
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void iommu_put_dma_cookie(struct iommu_domain *domain);
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/* Setup call for arch DMA mapping code */
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2019-05-20 15:29:29 +08:00
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void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size);
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2015-10-02 03:13:58 +08:00
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2016-09-13 00:13:59 +08:00
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/* The DMA API isn't _quite_ the whole story, though... */
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2019-05-01 21:58:19 +08:00
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/*
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* iommu_dma_prepare_msi() - Map the MSI page in the IOMMU device
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*
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* The MSI page will be stored in @desc.
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*
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* Return: 0 on success otherwise an error describing the failure.
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*/
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int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
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/* Update the MSI message if required. */
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void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg);
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2017-03-17 01:00:19 +08:00
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void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list);
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2016-09-13 00:13:59 +08:00
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2020-11-24 16:20:52 +08:00
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void iommu_dma_free_cpu_cached_iovas(unsigned int cpu,
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struct iommu_domain *domain);
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2019-05-20 15:29:26 +08:00
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#else /* CONFIG_IOMMU_DMA */
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2015-10-02 03:13:58 +08:00
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struct iommu_domain;
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2019-05-01 21:58:19 +08:00
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struct msi_desc;
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2016-09-13 00:13:59 +08:00
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struct msi_msg;
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2017-05-18 21:13:57 +08:00
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struct device;
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2015-10-02 03:13:58 +08:00
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2019-05-20 15:29:29 +08:00
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static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base,
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u64 size)
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2015-10-02 03:13:58 +08:00
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{
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}
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static inline int iommu_get_dma_cookie(struct iommu_domain *domain)
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{
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return -ENODEV;
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}
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2017-01-20 04:57:46 +08:00
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static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
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{
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return -ENODEV;
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}
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2015-10-02 03:13:58 +08:00
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static inline void iommu_put_dma_cookie(struct iommu_domain *domain)
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{
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}
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2019-05-01 21:58:19 +08:00
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static inline int iommu_dma_prepare_msi(struct msi_desc *desc,
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phys_addr_t msi_addr)
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{
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return 0;
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}
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static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg)
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{
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}
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2017-03-17 01:00:19 +08:00
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static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
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{
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}
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2020-11-24 16:20:52 +08:00
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static inline void iommu_dma_free_cpu_cached_iovas(unsigned int cpu,
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struct iommu_domain *domain)
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{
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}
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2015-10-02 03:13:58 +08:00
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#endif /* CONFIG_IOMMU_DMA */
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#endif /* __DMA_IOMMU_H */
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