2021-08-03 01:30:05 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. */
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/idr.h>
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#include <linux/pci.h>
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#include <cxlmem.h>
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#include "core.h"
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2021-09-09 13:12:32 +08:00
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static DECLARE_RWSEM(cxl_memdev_rwsem);
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2021-08-03 01:30:05 +08:00
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/*
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* An entire PCI topology full of devices should be enough for any
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* config
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*/
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#define CXL_MEM_MAX_DEVS 65536
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static int cxl_mem_major;
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static DEFINE_IDA(cxl_memdev_ida);
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static void cxl_memdev_release(struct device *dev)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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ida_free(&cxl_memdev_ida, cxlmd->id);
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kfree(cxlmd);
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}
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static char *cxl_memdev_devnode(struct device *dev, umode_t *mode, kuid_t *uid,
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kgid_t *gid)
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{
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return kasprintf(GFP_KERNEL, "cxl/%s", dev_name(dev));
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}
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static ssize_t firmware_version_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-08-03 01:30:05 +08:00
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2021-11-03 04:29:01 +08:00
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return sysfs_emit(buf, "%.16s\n", cxlds->firmware_version);
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2021-08-03 01:30:05 +08:00
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}
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static DEVICE_ATTR_RO(firmware_version);
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static ssize_t payload_max_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-08-03 01:30:05 +08:00
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2021-11-03 04:29:01 +08:00
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return sysfs_emit(buf, "%zu\n", cxlds->payload_size);
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2021-08-03 01:30:05 +08:00
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}
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static DEVICE_ATTR_RO(payload_max);
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static ssize_t label_storage_size_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-08-03 01:30:05 +08:00
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2021-11-03 04:29:01 +08:00
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return sysfs_emit(buf, "%zu\n", cxlds->lsa_size);
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2021-08-03 01:30:05 +08:00
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}
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static DEVICE_ATTR_RO(label_storage_size);
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static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2022-05-22 06:35:29 +08:00
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unsigned long long len = resource_size(&cxlds->ram_res);
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2021-08-03 01:30:05 +08:00
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return sysfs_emit(buf, "%#llx\n", len);
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}
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static struct device_attribute dev_attr_ram_size =
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__ATTR(size, 0444, ram_size_show, NULL);
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static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2022-05-22 06:35:29 +08:00
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unsigned long long len = resource_size(&cxlds->pmem_res);
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2021-08-03 01:30:05 +08:00
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return sysfs_emit(buf, "%#llx\n", len);
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}
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static struct device_attribute dev_attr_pmem_size =
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__ATTR(size, 0444, pmem_size_show, NULL);
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2022-02-01 05:56:11 +08:00
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static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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return sysfs_emit(buf, "%#llx\n", cxlds->serial);
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}
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static DEVICE_ATTR_RO(serial);
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2022-01-24 08:31:24 +08:00
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static ssize_t numa_node_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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return sprintf(buf, "%d\n", dev_to_node(dev));
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}
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static DEVICE_ATTR_RO(numa_node);
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2021-08-03 01:30:05 +08:00
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static struct attribute *cxl_memdev_attributes[] = {
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2022-02-01 05:56:11 +08:00
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&dev_attr_serial.attr,
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2021-08-03 01:30:05 +08:00
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&dev_attr_firmware_version.attr,
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&dev_attr_payload_max.attr,
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&dev_attr_label_storage_size.attr,
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2022-01-24 08:31:24 +08:00
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&dev_attr_numa_node.attr,
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2021-08-03 01:30:05 +08:00
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NULL,
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};
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static struct attribute *cxl_memdev_pmem_attributes[] = {
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&dev_attr_pmem_size.attr,
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NULL,
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};
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static struct attribute *cxl_memdev_ram_attributes[] = {
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&dev_attr_ram_size.attr,
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NULL,
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};
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2022-01-24 08:31:24 +08:00
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static umode_t cxl_memdev_visible(struct kobject *kobj, struct attribute *a,
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int n)
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{
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if (!IS_ENABLED(CONFIG_NUMA) && a == &dev_attr_numa_node.attr)
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return 0;
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return a->mode;
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}
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2021-08-03 01:30:05 +08:00
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static struct attribute_group cxl_memdev_attribute_group = {
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.attrs = cxl_memdev_attributes,
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2022-01-24 08:31:24 +08:00
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.is_visible = cxl_memdev_visible,
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2021-08-03 01:30:05 +08:00
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};
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static struct attribute_group cxl_memdev_ram_attribute_group = {
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.name = "ram",
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.attrs = cxl_memdev_ram_attributes,
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};
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static struct attribute_group cxl_memdev_pmem_attribute_group = {
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.name = "pmem",
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.attrs = cxl_memdev_pmem_attributes,
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};
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static const struct attribute_group *cxl_memdev_attribute_groups[] = {
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&cxl_memdev_attribute_group,
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&cxl_memdev_ram_attribute_group,
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&cxl_memdev_pmem_attribute_group,
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NULL,
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};
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static const struct device_type cxl_memdev_type = {
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.name = "cxl_memdev",
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.release = cxl_memdev_release,
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.devnode = cxl_memdev_devnode,
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.groups = cxl_memdev_attribute_groups,
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};
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2022-02-04 23:18:31 +08:00
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bool is_cxl_memdev(struct device *dev)
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{
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return dev->type == &cxl_memdev_type;
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}
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EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL);
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2021-09-15 03:03:04 +08:00
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/**
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* set_exclusive_cxl_commands() - atomically disable user cxl commands
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2021-11-03 04:29:01 +08:00
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* @cxlds: The device state to operate on
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2021-09-15 03:03:04 +08:00
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* @cmds: bitmap of commands to mark exclusive
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*
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* Grab the cxl_memdev_rwsem in write mode to flush in-flight
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* invocations of the ioctl path and then disable future execution of
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* commands with the command ids set in @cmds.
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*/
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2021-11-03 04:29:01 +08:00
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void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds)
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2021-09-15 03:03:04 +08:00
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{
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down_write(&cxl_memdev_rwsem);
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2021-11-03 04:29:01 +08:00
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bitmap_or(cxlds->exclusive_cmds, cxlds->exclusive_cmds, cmds,
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2021-09-15 03:03:04 +08:00
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CXL_MEM_COMMAND_ID_MAX);
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up_write(&cxl_memdev_rwsem);
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}
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2021-11-13 08:32:58 +08:00
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EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, CXL);
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2021-09-15 03:03:04 +08:00
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/**
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* clear_exclusive_cxl_commands() - atomically enable user cxl commands
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2021-11-03 04:29:01 +08:00
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* @cxlds: The device state to modify
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2021-09-15 03:03:04 +08:00
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* @cmds: bitmap of commands to mark available for userspace
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*/
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2021-11-03 04:29:01 +08:00
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void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds)
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2021-09-15 03:03:04 +08:00
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{
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down_write(&cxl_memdev_rwsem);
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2021-11-03 04:29:01 +08:00
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bitmap_andnot(cxlds->exclusive_cmds, cxlds->exclusive_cmds, cmds,
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2021-09-15 03:03:04 +08:00
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CXL_MEM_COMMAND_ID_MAX);
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up_write(&cxl_memdev_rwsem);
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}
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2021-11-13 08:32:58 +08:00
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EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, CXL);
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2021-09-15 03:03:04 +08:00
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2021-09-09 13:12:32 +08:00
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static void cxl_memdev_shutdown(struct device *dev)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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down_write(&cxl_memdev_rwsem);
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2021-11-03 04:29:01 +08:00
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cxlmd->cxlds = NULL;
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2021-09-09 13:12:32 +08:00
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up_write(&cxl_memdev_rwsem);
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}
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2021-08-03 01:30:05 +08:00
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static void cxl_memdev_unregister(void *_cxlmd)
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{
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struct cxl_memdev *cxlmd = _cxlmd;
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struct device *dev = &cxlmd->dev;
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2021-09-09 13:12:32 +08:00
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cxl_memdev_shutdown(dev);
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2021-08-03 01:30:05 +08:00
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cdev_device_del(&cxlmd->cdev, dev);
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put_device(dev);
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}
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2022-02-04 23:18:31 +08:00
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static void detach_memdev(struct work_struct *work)
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{
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struct cxl_memdev *cxlmd;
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cxlmd = container_of(work, typeof(*cxlmd), detach_work);
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device_release_driver(&cxlmd->dev);
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put_device(&cxlmd->dev);
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}
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2022-04-21 23:33:13 +08:00
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static struct lock_class_key cxl_memdev_key;
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2021-11-03 04:29:01 +08:00
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static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
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2021-08-03 01:30:05 +08:00
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const struct file_operations *fops)
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{
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struct cxl_memdev *cxlmd;
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struct device *dev;
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struct cdev *cdev;
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int rc;
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cxlmd = kzalloc(sizeof(*cxlmd), GFP_KERNEL);
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if (!cxlmd)
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return ERR_PTR(-ENOMEM);
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rc = ida_alloc_range(&cxl_memdev_ida, 0, CXL_MEM_MAX_DEVS, GFP_KERNEL);
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if (rc < 0)
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goto err;
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cxlmd->id = rc;
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dev = &cxlmd->dev;
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device_initialize(dev);
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2022-04-21 23:33:13 +08:00
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lockdep_set_class(&dev->mutex, &cxl_memdev_key);
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2021-11-03 04:29:01 +08:00
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dev->parent = cxlds->dev;
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2021-08-03 01:30:05 +08:00
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dev->bus = &cxl_bus_type;
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dev->devt = MKDEV(cxl_mem_major, cxlmd->id);
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dev->type = &cxl_memdev_type;
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device_set_pm_not_required(dev);
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2022-02-04 23:18:31 +08:00
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INIT_WORK(&cxlmd->detach_work, detach_memdev);
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2021-08-03 01:30:05 +08:00
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cdev = &cxlmd->cdev;
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cdev_init(cdev, fops);
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return cxlmd;
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err:
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kfree(cxlmd);
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return ERR_PTR(rc);
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}
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2021-09-09 13:12:32 +08:00
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static long __cxl_memdev_ioctl(struct cxl_memdev *cxlmd, unsigned int cmd,
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unsigned long arg)
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{
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switch (cmd) {
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case CXL_MEM_QUERY_COMMANDS:
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return cxl_query_cmd(cxlmd, (void __user *)arg);
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case CXL_MEM_SEND_COMMAND:
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return cxl_send_cmd(cxlmd, (void __user *)arg);
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default:
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return -ENOTTY;
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}
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}
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static long cxl_memdev_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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struct cxl_memdev *cxlmd = file->private_data;
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int rc = -ENXIO;
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down_read(&cxl_memdev_rwsem);
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2021-11-03 04:29:01 +08:00
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if (cxlmd->cxlds)
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2021-09-09 13:12:32 +08:00
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rc = __cxl_memdev_ioctl(cxlmd, cmd, arg);
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up_read(&cxl_memdev_rwsem);
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return rc;
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}
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static int cxl_memdev_open(struct inode *inode, struct file *file)
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{
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struct cxl_memdev *cxlmd =
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container_of(inode->i_cdev, typeof(*cxlmd), cdev);
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get_device(&cxlmd->dev);
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file->private_data = cxlmd;
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return 0;
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}
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static int cxl_memdev_release_file(struct inode *inode, struct file *file)
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{
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struct cxl_memdev *cxlmd =
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container_of(inode->i_cdev, typeof(*cxlmd), cdev);
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|
|
put_device(&cxlmd->dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations cxl_memdev_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.unlocked_ioctl = cxl_memdev_ioctl,
|
|
|
|
.open = cxl_memdev_open,
|
|
|
|
.release = cxl_memdev_release_file,
|
|
|
|
.compat_ioctl = compat_ptr_ioctl,
|
|
|
|
.llseek = noop_llseek,
|
|
|
|
};
|
|
|
|
|
2021-11-03 04:29:01 +08:00
|
|
|
struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds)
|
2021-08-03 01:30:05 +08:00
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd;
|
|
|
|
struct device *dev;
|
|
|
|
struct cdev *cdev;
|
|
|
|
int rc;
|
|
|
|
|
2021-11-03 04:29:01 +08:00
|
|
|
cxlmd = cxl_memdev_alloc(cxlds, &cxl_memdev_fops);
|
2021-08-03 01:30:05 +08:00
|
|
|
if (IS_ERR(cxlmd))
|
|
|
|
return cxlmd;
|
|
|
|
|
|
|
|
dev = &cxlmd->dev;
|
|
|
|
rc = dev_set_name(dev, "mem%d", cxlmd->id);
|
|
|
|
if (rc)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Activate ioctl operations, no cxl_memdev_rwsem manipulation
|
|
|
|
* needed as this is ordered with cdev_add() publishing the device.
|
|
|
|
*/
|
2021-11-03 04:29:01 +08:00
|
|
|
cxlmd->cxlds = cxlds;
|
2021-08-03 01:30:05 +08:00
|
|
|
|
|
|
|
cdev = &cxlmd->cdev;
|
|
|
|
rc = cdev_device_add(cdev, dev);
|
|
|
|
if (rc)
|
|
|
|
goto err;
|
|
|
|
|
2021-11-03 04:29:01 +08:00
|
|
|
rc = devm_add_action_or_reset(cxlds->dev, cxl_memdev_unregister, cxlmd);
|
2021-08-03 01:30:05 +08:00
|
|
|
if (rc)
|
|
|
|
return ERR_PTR(rc);
|
|
|
|
return cxlmd;
|
|
|
|
|
|
|
|
err:
|
|
|
|
/*
|
|
|
|
* The cdev was briefly live, shutdown any ioctl operations that
|
|
|
|
* saw that state.
|
|
|
|
*/
|
2021-09-09 13:12:32 +08:00
|
|
|
cxl_memdev_shutdown(dev);
|
2021-08-03 01:30:05 +08:00
|
|
|
put_device(dev);
|
|
|
|
return ERR_PTR(rc);
|
|
|
|
}
|
2021-11-13 08:32:58 +08:00
|
|
|
EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL);
|
2021-08-03 01:30:05 +08:00
|
|
|
|
|
|
|
__init int cxl_memdev_init(void)
|
|
|
|
{
|
|
|
|
dev_t devt;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = alloc_chrdev_region(&devt, 0, CXL_MEM_MAX_DEVS, "cxl");
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
cxl_mem_major = MAJOR(devt);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cxl_memdev_exit(void)
|
|
|
|
{
|
|
|
|
unregister_chrdev_region(MKDEV(cxl_mem_major, 0), CXL_MEM_MAX_DEVS);
|
|
|
|
}
|