2018-05-17 07:49:58 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2015-10-07 23:36:28 +08:00
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/*
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* FPGA Manager Core
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*
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* Copyright (C) 2013-2015 Altera Corporation
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2017-11-16 04:20:12 +08:00
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* Copyright (C) 2017 Intel Corporation
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2015-10-07 23:36:28 +08:00
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*
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* With code from the mailing list:
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* Copyright (C) 2013 Xilinx, Inc.
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*/
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#include <linux/firmware.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/idr.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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2017-02-02 03:48:44 +08:00
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#include <linux/scatterlist.h>
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#include <linux/highmem.h>
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2015-10-07 23:36:28 +08:00
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static DEFINE_IDA(fpga_mgr_ida);
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static struct class *fpga_mgr_class;
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2020-11-16 03:51:18 +08:00
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struct fpga_mgr_devres {
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struct fpga_manager *mgr;
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};
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2021-06-26 03:51:47 +08:00
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static inline void fpga_mgr_fpga_remove(struct fpga_manager *mgr)
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{
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if (mgr->mops->fpga_remove)
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mgr->mops->fpga_remove(mgr);
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}
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2021-06-26 03:51:46 +08:00
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static inline enum fpga_mgr_states fpga_mgr_state(struct fpga_manager *mgr)
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{
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if (mgr->mops->state)
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return mgr->mops->state(mgr);
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return FPGA_MGR_STATE_UNKNOWN;
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}
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2021-06-26 03:51:45 +08:00
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static inline u64 fpga_mgr_status(struct fpga_manager *mgr)
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{
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if (mgr->mops->status)
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return mgr->mops->status(mgr);
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return 0;
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}
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2021-06-26 03:51:44 +08:00
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static inline int fpga_mgr_write(struct fpga_manager *mgr, const char *buf, size_t count)
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{
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if (mgr->mops->write)
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return mgr->mops->write(mgr, buf, count);
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return -EOPNOTSUPP;
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}
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2021-06-26 03:51:43 +08:00
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/*
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* After all the FPGA image has been written, do the device specific steps to
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* finish and set the FPGA into operating mode.
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*/
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static inline int fpga_mgr_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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int ret = 0;
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mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
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if (mgr->mops->write_complete)
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ret = mgr->mops->write_complete(mgr, info);
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if (ret) {
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dev_err(&mgr->dev, "Error after writing image data to FPGA\n");
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mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
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return ret;
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}
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mgr->state = FPGA_MGR_STATE_OPERATING;
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return 0;
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}
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2021-06-26 03:51:42 +08:00
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static inline int fpga_mgr_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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if (mgr->mops->write_init)
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return mgr->mops->write_init(mgr, info, buf, count);
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return 0;
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}
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2021-06-26 03:51:48 +08:00
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static inline int fpga_mgr_write_sg(struct fpga_manager *mgr,
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struct sg_table *sgt)
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{
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if (mgr->mops->write_sg)
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return mgr->mops->write_sg(mgr, sgt);
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return -EOPNOTSUPP;
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}
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2018-05-17 07:49:59 +08:00
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/**
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2021-06-09 05:23:46 +08:00
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* fpga_image_info_alloc - Allocate an FPGA image info struct
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2018-05-17 07:49:59 +08:00
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* @dev: owning device
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*
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* Return: struct fpga_image_info or NULL
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*/
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2017-11-16 04:20:12 +08:00
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struct fpga_image_info *fpga_image_info_alloc(struct device *dev)
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{
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struct fpga_image_info *info;
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get_device(dev);
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info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
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if (!info) {
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put_device(dev);
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return NULL;
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}
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info->dev = dev;
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return info;
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}
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EXPORT_SYMBOL_GPL(fpga_image_info_alloc);
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2018-05-17 07:49:59 +08:00
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/**
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2021-06-09 05:23:46 +08:00
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* fpga_image_info_free - Free an FPGA image info struct
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2018-05-17 07:49:59 +08:00
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* @info: FPGA image info struct to free
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*/
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2017-11-16 04:20:12 +08:00
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void fpga_image_info_free(struct fpga_image_info *info)
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{
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struct device *dev;
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if (!info)
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return;
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dev = info->dev;
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if (info->firmware_name)
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devm_kfree(dev, info->firmware_name);
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devm_kfree(dev, info);
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put_device(dev);
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}
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EXPORT_SYMBOL_GPL(fpga_image_info_free);
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2017-02-02 03:48:44 +08:00
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/*
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* Call the low level driver's write_init function. This will do the
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* device-specific things to get the FPGA into the state where it is ready to
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* receive an FPGA image. The low level driver only gets to see the first
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* initial_header_size bytes in the buffer.
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*/
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static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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int ret;
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mgr->state = FPGA_MGR_STATE_WRITE_INIT;
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2022-04-24 01:02:32 +08:00
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if (!mgr->mops->initial_header_size) {
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2021-06-26 03:51:42 +08:00
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ret = fpga_mgr_write_init(mgr, info, NULL, 0);
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2022-04-24 01:02:32 +08:00
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} else {
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count = min(mgr->mops->initial_header_size, count);
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ret = fpga_mgr_write_init(mgr, info, buf, count);
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}
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2017-02-02 03:48:44 +08:00
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if (ret) {
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dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
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mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
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return ret;
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}
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return 0;
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}
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static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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struct sg_table *sgt)
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{
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struct sg_mapping_iter miter;
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size_t len;
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char *buf;
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int ret;
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if (!mgr->mops->initial_header_size)
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return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
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/*
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* First try to use miter to map the first fragment to access the
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* header, this is the typical path.
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*/
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sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
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if (sg_miter_next(&miter) &&
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miter.length >= mgr->mops->initial_header_size) {
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ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
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miter.length);
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sg_miter_stop(&miter);
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return ret;
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}
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sg_miter_stop(&miter);
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/* Otherwise copy the fragments into temporary memory. */
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buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
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mgr->mops->initial_header_size);
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ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
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kfree(buf);
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return ret;
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}
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2015-10-07 23:36:28 +08:00
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/**
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2017-02-02 03:48:44 +08:00
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* fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list
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2015-10-07 23:36:28 +08:00
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* @mgr: fpga manager
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2016-11-02 03:14:26 +08:00
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* @info: fpga image specific information
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2017-02-02 03:48:44 +08:00
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* @sgt: scatterlist table
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2015-10-07 23:36:28 +08:00
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*
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* Step the low level fpga manager through the device-specific steps of getting
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* an FPGA ready to be configured, writing the image to it, then doing whatever
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2015-10-23 01:38:38 +08:00
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* post-configuration steps necessary. This code assumes the caller got the
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2016-11-02 03:14:23 +08:00
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* mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is
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* not an error code.
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2015-10-07 23:36:28 +08:00
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*
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2017-02-02 03:48:44 +08:00
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* This is the preferred entry point for FPGA programming, it does not require
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* any contiguous kernel memory.
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*
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2015-10-07 23:36:28 +08:00
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* Return: 0 on success, negative error code otherwise.
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*/
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2017-11-16 04:20:12 +08:00
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static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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struct sg_table *sgt)
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2015-10-07 23:36:28 +08:00
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{
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int ret;
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2017-02-02 03:48:44 +08:00
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ret = fpga_mgr_write_init_sg(mgr, info, sgt);
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if (ret)
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return ret;
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/* Write the FPGA image to the FPGA. */
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mgr->state = FPGA_MGR_STATE_WRITE;
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if (mgr->mops->write_sg) {
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2021-06-26 03:51:48 +08:00
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ret = fpga_mgr_write_sg(mgr, sgt);
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2017-02-02 03:48:44 +08:00
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} else {
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struct sg_mapping_iter miter;
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sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
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while (sg_miter_next(&miter)) {
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2021-06-26 03:51:44 +08:00
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ret = fpga_mgr_write(mgr, miter.addr, miter.length);
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2017-02-02 03:48:44 +08:00
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if (ret)
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break;
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}
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sg_miter_stop(&miter);
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}
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2015-10-07 23:36:28 +08:00
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if (ret) {
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2017-02-02 03:48:44 +08:00
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dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
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mgr->state = FPGA_MGR_STATE_WRITE_ERR;
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2015-10-07 23:36:28 +08:00
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return ret;
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}
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2017-02-02 03:48:44 +08:00
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return fpga_mgr_write_complete(mgr, info);
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}
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static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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int ret;
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ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
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if (ret)
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return ret;
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2015-10-07 23:36:28 +08:00
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/*
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* Write the FPGA image to the FPGA.
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*/
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mgr->state = FPGA_MGR_STATE_WRITE;
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2021-06-26 03:51:44 +08:00
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ret = fpga_mgr_write(mgr, buf, count);
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2015-10-07 23:36:28 +08:00
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if (ret) {
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2017-02-02 03:48:44 +08:00
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dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
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2015-10-07 23:36:28 +08:00
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mgr->state = FPGA_MGR_STATE_WRITE_ERR;
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return ret;
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}
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2017-02-02 03:48:44 +08:00
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return fpga_mgr_write_complete(mgr, info);
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}
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/**
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* fpga_mgr_buf_load - load fpga from image in buffer
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* @mgr: fpga manager
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2018-05-17 07:49:59 +08:00
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* @info: fpga image info
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2017-02-02 03:48:44 +08:00
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* @buf: buffer contain fpga image
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* @count: byte count of buf
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*
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* Step the low level fpga manager through the device-specific steps of getting
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* an FPGA ready to be configured, writing the image to it, then doing whatever
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* post-configuration steps necessary. This code assumes the caller got the
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* mgr pointer from of_fpga_mgr_get() and checked that it is not an error code.
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*
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* Return: 0 on success, negative error code otherwise.
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*/
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2017-11-16 04:20:12 +08:00
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static int fpga_mgr_buf_load(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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2017-02-02 03:48:44 +08:00
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{
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struct page **pages;
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struct sg_table sgt;
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const void *p;
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int nr_pages;
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int index;
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int rc;
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2015-10-07 23:36:28 +08:00
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/*
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2017-02-02 03:48:44 +08:00
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* This is just a fast path if the caller has already created a
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* contiguous kernel buffer and the driver doesn't require SG, non-SG
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* drivers will still work on the slow path.
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2015-10-07 23:36:28 +08:00
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*/
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2017-02-02 03:48:44 +08:00
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if (mgr->mops->write)
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return fpga_mgr_buf_load_mapped(mgr, info, buf, count);
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/*
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* Convert the linear kernel pointer into a sg_table of pages for use
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* by the driver.
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*/
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nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) -
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(unsigned long)buf / PAGE_SIZE;
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pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
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if (!pages)
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return -ENOMEM;
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p = buf - offset_in_page(buf);
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for (index = 0; index < nr_pages; index++) {
|
|
|
|
if (is_vmalloc_addr(p))
|
|
|
|
pages[index] = vmalloc_to_page(p);
|
|
|
|
else
|
|
|
|
pages[index] = kmap_to_page((void *)p);
|
|
|
|
if (!pages[index]) {
|
|
|
|
kfree(pages);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
p += PAGE_SIZE;
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
|
|
|
|
2017-02-02 03:48:44 +08:00
|
|
|
/*
|
|
|
|
* The temporary pages list is used to code share the merging algorithm
|
|
|
|
* in sg_alloc_table_from_pages
|
|
|
|
*/
|
|
|
|
rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf),
|
|
|
|
count, GFP_KERNEL);
|
|
|
|
kfree(pages);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = fpga_mgr_buf_load_sg(mgr, info, &sgt);
|
|
|
|
sg_free_table(&sgt);
|
|
|
|
|
|
|
|
return rc;
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* fpga_mgr_firmware_load - request firmware and load to fpga
|
|
|
|
* @mgr: fpga manager
|
2016-11-02 03:14:26 +08:00
|
|
|
* @info: fpga image specific information
|
2015-10-07 23:36:28 +08:00
|
|
|
* @image_name: name of image file on the firmware search path
|
|
|
|
*
|
|
|
|
* Request an FPGA image using the firmware class, then write out to the FPGA.
|
|
|
|
* Update the state before each step to provide info on what step failed if
|
2015-10-23 01:38:38 +08:00
|
|
|
* there is a failure. This code assumes the caller got the mgr pointer
|
2016-11-02 03:14:23 +08:00
|
|
|
* from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error
|
|
|
|
* code.
|
2015-10-07 23:36:28 +08:00
|
|
|
*
|
|
|
|
* Return: 0 on success, negative error code otherwise.
|
|
|
|
*/
|
2017-11-16 04:20:12 +08:00
|
|
|
static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
|
|
|
|
struct fpga_image_info *info,
|
|
|
|
const char *image_name)
|
2015-10-07 23:36:28 +08:00
|
|
|
{
|
|
|
|
struct device *dev = &mgr->dev;
|
|
|
|
const struct firmware *fw;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dev_info(dev, "writing %s to %s\n", image_name, mgr->name);
|
|
|
|
|
|
|
|
mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ;
|
|
|
|
|
|
|
|
ret = request_firmware(&fw, image_name, dev);
|
|
|
|
if (ret) {
|
|
|
|
mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR;
|
|
|
|
dev_err(dev, "Error requesting firmware %s\n", image_name);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-11-02 03:14:26 +08:00
|
|
|
ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
|
2015-10-07 23:36:28 +08:00
|
|
|
|
|
|
|
release_firmware(fw);
|
|
|
|
|
2015-11-18 17:48:16 +08:00
|
|
|
return ret;
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
2017-11-16 04:20:12 +08:00
|
|
|
|
2018-05-17 07:49:59 +08:00
|
|
|
/**
|
|
|
|
* fpga_mgr_load - load FPGA from scatter/gather table, buffer, or firmware
|
|
|
|
* @mgr: fpga manager
|
|
|
|
* @info: fpga image information.
|
|
|
|
*
|
|
|
|
* Load the FPGA from an image which is indicated in @info. If successful, the
|
|
|
|
* FPGA ends up in operating mode.
|
|
|
|
*
|
|
|
|
* Return: 0 on success, negative error code otherwise.
|
|
|
|
*/
|
2017-11-16 04:20:12 +08:00
|
|
|
int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
|
|
|
|
{
|
|
|
|
if (info->sgt)
|
|
|
|
return fpga_mgr_buf_load_sg(mgr, info, info->sgt);
|
|
|
|
if (info->buf && info->count)
|
|
|
|
return fpga_mgr_buf_load(mgr, info, info->buf, info->count);
|
|
|
|
if (info->firmware_name)
|
|
|
|
return fpga_mgr_firmware_load(mgr, info, info->firmware_name);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_load);
|
2015-10-07 23:36:28 +08:00
|
|
|
|
|
|
|
static const char * const state_str[] = {
|
|
|
|
[FPGA_MGR_STATE_UNKNOWN] = "unknown",
|
|
|
|
[FPGA_MGR_STATE_POWER_OFF] = "power off",
|
|
|
|
[FPGA_MGR_STATE_POWER_UP] = "power up",
|
|
|
|
[FPGA_MGR_STATE_RESET] = "reset",
|
|
|
|
|
|
|
|
/* requesting FPGA image from firmware */
|
|
|
|
[FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request",
|
|
|
|
[FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error",
|
|
|
|
|
|
|
|
/* Preparing FPGA to receive image */
|
|
|
|
[FPGA_MGR_STATE_WRITE_INIT] = "write init",
|
|
|
|
[FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error",
|
|
|
|
|
|
|
|
/* Writing image to FPGA */
|
|
|
|
[FPGA_MGR_STATE_WRITE] = "write",
|
|
|
|
[FPGA_MGR_STATE_WRITE_ERR] = "write error",
|
|
|
|
|
|
|
|
/* Finishing configuration after image has been written */
|
|
|
|
[FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete",
|
|
|
|
[FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error",
|
|
|
|
|
|
|
|
/* FPGA reports to be in normal operating mode */
|
|
|
|
[FPGA_MGR_STATE_OPERATING] = "operating",
|
|
|
|
};
|
|
|
|
|
|
|
|
static ssize_t name_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct fpga_manager *mgr = to_fpga_manager(dev);
|
|
|
|
|
|
|
|
return sprintf(buf, "%s\n", mgr->name);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t state_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct fpga_manager *mgr = to_fpga_manager(dev);
|
|
|
|
|
|
|
|
return sprintf(buf, "%s\n", state_str[mgr->state]);
|
|
|
|
}
|
|
|
|
|
2018-06-30 08:53:10 +08:00
|
|
|
static ssize_t status_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct fpga_manager *mgr = to_fpga_manager(dev);
|
|
|
|
u64 status;
|
|
|
|
int len = 0;
|
|
|
|
|
2021-06-26 03:51:45 +08:00
|
|
|
status = fpga_mgr_status(mgr);
|
2018-06-30 08:53:10 +08:00
|
|
|
|
|
|
|
if (status & FPGA_MGR_STATUS_OPERATION_ERR)
|
|
|
|
len += sprintf(buf + len, "reconfig operation error\n");
|
|
|
|
if (status & FPGA_MGR_STATUS_CRC_ERR)
|
|
|
|
len += sprintf(buf + len, "reconfig CRC error\n");
|
|
|
|
if (status & FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR)
|
|
|
|
len += sprintf(buf + len, "reconfig incompatible image\n");
|
|
|
|
if (status & FPGA_MGR_STATUS_IP_PROTOCOL_ERR)
|
|
|
|
len += sprintf(buf + len, "reconfig IP protocol error\n");
|
|
|
|
if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR)
|
|
|
|
len += sprintf(buf + len, "reconfig fifo overflow error\n");
|
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
2015-10-07 23:36:28 +08:00
|
|
|
static DEVICE_ATTR_RO(name);
|
|
|
|
static DEVICE_ATTR_RO(state);
|
2018-06-30 08:53:10 +08:00
|
|
|
static DEVICE_ATTR_RO(status);
|
2015-10-07 23:36:28 +08:00
|
|
|
|
|
|
|
static struct attribute *fpga_mgr_attrs[] = {
|
|
|
|
&dev_attr_name.attr,
|
|
|
|
&dev_attr_state.attr,
|
2018-06-30 08:53:10 +08:00
|
|
|
&dev_attr_status.attr,
|
2015-10-07 23:36:28 +08:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
ATTRIBUTE_GROUPS(fpga_mgr);
|
|
|
|
|
2017-02-27 23:18:59 +08:00
|
|
|
static struct fpga_manager *__fpga_mgr_get(struct device *dev)
|
2015-10-07 23:36:28 +08:00
|
|
|
{
|
|
|
|
struct fpga_manager *mgr;
|
|
|
|
|
|
|
|
mgr = to_fpga_manager(dev);
|
|
|
|
|
2015-10-23 01:38:37 +08:00
|
|
|
if (!try_module_get(dev->parent->driver->owner))
|
2017-11-16 04:20:13 +08:00
|
|
|
goto err_dev;
|
2015-10-23 01:38:37 +08:00
|
|
|
|
2015-10-07 23:36:28 +08:00
|
|
|
return mgr;
|
2015-10-23 01:38:37 +08:00
|
|
|
|
|
|
|
err_dev:
|
|
|
|
put_device(dev);
|
2017-11-16 04:20:13 +08:00
|
|
|
return ERR_PTR(-ENODEV);
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
2016-11-02 03:14:23 +08:00
|
|
|
|
|
|
|
static int fpga_mgr_dev_match(struct device *dev, const void *data)
|
|
|
|
{
|
|
|
|
return dev->parent == data;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-06-09 05:23:46 +08:00
|
|
|
* fpga_mgr_get - Given a device, get a reference to an fpga mgr.
|
2016-11-02 03:14:23 +08:00
|
|
|
* @dev: parent device that fpga mgr was registered with
|
|
|
|
*
|
|
|
|
* Return: fpga manager struct or IS_ERR() condition containing error code.
|
|
|
|
*/
|
|
|
|
struct fpga_manager *fpga_mgr_get(struct device *dev)
|
|
|
|
{
|
|
|
|
struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
|
|
|
|
fpga_mgr_dev_match);
|
|
|
|
if (!mgr_dev)
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
|
|
|
return __fpga_mgr_get(mgr_dev);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_get);
|
|
|
|
|
|
|
|
/**
|
2021-06-09 05:23:46 +08:00
|
|
|
* of_fpga_mgr_get - Given a device node, get a reference to an fpga mgr.
|
2016-11-02 03:14:23 +08:00
|
|
|
*
|
2018-05-17 07:49:59 +08:00
|
|
|
* @node: device node
|
2016-11-02 03:14:23 +08:00
|
|
|
*
|
|
|
|
* Return: fpga manager struct or IS_ERR() condition containing error code.
|
|
|
|
*/
|
|
|
|
struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
|
|
|
|
{
|
|
|
|
struct device *dev;
|
|
|
|
|
2019-07-24 06:18:33 +08:00
|
|
|
dev = class_find_device_by_of_node(fpga_mgr_class, node);
|
2016-11-02 03:14:23 +08:00
|
|
|
if (!dev)
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
|
|
|
return __fpga_mgr_get(dev);
|
|
|
|
}
|
2015-10-07 23:36:28 +08:00
|
|
|
EXPORT_SYMBOL_GPL(of_fpga_mgr_get);
|
|
|
|
|
|
|
|
/**
|
2021-06-09 05:23:46 +08:00
|
|
|
* fpga_mgr_put - release a reference to an fpga manager
|
2015-10-07 23:36:28 +08:00
|
|
|
* @mgr: fpga manager structure
|
|
|
|
*/
|
|
|
|
void fpga_mgr_put(struct fpga_manager *mgr)
|
|
|
|
{
|
2015-10-23 01:38:37 +08:00
|
|
|
module_put(mgr->dev.parent->driver->owner);
|
|
|
|
put_device(&mgr->dev);
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_put);
|
|
|
|
|
2017-11-16 04:20:13 +08:00
|
|
|
/**
|
|
|
|
* fpga_mgr_lock - Lock FPGA manager for exclusive use
|
|
|
|
* @mgr: fpga manager
|
|
|
|
*
|
|
|
|
* Given a pointer to FPGA Manager (from fpga_mgr_get() or
|
2018-05-17 07:49:59 +08:00
|
|
|
* of_fpga_mgr_put()) attempt to get the mutex. The user should call
|
|
|
|
* fpga_mgr_lock() and verify that it returns 0 before attempting to
|
|
|
|
* program the FPGA. Likewise, the user should call fpga_mgr_unlock
|
|
|
|
* when done programming the FPGA.
|
2017-11-16 04:20:13 +08:00
|
|
|
*
|
|
|
|
* Return: 0 for success or -EBUSY
|
|
|
|
*/
|
|
|
|
int fpga_mgr_lock(struct fpga_manager *mgr)
|
|
|
|
{
|
|
|
|
if (!mutex_trylock(&mgr->ref_mutex)) {
|
|
|
|
dev_err(&mgr->dev, "FPGA manager is in use.\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_lock);
|
|
|
|
|
|
|
|
/**
|
2018-05-17 07:49:59 +08:00
|
|
|
* fpga_mgr_unlock - Unlock FPGA manager after done programming
|
2017-11-16 04:20:13 +08:00
|
|
|
* @mgr: fpga manager
|
|
|
|
*/
|
|
|
|
void fpga_mgr_unlock(struct fpga_manager *mgr)
|
|
|
|
{
|
|
|
|
mutex_unlock(&mgr->ref_mutex);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_unlock);
|
|
|
|
|
2015-10-07 23:36:28 +08:00
|
|
|
/**
|
2021-11-19 09:55:51 +08:00
|
|
|
* fpga_mgr_register_full - create and register an FPGA Manager device
|
2021-06-15 01:09:04 +08:00
|
|
|
* @parent: fpga manager device from pdev
|
2021-11-19 09:55:51 +08:00
|
|
|
* @info: parameters for fpga manager
|
2015-10-07 23:36:28 +08:00
|
|
|
*
|
2021-11-19 09:55:51 +08:00
|
|
|
* The caller of this function is responsible for calling fpga_mgr_unregister().
|
|
|
|
* Using devm_fpga_mgr_register_full() instead is recommended.
|
2018-10-16 06:20:01 +08:00
|
|
|
*
|
2021-11-19 09:55:51 +08:00
|
|
|
* Return: pointer to struct fpga_manager pointer or ERR_PTR()
|
2015-10-07 23:36:28 +08:00
|
|
|
*/
|
2021-11-19 09:55:51 +08:00
|
|
|
struct fpga_manager *
|
|
|
|
fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info)
|
2015-10-07 23:36:28 +08:00
|
|
|
{
|
2021-11-19 09:55:51 +08:00
|
|
|
const struct fpga_manager_ops *mops = info->mops;
|
2015-10-07 23:36:28 +08:00
|
|
|
struct fpga_manager *mgr;
|
|
|
|
int id, ret;
|
|
|
|
|
2021-06-26 03:51:46 +08:00
|
|
|
if (!mops) {
|
2021-06-15 01:09:04 +08:00
|
|
|
dev_err(parent, "Attempt to register without fpga_manager_ops\n");
|
2021-11-19 09:55:51 +08:00
|
|
|
return ERR_PTR(-EINVAL);
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
if (!info->name || !strlen(info->name)) {
|
2021-06-15 01:09:04 +08:00
|
|
|
dev_err(parent, "Attempt to register with no name!\n");
|
2021-11-19 09:55:51 +08:00
|
|
|
return ERR_PTR(-EINVAL);
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
|
|
|
|
if (!mgr)
|
2021-11-19 09:55:51 +08:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2015-10-07 23:36:28 +08:00
|
|
|
|
2022-05-27 16:59:15 +08:00
|
|
|
id = ida_alloc(&fpga_mgr_ida, GFP_KERNEL);
|
2021-11-19 09:55:51 +08:00
|
|
|
if (id < 0) {
|
|
|
|
ret = id;
|
2015-10-07 23:36:28 +08:00
|
|
|
goto error_kfree;
|
2021-11-19 09:55:51 +08:00
|
|
|
}
|
2015-10-07 23:36:28 +08:00
|
|
|
|
|
|
|
mutex_init(&mgr->ref_mutex);
|
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
mgr->name = info->name;
|
|
|
|
mgr->mops = info->mops;
|
|
|
|
mgr->priv = info->priv;
|
|
|
|
mgr->compat_id = info->compat_id;
|
2015-10-07 23:36:28 +08:00
|
|
|
|
|
|
|
mgr->dev.class = fpga_mgr_class;
|
2017-11-16 04:20:28 +08:00
|
|
|
mgr->dev.groups = mops->groups;
|
2021-06-15 01:09:04 +08:00
|
|
|
mgr->dev.parent = parent;
|
|
|
|
mgr->dev.of_node = parent->of_node;
|
2015-10-07 23:36:28 +08:00
|
|
|
mgr->dev.id = id;
|
|
|
|
|
2015-10-30 03:39:56 +08:00
|
|
|
ret = dev_set_name(&mgr->dev, "fpga%d", id);
|
|
|
|
if (ret)
|
|
|
|
goto error_device;
|
2015-10-07 23:36:28 +08:00
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
/*
|
|
|
|
* Initialize framework state by requesting low level driver read state
|
|
|
|
* from device. FPGA may be in reset mode or may have been programmed
|
|
|
|
* by bootloader or EEPROM.
|
|
|
|
*/
|
|
|
|
mgr->state = fpga_mgr_state(mgr);
|
|
|
|
|
|
|
|
ret = device_register(&mgr->dev);
|
|
|
|
if (ret) {
|
|
|
|
put_device(&mgr->dev);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
2018-05-17 07:49:55 +08:00
|
|
|
return mgr;
|
|
|
|
|
|
|
|
error_device:
|
2022-05-27 16:59:15 +08:00
|
|
|
ida_free(&fpga_mgr_ida, id);
|
2018-05-17 07:49:55 +08:00
|
|
|
error_kfree:
|
|
|
|
kfree(mgr);
|
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
return ERR_PTR(ret);
|
2018-05-17 07:49:55 +08:00
|
|
|
}
|
2021-11-19 09:55:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_register_full);
|
2018-05-17 07:49:55 +08:00
|
|
|
|
|
|
|
/**
|
2021-11-19 09:55:51 +08:00
|
|
|
* fpga_mgr_register - create and register an FPGA Manager device
|
2021-06-15 01:09:04 +08:00
|
|
|
* @parent: fpga manager device from pdev
|
2018-10-16 06:20:01 +08:00
|
|
|
* @name: fpga manager name
|
|
|
|
* @mops: pointer to structure of fpga manager ops
|
|
|
|
* @priv: fpga manager private data
|
|
|
|
*
|
2021-11-19 09:55:51 +08:00
|
|
|
* The caller of this function is responsible for calling fpga_mgr_unregister().
|
|
|
|
* Using devm_fpga_mgr_register() instead is recommended. This simple
|
|
|
|
* version of the register function should be sufficient for most users. The
|
|
|
|
* fpga_mgr_register_full() function is available for users that need to pass
|
|
|
|
* additional, optional parameters.
|
2018-10-16 06:20:01 +08:00
|
|
|
*
|
2021-11-19 09:55:51 +08:00
|
|
|
* Return: pointer to struct fpga_manager pointer or ERR_PTR()
|
2018-10-16 06:20:01 +08:00
|
|
|
*/
|
2021-11-19 09:55:51 +08:00
|
|
|
struct fpga_manager *
|
|
|
|
fpga_mgr_register(struct device *parent, const char *name,
|
|
|
|
const struct fpga_manager_ops *mops, void *priv)
|
2018-10-16 06:20:01 +08:00
|
|
|
{
|
2021-11-19 09:55:51 +08:00
|
|
|
struct fpga_manager_info info = { 0 };
|
2018-10-16 06:20:01 +08:00
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
info.name = name;
|
|
|
|
info.mops = mops;
|
|
|
|
info.priv = priv;
|
2018-10-16 06:20:01 +08:00
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
return fpga_mgr_register_full(parent, &info);
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_register);
|
|
|
|
|
|
|
|
/**
|
2021-06-09 05:23:46 +08:00
|
|
|
* fpga_mgr_unregister - unregister an FPGA manager
|
2018-10-16 06:20:01 +08:00
|
|
|
* @mgr: fpga manager struct
|
|
|
|
*
|
2021-06-09 05:23:46 +08:00
|
|
|
* This function is intended for use in an FPGA manager driver's remove function.
|
2015-10-07 23:36:28 +08:00
|
|
|
*/
|
2018-05-17 07:49:55 +08:00
|
|
|
void fpga_mgr_unregister(struct fpga_manager *mgr)
|
2015-10-07 23:36:28 +08:00
|
|
|
{
|
|
|
|
dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the low level driver provides a method for putting fpga into
|
|
|
|
* a desired state upon unregister, do it.
|
|
|
|
*/
|
2021-06-26 03:51:47 +08:00
|
|
|
fpga_mgr_fpga_remove(mgr);
|
2015-10-07 23:36:28 +08:00
|
|
|
|
|
|
|
device_unregister(&mgr->dev);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_unregister);
|
|
|
|
|
2020-11-16 03:51:18 +08:00
|
|
|
static void devm_fpga_mgr_unregister(struct device *dev, void *res)
|
|
|
|
{
|
|
|
|
struct fpga_mgr_devres *dr = res;
|
|
|
|
|
|
|
|
fpga_mgr_unregister(dr->mgr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-11-19 09:55:51 +08:00
|
|
|
* devm_fpga_mgr_register_full - resource managed variant of fpga_mgr_register()
|
|
|
|
* @parent: fpga manager device from pdev
|
|
|
|
* @info: parameters for fpga manager
|
2020-11-16 03:51:18 +08:00
|
|
|
*
|
2022-04-24 01:02:33 +08:00
|
|
|
* Return: fpga manager pointer on success, negative error code otherwise.
|
|
|
|
*
|
2021-11-19 09:55:51 +08:00
|
|
|
* This is the devres variant of fpga_mgr_register_full() for which the unregister
|
2020-11-16 03:51:18 +08:00
|
|
|
* function will be called automatically when the managing device is detached.
|
|
|
|
*/
|
2021-11-19 09:55:51 +08:00
|
|
|
struct fpga_manager *
|
|
|
|
devm_fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info)
|
2020-11-16 03:51:18 +08:00
|
|
|
{
|
|
|
|
struct fpga_mgr_devres *dr;
|
2021-11-19 09:55:51 +08:00
|
|
|
struct fpga_manager *mgr;
|
2020-11-16 03:51:18 +08:00
|
|
|
|
|
|
|
dr = devres_alloc(devm_fpga_mgr_unregister, sizeof(*dr), GFP_KERNEL);
|
|
|
|
if (!dr)
|
2021-11-19 09:55:51 +08:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2020-11-16 03:51:18 +08:00
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
mgr = fpga_mgr_register_full(parent, info);
|
|
|
|
if (IS_ERR(mgr)) {
|
2020-11-16 03:51:18 +08:00
|
|
|
devres_free(dr);
|
2021-11-19 09:55:51 +08:00
|
|
|
return mgr;
|
2020-11-16 03:51:18 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
dr->mgr = mgr;
|
2021-11-19 09:55:51 +08:00
|
|
|
devres_add(parent, dr);
|
2020-11-16 03:51:18 +08:00
|
|
|
|
2021-11-19 09:55:51 +08:00
|
|
|
return mgr;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(devm_fpga_mgr_register_full);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* devm_fpga_mgr_register - resource managed variant of fpga_mgr_register()
|
|
|
|
* @parent: fpga manager device from pdev
|
|
|
|
* @name: fpga manager name
|
|
|
|
* @mops: pointer to structure of fpga manager ops
|
|
|
|
* @priv: fpga manager private data
|
|
|
|
*
|
2022-04-24 01:02:33 +08:00
|
|
|
* Return: fpga manager pointer on success, negative error code otherwise.
|
|
|
|
*
|
2021-11-19 09:55:51 +08:00
|
|
|
* This is the devres variant of fpga_mgr_register() for which the
|
|
|
|
* unregister function will be called automatically when the managing
|
|
|
|
* device is detached.
|
|
|
|
*/
|
|
|
|
struct fpga_manager *
|
|
|
|
devm_fpga_mgr_register(struct device *parent, const char *name,
|
|
|
|
const struct fpga_manager_ops *mops, void *priv)
|
|
|
|
{
|
|
|
|
struct fpga_manager_info info = { 0 };
|
|
|
|
|
|
|
|
info.name = name;
|
|
|
|
info.mops = mops;
|
|
|
|
info.priv = priv;
|
|
|
|
|
|
|
|
return devm_fpga_mgr_register_full(parent, &info);
|
2020-11-16 03:51:18 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(devm_fpga_mgr_register);
|
|
|
|
|
2015-10-07 23:36:28 +08:00
|
|
|
static void fpga_mgr_dev_release(struct device *dev)
|
|
|
|
{
|
2021-11-19 09:55:51 +08:00
|
|
|
struct fpga_manager *mgr = to_fpga_manager(dev);
|
|
|
|
|
2022-05-27 16:59:15 +08:00
|
|
|
ida_free(&fpga_mgr_ida, mgr->dev.id);
|
2021-11-19 09:55:51 +08:00
|
|
|
kfree(mgr);
|
2015-10-07 23:36:28 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int __init fpga_mgr_class_init(void)
|
|
|
|
{
|
|
|
|
pr_info("FPGA manager framework\n");
|
|
|
|
|
|
|
|
fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager");
|
|
|
|
if (IS_ERR(fpga_mgr_class))
|
|
|
|
return PTR_ERR(fpga_mgr_class);
|
|
|
|
|
|
|
|
fpga_mgr_class->dev_groups = fpga_mgr_groups;
|
|
|
|
fpga_mgr_class->dev_release = fpga_mgr_dev_release;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit fpga_mgr_class_exit(void)
|
|
|
|
{
|
|
|
|
class_destroy(fpga_mgr_class);
|
|
|
|
ida_destroy(&fpga_mgr_ida);
|
|
|
|
}
|
|
|
|
|
2017-11-16 04:20:12 +08:00
|
|
|
MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
|
2015-10-07 23:36:28 +08:00
|
|
|
MODULE_DESCRIPTION("FPGA manager framework");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
|
|
|
|
subsys_initcall(fpga_mgr_class_init);
|
|
|
|
module_exit(fpga_mgr_class_exit);
|