2019-06-04 16:11:33 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2008-12-24 02:55:54 +08:00
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/*
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* Processor cache information made available to userspace via sysfs;
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* intended to be compatible with x86 intel_cacheinfo implementation.
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*
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* Copyright 2008 IBM Corporation
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* Author: Nathan Lynch
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*/
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2019-06-27 13:15:34 +08:00
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#define pr_fmt(fmt) "cacheinfo: " fmt
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2008-12-24 02:55:54 +08:00
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/kernel.h>
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#include <linux/kobject.h>
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#include <linux/list.h>
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#include <linux/notifier.h>
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#include <linux/of.h>
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#include <linux/percpu.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2008-12-24 02:55:54 +08:00
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#include <asm/prom.h>
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2018-10-11 13:33:03 +08:00
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#include <asm/cputhreads.h>
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#include <asm/smp.h>
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2008-12-24 02:55:54 +08:00
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#include "cacheinfo.h"
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/* per-cpu object for tracking:
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* - a "cache" kobject for the top-level directory
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* - a list of "index" objects representing the cpu's local cache hierarchy
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*/
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struct cache_dir {
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struct kobject *kobj; /* bare (not embedded) kobject for cache
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* directory */
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struct cache_index_dir *index; /* list of index objects */
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};
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/* "index" object: each cpu's cache directory has an index
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* subdirectory corresponding to a cache object associated with the
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* cpu. This object's lifetime is managed via the embedded kobject.
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*/
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struct cache_index_dir {
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struct kobject kobj;
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struct cache_index_dir *next; /* next index in parent directory */
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struct cache *cache;
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};
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/* Template for determining which OF properties to query for a given
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* cache type */
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struct cache_type_info {
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const char *name;
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const char *size_prop;
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/* Allow for both [di]-cache-line-size and
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* [di]-cache-block-size properties. According to the PowerPC
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* Processor binding, -line-size should be provided if it
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* differs from the cache block size (that which is operated
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* on by cache instructions), so we look for -line-size first.
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* See cache_get_line_size(). */
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const char *line_size_props[2];
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const char *nr_sets_prop;
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};
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/* These are used to index the cache_type_info array. */
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2015-04-03 12:28:45 +08:00
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#define CACHE_TYPE_UNIFIED 0 /* cache-size, cache-block-size, etc. */
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#define CACHE_TYPE_UNIFIED_D 1 /* d-cache-size, d-cache-block-size, etc */
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#define CACHE_TYPE_INSTRUCTION 2
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#define CACHE_TYPE_DATA 3
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2008-12-24 02:55:54 +08:00
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static const struct cache_type_info cache_type_info[] = {
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2015-04-03 12:28:45 +08:00
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{
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/* Embedded systems that use cache-size, cache-block-size,
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* etc. for the Unified (typically L2) cache. */
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.name = "Unified",
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.size_prop = "cache-size",
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.line_size_props = { "cache-line-size",
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"cache-block-size", },
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.nr_sets_prop = "cache-sets",
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},
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2008-12-24 02:55:54 +08:00
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{
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/* PowerPC Processor binding says the [di]-cache-*
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* must be equal on unified caches, so just use
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* d-cache properties. */
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.name = "Unified",
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.size_prop = "d-cache-size",
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.line_size_props = { "d-cache-line-size",
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"d-cache-block-size", },
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.nr_sets_prop = "d-cache-sets",
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},
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{
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.name = "Instruction",
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.size_prop = "i-cache-size",
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.line_size_props = { "i-cache-line-size",
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"i-cache-block-size", },
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.nr_sets_prop = "i-cache-sets",
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},
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{
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.name = "Data",
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.size_prop = "d-cache-size",
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.line_size_props = { "d-cache-line-size",
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"d-cache-block-size", },
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.nr_sets_prop = "d-cache-sets",
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},
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};
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/* Cache object: each instance of this corresponds to a distinct cache
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* in the system. There are separate objects for Harvard caches: one
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* each for instruction and data, and each refers to the same OF node.
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* The refcount of the OF node is elevated for the lifetime of the
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* cache object. A cache object is released when its shared_cpu_map
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* is cleared (see cache_cpu_clear).
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*
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* A cache object is on two lists: an unsorted global list
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* (cache_list) of cache objects; and a singly-linked list
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* representing the local cache hierarchy, which is ordered by level
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* (e.g. L1d -> L1i -> L2 -> L3).
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*/
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struct cache {
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struct device_node *ofnode; /* OF node for this cache, may be cpu */
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struct cpumask shared_cpu_map; /* online CPUs using this cache */
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int type; /* split cache disambiguation */
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int level; /* level not explicit in device tree */
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powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
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int group_id; /* id of the group of threads that share this cache */
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2008-12-24 02:55:54 +08:00
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struct list_head list; /* global list of cache objects */
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struct cache *next_local; /* next cache of >= level */
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};
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2009-01-09 21:12:44 +08:00
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static DEFINE_PER_CPU(struct cache_dir *, cache_dir_pcpu);
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2008-12-24 02:55:54 +08:00
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/* traversal/modification of this list occurs only at cpu hotplug time;
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* access is serialized by cpu hotplug locking
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*/
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static LIST_HEAD(cache_list);
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static struct cache_index_dir *kobj_to_cache_index_dir(struct kobject *k)
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{
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return container_of(k, struct cache_index_dir, kobj);
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}
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static const char *cache_type_string(const struct cache *cache)
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{
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return cache_type_info[cache->type].name;
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}
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2013-06-25 03:30:09 +08:00
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static void cache_init(struct cache *cache, int type, int level,
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powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
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struct device_node *ofnode, int group_id)
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2008-12-24 02:55:54 +08:00
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{
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cache->type = type;
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cache->level = level;
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cache->ofnode = of_node_get(ofnode);
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powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
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cache->group_id = group_id;
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2008-12-24 02:55:54 +08:00
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INIT_LIST_HEAD(&cache->list);
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list_add(&cache->list, &cache_list);
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}
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powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
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static struct cache *new_cache(int type, int level,
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struct device_node *ofnode, int group_id)
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2008-12-24 02:55:54 +08:00
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{
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struct cache *cache;
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cache = kzalloc(sizeof(*cache), GFP_KERNEL);
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if (cache)
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powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
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cache_init(cache, type, level, ofnode, group_id);
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2008-12-24 02:55:54 +08:00
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return cache;
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}
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static void release_cache_debugcheck(struct cache *cache)
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{
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struct cache *iter;
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list_for_each_entry(iter, &cache_list, list)
|
|
|
|
WARN_ONCE(iter->next_local == cache,
|
2019-06-27 13:15:35 +08:00
|
|
|
"cache for %pOFP(%s) refers to cache for %pOFP(%s)\n",
|
2017-08-21 23:16:47 +08:00
|
|
|
iter->ofnode,
|
2008-12-24 02:55:54 +08:00
|
|
|
cache_type_string(iter),
|
2017-08-21 23:16:47 +08:00
|
|
|
cache->ofnode,
|
2008-12-24 02:55:54 +08:00
|
|
|
cache_type_string(cache));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void release_cache(struct cache *cache)
|
|
|
|
{
|
|
|
|
if (!cache)
|
|
|
|
return;
|
|
|
|
|
2019-06-27 13:15:35 +08:00
|
|
|
pr_debug("freeing L%d %s cache for %pOFP\n", cache->level,
|
2017-08-21 23:16:47 +08:00
|
|
|
cache_type_string(cache), cache->ofnode);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
release_cache_debugcheck(cache);
|
|
|
|
list_del(&cache->list);
|
|
|
|
of_node_put(cache->ofnode);
|
|
|
|
kfree(cache);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cache_cpu_set(struct cache *cache, int cpu)
|
|
|
|
{
|
|
|
|
struct cache *next = cache;
|
|
|
|
|
|
|
|
while (next) {
|
|
|
|
WARN_ONCE(cpumask_test_cpu(cpu, &next->shared_cpu_map),
|
2019-06-27 13:15:35 +08:00
|
|
|
"CPU %i already accounted in %pOFP(%s)\n",
|
2017-08-21 23:16:47 +08:00
|
|
|
cpu, next->ofnode,
|
2008-12-24 02:55:54 +08:00
|
|
|
cache_type_string(next));
|
|
|
|
cpumask_set_cpu(cpu, &next->shared_cpu_map);
|
|
|
|
next = next->next_local;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cache_size(const struct cache *cache, unsigned int *ret)
|
|
|
|
{
|
|
|
|
const char *propname;
|
2013-08-07 00:01:37 +08:00
|
|
|
const __be32 *cache_size;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
propname = cache_type_info[cache->type].size_prop;
|
|
|
|
|
|
|
|
cache_size = of_get_property(cache->ofnode, propname, NULL);
|
|
|
|
if (!cache_size)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-08-07 00:01:37 +08:00
|
|
|
*ret = of_read_number(cache_size, 1);
|
2008-12-24 02:55:54 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cache_size_kb(const struct cache *cache, unsigned int *ret)
|
|
|
|
{
|
|
|
|
unsigned int size;
|
|
|
|
|
|
|
|
if (cache_size(cache, &size))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
*ret = size / 1024;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* not cache_line_size() because that's a macro in include/linux/cache.h */
|
|
|
|
static int cache_get_line_size(const struct cache *cache, unsigned int *ret)
|
|
|
|
{
|
2013-08-07 00:01:37 +08:00
|
|
|
const __be32 *line_size;
|
2008-12-24 02:55:54 +08:00
|
|
|
int i, lim;
|
|
|
|
|
|
|
|
lim = ARRAY_SIZE(cache_type_info[cache->type].line_size_props);
|
|
|
|
|
|
|
|
for (i = 0; i < lim; i++) {
|
|
|
|
const char *propname;
|
|
|
|
|
|
|
|
propname = cache_type_info[cache->type].line_size_props[i];
|
|
|
|
line_size = of_get_property(cache->ofnode, propname, NULL);
|
|
|
|
if (line_size)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!line_size)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-08-07 00:01:37 +08:00
|
|
|
*ret = of_read_number(line_size, 1);
|
2008-12-24 02:55:54 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cache_nr_sets(const struct cache *cache, unsigned int *ret)
|
|
|
|
{
|
|
|
|
const char *propname;
|
2013-08-07 00:01:37 +08:00
|
|
|
const __be32 *nr_sets;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
propname = cache_type_info[cache->type].nr_sets_prop;
|
|
|
|
|
|
|
|
nr_sets = of_get_property(cache->ofnode, propname, NULL);
|
|
|
|
if (!nr_sets)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-08-07 00:01:37 +08:00
|
|
|
*ret = of_read_number(nr_sets, 1);
|
2008-12-24 02:55:54 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cache_associativity(const struct cache *cache, unsigned int *ret)
|
|
|
|
{
|
|
|
|
unsigned int line_size;
|
|
|
|
unsigned int nr_sets;
|
|
|
|
unsigned int size;
|
|
|
|
|
|
|
|
if (cache_nr_sets(cache, &nr_sets))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
/* If the cache is fully associative, there is no need to
|
|
|
|
* check the other properties.
|
|
|
|
*/
|
|
|
|
if (nr_sets == 1) {
|
|
|
|
*ret = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cache_get_line_size(cache, &line_size))
|
|
|
|
goto err;
|
|
|
|
if (cache_size(cache, &size))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
if (!(nr_sets > 0 && size > 0 && line_size > 0))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
*ret = (size / nr_sets) / line_size;
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* helper for dealing with split caches */
|
|
|
|
static struct cache *cache_find_first_sibling(struct cache *cache)
|
|
|
|
{
|
|
|
|
struct cache *iter;
|
|
|
|
|
2015-04-03 12:28:45 +08:00
|
|
|
if (cache->type == CACHE_TYPE_UNIFIED ||
|
|
|
|
cache->type == CACHE_TYPE_UNIFIED_D)
|
2008-12-24 02:55:54 +08:00
|
|
|
return cache;
|
|
|
|
|
|
|
|
list_for_each_entry(iter, &cache_list, list)
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
if (iter->ofnode == cache->ofnode &&
|
|
|
|
iter->group_id == cache->group_id &&
|
|
|
|
iter->next_local == cache)
|
2008-12-24 02:55:54 +08:00
|
|
|
return iter;
|
|
|
|
|
|
|
|
return cache;
|
|
|
|
}
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
/* return the first cache on a local list matching node and thread-group id */
|
|
|
|
static struct cache *cache_lookup_by_node_group(const struct device_node *node,
|
|
|
|
int group_id)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache *cache = NULL;
|
|
|
|
struct cache *iter;
|
|
|
|
|
|
|
|
list_for_each_entry(iter, &cache_list, list) {
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
if (iter->ofnode != node ||
|
|
|
|
iter->group_id != group_id)
|
2008-12-24 02:55:54 +08:00
|
|
|
continue;
|
|
|
|
cache = cache_find_first_sibling(iter);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return cache;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cache_node_is_unified(const struct device_node *np)
|
|
|
|
{
|
|
|
|
return of_get_property(np, "cache-unified", NULL);
|
|
|
|
}
|
|
|
|
|
2015-04-03 12:28:45 +08:00
|
|
|
/*
|
|
|
|
* Unified caches can have two different sets of tags. Most embedded
|
|
|
|
* use cache-size, etc. for the unified cache size, but open firmware systems
|
|
|
|
* use d-cache-size, etc. Check on initialization for which type we have, and
|
|
|
|
* return the appropriate structure type. Assume it's embedded if it isn't
|
|
|
|
* open firmware. If it's yet a 3rd type, then there will be missing entries
|
|
|
|
* in /sys/devices/system/cpu/cpu0/cache/index2/, and this code will need
|
|
|
|
* to be extended further.
|
|
|
|
*/
|
|
|
|
static int cache_is_unified_d(const struct device_node *np)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
2015-04-03 12:28:45 +08:00
|
|
|
return of_get_property(np,
|
|
|
|
cache_type_info[CACHE_TYPE_UNIFIED_D].size_prop, NULL) ?
|
|
|
|
CACHE_TYPE_UNIFIED_D : CACHE_TYPE_UNIFIED;
|
|
|
|
}
|
2008-12-24 02:55:54 +08:00
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
static struct cache *cache_do_one_devnode_unified(struct device_node *node, int group_id,
|
|
|
|
int level)
|
2015-04-03 12:28:45 +08:00
|
|
|
{
|
2019-06-27 13:15:35 +08:00
|
|
|
pr_debug("creating L%d ucache for %pOFP\n", level, node);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
return new_cache(cache_is_unified_d(node), level, node, group_id);
|
2008-12-24 02:55:54 +08:00
|
|
|
}
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
static struct cache *cache_do_one_devnode_split(struct device_node *node, int group_id,
|
2013-06-25 03:30:09 +08:00
|
|
|
int level)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache *dcache, *icache;
|
|
|
|
|
2019-06-27 13:15:35 +08:00
|
|
|
pr_debug("creating L%d dcache and icache for %pOFP\n", level,
|
2017-08-21 23:16:47 +08:00
|
|
|
node);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
dcache = new_cache(CACHE_TYPE_DATA, level, node, group_id);
|
|
|
|
icache = new_cache(CACHE_TYPE_INSTRUCTION, level, node, group_id);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
if (!dcache || !icache)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
dcache->next_local = icache;
|
|
|
|
|
|
|
|
return dcache;
|
|
|
|
err:
|
|
|
|
release_cache(dcache);
|
|
|
|
release_cache(icache);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
static struct cache *cache_do_one_devnode(struct device_node *node, int group_id, int level)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
if (cache_node_is_unified(node))
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
cache = cache_do_one_devnode_unified(node, group_id, level);
|
2008-12-24 02:55:54 +08:00
|
|
|
else
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
cache = cache_do_one_devnode_split(node, group_id, level);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
return cache;
|
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static struct cache *cache_lookup_or_instantiate(struct device_node *node,
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
int group_id,
|
2013-06-25 03:30:09 +08:00
|
|
|
int level)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache *cache;
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
cache = cache_lookup_by_node_group(node, group_id);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
WARN_ONCE(cache && cache->level != level,
|
|
|
|
"cache level mismatch on lookup (got %d, expected %d)\n",
|
|
|
|
cache->level, level);
|
|
|
|
|
|
|
|
if (!cache)
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
cache = cache_do_one_devnode(node, group_id, level);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
return cache;
|
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static void link_cache_lists(struct cache *smaller, struct cache *bigger)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
while (smaller->next_local) {
|
|
|
|
if (smaller->next_local == bigger)
|
|
|
|
return; /* already linked */
|
|
|
|
smaller = smaller->next_local;
|
|
|
|
}
|
|
|
|
|
|
|
|
smaller->next_local = bigger;
|
2019-06-27 13:15:37 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The cache->next_local list sorts by level ascending:
|
|
|
|
* L1d -> L1i -> L2 -> L3 ...
|
|
|
|
*/
|
|
|
|
WARN_ONCE((smaller->level == 1 && bigger->level > 2) ||
|
|
|
|
(smaller->level > 1 && bigger->level != smaller->level + 1),
|
|
|
|
"linking L%i cache %pOFP to L%i cache %pOFP; skipped a level?\n",
|
|
|
|
smaller->level, smaller->ofnode, bigger->level, bigger->ofnode);
|
2008-12-24 02:55:54 +08:00
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static void do_subsidiary_caches_debugcheck(struct cache *cache)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
2019-06-27 13:15:36 +08:00
|
|
|
WARN_ONCE(cache->level != 1,
|
|
|
|
"instantiating cache chain from L%d %s cache for "
|
|
|
|
"%pOFP instead of an L1\n", cache->level,
|
|
|
|
cache_type_string(cache), cache->ofnode);
|
|
|
|
WARN_ONCE(!of_node_is_type(cache->ofnode, "cpu"),
|
|
|
|
"instantiating cache chain from node %pOFP of type '%s' "
|
|
|
|
"instead of a cpu node\n", cache->ofnode,
|
|
|
|
of_node_get_device_type(cache->ofnode));
|
2008-12-24 02:55:54 +08:00
|
|
|
}
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
/*
|
|
|
|
* If sub-groups of threads in a core containing @cpu_id share the
|
|
|
|
* L@level-cache (information obtained via "ibm,thread-groups"
|
|
|
|
* device-tree property), then we identify the group by the first
|
|
|
|
* thread-sibling in the group. We define this to be the group-id.
|
|
|
|
*
|
|
|
|
* In the absence of any thread-group information for L@level-cache,
|
|
|
|
* this function returns -1.
|
|
|
|
*/
|
|
|
|
static int get_group_id(unsigned int cpu_id, int level)
|
|
|
|
{
|
|
|
|
if (has_big_cores && level == 1)
|
|
|
|
return cpumask_first(per_cpu(thread_group_l1_cache_map,
|
|
|
|
cpu_id));
|
|
|
|
else if (thread_group_shares_l2 && level == 2)
|
|
|
|
return cpumask_first(per_cpu(thread_group_l2_cache_map,
|
|
|
|
cpu_id));
|
2021-07-29 01:56:07 +08:00
|
|
|
else if (thread_group_shares_l3 && level == 3)
|
|
|
|
return cpumask_first(per_cpu(thread_group_l3_cache_map,
|
|
|
|
cpu_id));
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void do_subsidiary_caches(struct cache *cache, unsigned int cpu_id)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct device_node *subcache_node;
|
|
|
|
int level = cache->level;
|
|
|
|
|
|
|
|
do_subsidiary_caches_debugcheck(cache);
|
|
|
|
|
|
|
|
while ((subcache_node = of_find_next_cache_node(cache->ofnode))) {
|
|
|
|
struct cache *subcache;
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
int group_id;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
level++;
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
group_id = get_group_id(cpu_id, level);
|
|
|
|
subcache = cache_lookup_or_instantiate(subcache_node, group_id, level);
|
2008-12-24 02:55:54 +08:00
|
|
|
of_node_put(subcache_node);
|
|
|
|
if (!subcache)
|
|
|
|
break;
|
|
|
|
|
|
|
|
link_cache_lists(cache, subcache);
|
|
|
|
cache = subcache;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static struct cache *cache_chain_instantiate(unsigned int cpu_id)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct device_node *cpu_node;
|
|
|
|
struct cache *cpu_cache = NULL;
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
int group_id;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
pr_debug("creating cache object(s) for CPU %i\n", cpu_id);
|
|
|
|
|
|
|
|
cpu_node = of_get_cpu_node(cpu_id, NULL);
|
|
|
|
WARN_ONCE(!cpu_node, "no OF node found for CPU %i\n", cpu_id);
|
|
|
|
if (!cpu_node)
|
|
|
|
goto out;
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
group_id = get_group_id(cpu_id, 1);
|
|
|
|
|
|
|
|
cpu_cache = cache_lookup_or_instantiate(cpu_node, group_id, 1);
|
2008-12-24 02:55:54 +08:00
|
|
|
if (!cpu_cache)
|
|
|
|
goto out;
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
do_subsidiary_caches(cpu_cache, cpu_id);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
cache_cpu_set(cpu_cache, cpu_id);
|
|
|
|
out:
|
|
|
|
of_node_put(cpu_node);
|
|
|
|
|
|
|
|
return cpu_cache;
|
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static struct cache_dir *cacheinfo_create_cache_dir(unsigned int cpu_id)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache_dir *cache_dir;
|
2011-12-22 06:29:42 +08:00
|
|
|
struct device *dev;
|
2008-12-24 02:55:54 +08:00
|
|
|
struct kobject *kobj = NULL;
|
|
|
|
|
2011-12-22 06:29:42 +08:00
|
|
|
dev = get_cpu_device(cpu_id);
|
|
|
|
WARN_ONCE(!dev, "no dev for CPU %i\n", cpu_id);
|
|
|
|
if (!dev)
|
2008-12-24 02:55:54 +08:00
|
|
|
goto err;
|
|
|
|
|
2011-12-22 06:29:42 +08:00
|
|
|
kobj = kobject_create_and_add("cache", &dev->kobj);
|
2008-12-24 02:55:54 +08:00
|
|
|
if (!kobj)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
cache_dir = kzalloc(sizeof(*cache_dir), GFP_KERNEL);
|
|
|
|
if (!cache_dir)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
cache_dir->kobj = kobj;
|
|
|
|
|
2009-01-09 21:12:44 +08:00
|
|
|
WARN_ON_ONCE(per_cpu(cache_dir_pcpu, cpu_id) != NULL);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
2009-01-09 21:12:44 +08:00
|
|
|
per_cpu(cache_dir_pcpu, cpu_id) = cache_dir;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
return cache_dir;
|
|
|
|
err:
|
|
|
|
kobject_put(kobj);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cache_index_release(struct kobject *kobj)
|
|
|
|
{
|
|
|
|
struct cache_index_dir *index;
|
|
|
|
|
|
|
|
index = kobj_to_cache_index_dir(kobj);
|
|
|
|
|
|
|
|
pr_debug("freeing index directory for L%d %s cache\n",
|
|
|
|
index->cache->level, cache_type_string(index->cache));
|
|
|
|
|
|
|
|
kfree(index);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t cache_index_show(struct kobject *k, struct attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct kobj_attribute *kobj_attr;
|
|
|
|
|
|
|
|
kobj_attr = container_of(attr, struct kobj_attribute, attr);
|
|
|
|
|
|
|
|
return kobj_attr->show(k, kobj_attr, buf);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct cache *index_kobj_to_cache(struct kobject *k)
|
|
|
|
{
|
|
|
|
struct cache_index_dir *index;
|
|
|
|
|
|
|
|
index = kobj_to_cache_index_dir(k);
|
|
|
|
|
|
|
|
return index->cache;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t size_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
unsigned int size_kb;
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
cache = index_kobj_to_cache(k);
|
|
|
|
|
|
|
|
if (cache_size_kb(cache, &size_kb))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return sprintf(buf, "%uK\n", size_kb);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct kobj_attribute cache_size_attr =
|
|
|
|
__ATTR(size, 0444, size_show, NULL);
|
|
|
|
|
|
|
|
|
|
|
|
static ssize_t line_size_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
unsigned int line_size;
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
cache = index_kobj_to_cache(k);
|
|
|
|
|
|
|
|
if (cache_get_line_size(cache, &line_size))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return sprintf(buf, "%u\n", line_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct kobj_attribute cache_line_size_attr =
|
|
|
|
__ATTR(coherency_line_size, 0444, line_size_show, NULL);
|
|
|
|
|
|
|
|
static ssize_t nr_sets_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
unsigned int nr_sets;
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
cache = index_kobj_to_cache(k);
|
|
|
|
|
|
|
|
if (cache_nr_sets(cache, &nr_sets))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return sprintf(buf, "%u\n", nr_sets);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct kobj_attribute cache_nr_sets_attr =
|
|
|
|
__ATTR(number_of_sets, 0444, nr_sets_show, NULL);
|
|
|
|
|
|
|
|
static ssize_t associativity_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
unsigned int associativity;
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
cache = index_kobj_to_cache(k);
|
|
|
|
|
|
|
|
if (cache_associativity(cache, &associativity))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return sprintf(buf, "%u\n", associativity);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct kobj_attribute cache_assoc_attr =
|
|
|
|
__ATTR(ways_of_associativity, 0444, associativity_show, NULL);
|
|
|
|
|
|
|
|
static ssize_t type_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
cache = index_kobj_to_cache(k);
|
|
|
|
|
|
|
|
return sprintf(buf, "%s\n", cache_type_string(cache));
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct kobj_attribute cache_type_attr =
|
|
|
|
__ATTR(type, 0444, type_show, NULL);
|
|
|
|
|
|
|
|
static ssize_t level_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct cache_index_dir *index;
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
index = kobj_to_cache_index_dir(k);
|
|
|
|
cache = index->cache;
|
|
|
|
|
|
|
|
return sprintf(buf, "%d\n", cache->level);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct kobj_attribute cache_level_attr =
|
|
|
|
__ATTR(level, 0444, level_show, NULL);
|
|
|
|
|
2020-06-29 18:37:02 +08:00
|
|
|
static ssize_t
|
|
|
|
show_shared_cpumap(struct kobject *k, struct kobj_attribute *attr, char *buf, bool list)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache_index_dir *index;
|
|
|
|
struct cache *cache;
|
2018-10-11 13:33:03 +08:00
|
|
|
const struct cpumask *mask;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
index = kobj_to_cache_index_dir(k);
|
|
|
|
cache = index->cache;
|
|
|
|
|
powerpc/cacheinfo: Remove the redundant get_shared_cpu_map()
The helper function get_shared_cpu_map() was added in
'commit 500fe5f550ec ("powerpc/cacheinfo: Report the correct
shared_cpu_map on big-cores")'
and subsequently expanded upon in
'commit 0be47634db0b ("powerpc/cacheinfo: Print correct cache-sibling
map/list for L2 cache")'
in order to help report the correct groups of threads sharing these caches
on big-core systems where groups of threads within a core can share
different sets of caches.
Now that powerpc/cacheinfo is aware of "ibm,thread-groups" property,
cache->shared_cpu_map contains the correct set of thread-siblings
sharing the cache. Hence we no longer need the functions
get_shared_cpu_map(). This patch removes this function. We also remove
the helper function index_dir_to_cpu() which was only called by
get_shared_cpu_map().
With these functions removed, we can still see the correct
cache-sibling map/list for L1 and L2 caches on systems with L1 and L2
caches distributed among groups of threads in a core.
With this patch, on a SMT8 POWER10 system where the L1 and L2 caches
are split between the two groups of threads in a core, for CPUs 8,9,
the L1-Data, L1-Instruction, L2, L3 cache CPU sibling list is as
follows:
$ grep . /sys/devices/system/cpu/cpu[89]/cache/index[0123]/shared_cpu_list
/sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8,10,12,14
/sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8,10,12,14
/sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8,10,12,14
/sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8-15
/sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9,11,13,15
/sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9,11,13,15
/sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9,11,13,15
/sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:8-15
$ ppc64_cpu --smt=4
$ grep . /sys/devices/system/cpu/cpu[89]/cache/index[0123]/shared_cpu_list
/sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8,10
/sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8,10
/sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8,10
/sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8-11
/sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9,11
/sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9,11
/sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9,11
/sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:8-11
$ ppc64_cpu --smt=2
$ grep . /sys/devices/system/cpu/cpu[89]/cache/index[0123]/shared_cpu_list
/sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8
/sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8
/sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8
/sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8-9
/sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9
/sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9
/sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9
/sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:8-9
$ ppc64_cpu --smt=1
$ grep . /sys/devices/system/cpu/cpu[89]/cache/index[0123]/shared_cpu_list
/sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8
/sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8
/sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8
/sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-3-parth@linux.ibm.com
2021-07-29 01:56:06 +08:00
|
|
|
mask = &cache->shared_cpu_map;
|
2018-10-11 13:33:03 +08:00
|
|
|
|
2020-06-29 18:37:02 +08:00
|
|
|
return cpumap_print_to_pagebuf(list, buf, mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t shared_cpu_map_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
2020-06-29 18:37:03 +08:00
|
|
|
return show_shared_cpumap(k, attr, buf, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t shared_cpu_list_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
return show_shared_cpumap(k, attr, buf, true);
|
2008-12-24 02:55:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct kobj_attribute cache_shared_cpu_map_attr =
|
|
|
|
__ATTR(shared_cpu_map, 0444, shared_cpu_map_show, NULL);
|
|
|
|
|
2020-06-29 18:37:03 +08:00
|
|
|
static struct kobj_attribute cache_shared_cpu_list_attr =
|
|
|
|
__ATTR(shared_cpu_list, 0444, shared_cpu_list_show, NULL);
|
|
|
|
|
2008-12-24 02:55:54 +08:00
|
|
|
/* Attributes which should always be created -- the kobject/sysfs core
|
|
|
|
* does this automatically via kobj_type->default_attrs. This is the
|
|
|
|
* minimum data required to uniquely identify a cache.
|
|
|
|
*/
|
|
|
|
static struct attribute *cache_index_default_attrs[] = {
|
|
|
|
&cache_type_attr.attr,
|
|
|
|
&cache_level_attr.attr,
|
|
|
|
&cache_shared_cpu_map_attr.attr,
|
2020-06-29 18:37:03 +08:00
|
|
|
&cache_shared_cpu_list_attr.attr,
|
2008-12-24 02:55:54 +08:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Attributes which should be created if the cache device node has the
|
|
|
|
* right properties -- see cacheinfo_create_index_opt_attrs
|
|
|
|
*/
|
|
|
|
static struct kobj_attribute *cache_index_opt_attrs[] = {
|
|
|
|
&cache_size_attr,
|
|
|
|
&cache_line_size_attr,
|
|
|
|
&cache_nr_sets_attr,
|
|
|
|
&cache_assoc_attr,
|
|
|
|
};
|
|
|
|
|
2010-01-19 09:58:23 +08:00
|
|
|
static const struct sysfs_ops cache_index_ops = {
|
2008-12-24 02:55:54 +08:00
|
|
|
.show = cache_index_show,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct kobj_type cache_index_type = {
|
|
|
|
.release = cache_index_release,
|
|
|
|
.sysfs_ops = &cache_index_ops,
|
|
|
|
.default_attrs = cache_index_default_attrs,
|
|
|
|
};
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static void cacheinfo_create_index_opt_attrs(struct cache_index_dir *dir)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
const char *cache_type;
|
|
|
|
struct cache *cache;
|
|
|
|
char *buf;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
|
|
|
if (!buf)
|
|
|
|
return;
|
|
|
|
|
|
|
|
cache = dir->cache;
|
|
|
|
cache_type = cache_type_string(cache);
|
|
|
|
|
|
|
|
/* We don't want to create an attribute that can't provide a
|
|
|
|
* meaningful value. Check the return value of each optional
|
|
|
|
* attribute's ->show method before registering the
|
|
|
|
* attribute.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cache_index_opt_attrs); i++) {
|
|
|
|
struct kobj_attribute *attr;
|
|
|
|
ssize_t rc;
|
|
|
|
|
|
|
|
attr = cache_index_opt_attrs[i];
|
|
|
|
|
|
|
|
rc = attr->show(&dir->kobj, attr, buf);
|
|
|
|
if (rc <= 0) {
|
|
|
|
pr_debug("not creating %s attribute for "
|
2019-06-27 13:15:35 +08:00
|
|
|
"%pOFP(%s) (rc = %zd)\n",
|
2017-08-21 23:16:47 +08:00
|
|
|
attr->attr.name, cache->ofnode,
|
2008-12-24 02:55:54 +08:00
|
|
|
cache_type, rc);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (sysfs_create_file(&dir->kobj, &attr->attr))
|
2019-06-27 13:15:35 +08:00
|
|
|
pr_debug("could not create %s attribute for %pOFP(%s)\n",
|
2017-08-21 23:16:47 +08:00
|
|
|
attr->attr.name, cache->ofnode, cache_type);
|
2008-12-24 02:55:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
kfree(buf);
|
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static void cacheinfo_create_index_dir(struct cache *cache, int index,
|
|
|
|
struct cache_dir *cache_dir)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache_index_dir *index_dir;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
index_dir = kzalloc(sizeof(*index_dir), GFP_KERNEL);
|
|
|
|
if (!index_dir)
|
2019-04-30 09:09:23 +08:00
|
|
|
return;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
index_dir->cache = cache;
|
|
|
|
|
|
|
|
rc = kobject_init_and_add(&index_dir->kobj, &cache_index_type,
|
|
|
|
cache_dir->kobj, "index%d", index);
|
2019-04-30 09:09:23 +08:00
|
|
|
if (rc) {
|
|
|
|
kobject_put(&index_dir->kobj);
|
|
|
|
return;
|
|
|
|
}
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
index_dir->next = cache_dir->index;
|
|
|
|
cache_dir->index = index_dir;
|
|
|
|
|
|
|
|
cacheinfo_create_index_opt_attrs(index_dir);
|
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
static void cacheinfo_sysfs_populate(unsigned int cpu_id,
|
|
|
|
struct cache *cache_list)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache_dir *cache_dir;
|
|
|
|
struct cache *cache;
|
|
|
|
int index = 0;
|
|
|
|
|
|
|
|
cache_dir = cacheinfo_create_cache_dir(cpu_id);
|
|
|
|
if (!cache_dir)
|
|
|
|
return;
|
|
|
|
|
|
|
|
cache = cache_list;
|
|
|
|
while (cache) {
|
|
|
|
cacheinfo_create_index_dir(cache, index, cache_dir);
|
|
|
|
index++;
|
|
|
|
cache = cache->next_local;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-25 03:30:09 +08:00
|
|
|
void cacheinfo_cpu_online(unsigned int cpu_id)
|
2008-12-24 02:55:54 +08:00
|
|
|
{
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
cache = cache_chain_instantiate(cpu_id);
|
|
|
|
if (!cache)
|
|
|
|
return;
|
|
|
|
|
|
|
|
cacheinfo_sysfs_populate(cpu_id, cache);
|
|
|
|
}
|
|
|
|
|
2014-02-26 12:02:18 +08:00
|
|
|
/* functions needed to remove cache entry for cpu offline or suspend/resume */
|
|
|
|
|
|
|
|
#if (defined(CONFIG_PPC_PSERIES) && defined(CONFIG_SUSPEND)) || \
|
|
|
|
defined(CONFIG_HOTPLUG_CPU)
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
static struct cache *cache_lookup_by_cpu(unsigned int cpu_id)
|
|
|
|
{
|
|
|
|
struct device_node *cpu_node;
|
|
|
|
struct cache *cache;
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
int group_id;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
cpu_node = of_get_cpu_node(cpu_id, NULL);
|
|
|
|
WARN_ONCE(!cpu_node, "no OF node found for CPU %i\n", cpu_id);
|
|
|
|
if (!cpu_node)
|
|
|
|
return NULL;
|
|
|
|
|
powerpc/cacheinfo: Lookup cache by dt node and thread-group id
Currently the cacheinfo code on powerpc indexes the "cache" objects
(modelling the L1/L2/L3 caches) where the key is device-tree node
corresponding to that cache. On some of the POWER server platforms
thread-groups within the core share different sets of caches (Eg: On
SMT8 POWER9 systems, threads 0,2,4,6 of a core share L1 cache and
threads 1,3,5,7 of the same core share another L1 cache). On such
platforms, there is a single device-tree node corresponding to that
cache and the cache-configuration within the threads of the core is
indicated via "ibm,thread-groups" device-tree property.
Since the current code is not aware of the "ibm,thread-groups"
property, on the aforementoined systems, cacheinfo code still treats
all the threads in the core to be sharing the cache because of the
single device-tree node (In the earlier example, the cacheinfo code
would says CPUs 0-7 share L1 cache).
In this patch, we make the powerpc cacheinfo code aware of the
"ibm,thread-groups" property. We indexe the "cache" objects by the
key-pair (device-tree node, thread-group id). For any CPUX, for a
given level of cache, the thread-group id is defined to be the first
CPU in the "ibm,thread-groups" cache-group containing CPUX. For levels
of cache which are not represented in "ibm,thread-groups" property,
the thread-group id is -1.
[parth: Remove "static" keyword for the definition of "thread_group_l1_cache_map"
and "thread_group_l2_cache_map" to get rid of the compile error.]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Parth Shah <parth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210728175607.591679-2-parth@linux.ibm.com
2021-07-29 01:56:05 +08:00
|
|
|
group_id = get_group_id(cpu_id, 1);
|
|
|
|
cache = cache_lookup_by_node_group(cpu_node, group_id);
|
2008-12-24 02:55:54 +08:00
|
|
|
of_node_put(cpu_node);
|
|
|
|
|
|
|
|
return cache;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void remove_index_dirs(struct cache_dir *cache_dir)
|
|
|
|
{
|
|
|
|
struct cache_index_dir *index;
|
|
|
|
|
|
|
|
index = cache_dir->index;
|
|
|
|
|
|
|
|
while (index) {
|
|
|
|
struct cache_index_dir *next;
|
|
|
|
|
|
|
|
next = index->next;
|
|
|
|
kobject_put(&index->kobj);
|
|
|
|
index = next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void remove_cache_dir(struct cache_dir *cache_dir)
|
|
|
|
{
|
|
|
|
remove_index_dirs(cache_dir);
|
|
|
|
|
2014-01-18 18:14:47 +08:00
|
|
|
/* Remove cache dir from sysfs */
|
|
|
|
kobject_del(cache_dir->kobj);
|
|
|
|
|
2008-12-24 02:55:54 +08:00
|
|
|
kobject_put(cache_dir->kobj);
|
|
|
|
|
|
|
|
kfree(cache_dir);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cache_cpu_clear(struct cache *cache, int cpu)
|
|
|
|
{
|
|
|
|
while (cache) {
|
|
|
|
struct cache *next = cache->next_local;
|
|
|
|
|
|
|
|
WARN_ONCE(!cpumask_test_cpu(cpu, &cache->shared_cpu_map),
|
2019-06-27 13:15:35 +08:00
|
|
|
"CPU %i not accounted in %pOFP(%s)\n",
|
2017-08-21 23:16:47 +08:00
|
|
|
cpu, cache->ofnode,
|
2008-12-24 02:55:54 +08:00
|
|
|
cache_type_string(cache));
|
|
|
|
|
|
|
|
cpumask_clear_cpu(cpu, &cache->shared_cpu_map);
|
|
|
|
|
|
|
|
/* Release the cache object if all the cpus using it
|
|
|
|
* are offline */
|
|
|
|
if (cpumask_empty(&cache->shared_cpu_map))
|
|
|
|
release_cache(cache);
|
|
|
|
|
|
|
|
cache = next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void cacheinfo_cpu_offline(unsigned int cpu_id)
|
|
|
|
{
|
|
|
|
struct cache_dir *cache_dir;
|
|
|
|
struct cache *cache;
|
|
|
|
|
|
|
|
/* Prevent userspace from seeing inconsistent state - remove
|
|
|
|
* the sysfs hierarchy first */
|
2009-01-09 21:12:44 +08:00
|
|
|
cache_dir = per_cpu(cache_dir_pcpu, cpu_id);
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
/* careful, sysfs population may have failed */
|
|
|
|
if (cache_dir)
|
|
|
|
remove_cache_dir(cache_dir);
|
|
|
|
|
2009-01-09 21:12:44 +08:00
|
|
|
per_cpu(cache_dir_pcpu, cpu_id) = NULL;
|
2008-12-24 02:55:54 +08:00
|
|
|
|
|
|
|
/* clear the CPU's bit in its cache chain, possibly freeing
|
|
|
|
* cache objects */
|
|
|
|
cache = cache_lookup_by_cpu(cpu_id);
|
|
|
|
if (cache)
|
|
|
|
cache_cpu_clear(cache, cpu_id);
|
|
|
|
}
|
2019-06-12 12:45:04 +08:00
|
|
|
|
|
|
|
void cacheinfo_teardown(void)
|
|
|
|
{
|
|
|
|
unsigned int cpu;
|
|
|
|
|
|
|
|
lockdep_assert_cpus_held();
|
|
|
|
|
|
|
|
for_each_online_cpu(cpu)
|
|
|
|
cacheinfo_cpu_offline(cpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cacheinfo_rebuild(void)
|
|
|
|
{
|
|
|
|
unsigned int cpu;
|
|
|
|
|
|
|
|
lockdep_assert_cpus_held();
|
|
|
|
|
|
|
|
for_each_online_cpu(cpu)
|
|
|
|
cacheinfo_cpu_online(cpu);
|
|
|
|
}
|
|
|
|
|
2014-02-26 12:02:18 +08:00
|
|
|
#endif /* (CONFIG_PPC_PSERIES && CONFIG_SUSPEND) || CONFIG_HOTPLUG_CPU */
|