2012-02-17 08:51:31 +08:00
|
|
|
/*
|
|
|
|
|
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
2011-07-18 18:21:23 +08:00
|
|
|
* http://www.samsung.com/
|
|
|
|
|
*
|
2012-02-17 08:51:31 +08:00
|
|
|
* EXYNOS - CPU PMU(Power Management Unit) support
|
2011-07-18 18:21:23 +08:00
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <linux/io.h>
|
|
|
|
|
#include <linux/kernel.h>
|
2012-02-17 11:23:51 +08:00
|
|
|
#include <linux/bug.h>
|
2011-07-18 18:21:23 +08:00
|
|
|
|
|
|
|
|
#include <mach/regs-clock.h>
|
|
|
|
|
#include <mach/pmu.h>
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
static struct exynos_pmu_conf *exynos_pmu_config;
|
2011-07-18 18:21:23 +08:00
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
static struct exynos_pmu_conf exynos4210_pmu_config[] = {
|
2011-09-27 06:22:11 +08:00
|
|
|
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
|
|
|
|
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
|
|
|
|
|
{ S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
|
|
|
|
|
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
|
|
|
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
|
|
|
|
|
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
|
|
|
|
|
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ PMU_TABLE_END,},
|
2011-07-18 18:21:23 +08:00
|
|
|
};
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
|
2011-09-27 06:26:04 +08:00
|
|
|
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
|
|
|
|
|
/* XXX_OPTION register should be set other field */
|
|
|
|
|
{ S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
|
|
|
|
|
{ S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
|
|
|
{ S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
|
|
|
{ S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
|
|
|
{ S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
|
|
|
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
|
|
|
|
|
{ S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
|
|
|
{ S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
|
|
|
|
|
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
|
|
|
{ S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
|
|
|
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
|
|
|
{ S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
|
|
|
{ S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
|
|
|
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
|
|
|
|
|
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
|
|
|
{ PMU_TABLE_END,},
|
|
|
|
|
};
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
static struct exynos_pmu_conf exynos4412_pmu_config[] = {
|
2012-05-14 23:20:09 +08:00
|
|
|
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
|
|
|
|
|
{ PMU_TABLE_END,},
|
|
|
|
|
};
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
static struct exynos_pmu_conf exynos5250_pmu_config[] = {
|
|
|
|
|
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
|
|
|
|
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
|
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
|
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
|
|
|
{ EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
|
|
|
{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
|
|
|
|
|
{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
|
|
|
{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
|
|
|
{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
|
|
|
{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
|
|
|
{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
|
|
|
{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
|
|
|
{ EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
|
|
|
{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
|
|
|
{ EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
|
|
|
{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
|
|
|
{ PMU_TABLE_END,},
|
|
|
|
|
};
|
|
|
|
|
|
2012-07-12 15:49:10 +08:00
|
|
|
static void __iomem *exynos5_list_both_cnt_feed[] = {
|
2012-02-17 11:23:51 +08:00
|
|
|
EXYNOS5_ARM_CORE0_OPTION,
|
|
|
|
|
EXYNOS5_ARM_CORE1_OPTION,
|
|
|
|
|
EXYNOS5_ARM_COMMON_OPTION,
|
|
|
|
|
EXYNOS5_GSCL_OPTION,
|
|
|
|
|
EXYNOS5_ISP_OPTION,
|
|
|
|
|
EXYNOS5_MFC_OPTION,
|
|
|
|
|
EXYNOS5_G3D_OPTION,
|
|
|
|
|
EXYNOS5_DISP1_OPTION,
|
|
|
|
|
EXYNOS5_MAU_OPTION,
|
|
|
|
|
EXYNOS5_TOP_PWR_OPTION,
|
|
|
|
|
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
|
|
|
|
|
};
|
|
|
|
|
|
2012-07-12 15:49:10 +08:00
|
|
|
static void __iomem *exynos5_list_diable_wfi_wfe[] = {
|
2012-02-17 11:23:51 +08:00
|
|
|
EXYNOS5_ARM_CORE1_OPTION,
|
|
|
|
|
EXYNOS5_FSYS_ARM_OPTION,
|
|
|
|
|
EXYNOS5_ISP_ARM_OPTION,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void exynos5_init_pmu(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
unsigned int tmp;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Enable both SC_FEEDBACK and SC_COUNTER
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
|
|
|
|
|
tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
|
|
|
|
|
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
|
|
|
|
|
EXYNOS5_USE_SC_COUNTER);
|
|
|
|
|
__raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
|
|
|
|
|
* MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
|
|
|
|
|
*/
|
|
|
|
|
tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
|
|
|
|
|
tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
|
|
|
|
|
EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
|
|
|
|
|
__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Disable WFI/WFE on XXX_OPTION
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
|
|
|
|
|
tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
|
|
|
|
|
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
|
|
|
|
|
EXYNOS5_OPTION_USE_STANDBYWFI);
|
|
|
|
|
__raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
void exynos_sys_powerdown_conf(enum sys_powerdown mode)
|
2011-07-18 18:21:23 +08:00
|
|
|
{
|
2011-09-27 06:22:11 +08:00
|
|
|
unsigned int i;
|
|
|
|
|
|
2012-02-17 11:23:51 +08:00
|
|
|
if (soc_is_exynos5250())
|
|
|
|
|
exynos5_init_pmu();
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
|
|
|
|
|
__raw_writel(exynos_pmu_config[i].val[mode],
|
|
|
|
|
exynos_pmu_config[i].reg);
|
2012-05-14 23:20:09 +08:00
|
|
|
|
|
|
|
|
if (soc_is_exynos4412()) {
|
|
|
|
|
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
|
|
|
|
|
__raw_writel(exynos4412_pmu_config[i].val[mode],
|
|
|
|
|
exynos4412_pmu_config[i].reg);
|
|
|
|
|
}
|
2011-09-27 06:22:11 +08:00
|
|
|
}
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
static int __init exynos_pmu_init(void)
|
2011-09-27 06:22:11 +08:00
|
|
|
{
|
2012-06-27 08:47:35 +08:00
|
|
|
unsigned int value;
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
exynos_pmu_config = exynos4210_pmu_config;
|
2011-09-27 06:22:11 +08:00
|
|
|
|
2011-09-27 06:26:04 +08:00
|
|
|
if (soc_is_exynos4210()) {
|
2012-02-17 08:51:31 +08:00
|
|
|
exynos_pmu_config = exynos4210_pmu_config;
|
2011-09-27 06:26:04 +08:00
|
|
|
pr_info("EXYNOS4210 PMU Initialize\n");
|
2012-05-14 23:20:09 +08:00
|
|
|
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
2012-02-17 08:51:31 +08:00
|
|
|
exynos_pmu_config = exynos4x12_pmu_config;
|
2012-05-14 23:20:09 +08:00
|
|
|
pr_info("EXYNOS4x12 PMU Initialize\n");
|
2012-02-17 08:51:31 +08:00
|
|
|
} else if (soc_is_exynos5250()) {
|
2012-06-27 08:47:35 +08:00
|
|
|
/*
|
|
|
|
|
* When SYS_WDTRESET is set, watchdog timer reset request
|
|
|
|
|
* is ignored by power management unit.
|
|
|
|
|
*/
|
|
|
|
|
value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
|
|
|
|
|
value &= ~EXYNOS5_SYS_WDTRESET;
|
|
|
|
|
__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
|
|
|
|
|
|
|
|
|
|
value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
|
|
|
|
|
value &= ~EXYNOS5_SYS_WDTRESET;
|
|
|
|
|
__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
|
|
|
|
|
|
2012-02-17 08:51:31 +08:00
|
|
|
exynos_pmu_config = exynos5250_pmu_config;
|
|
|
|
|
pr_info("EXYNOS5250 PMU Initialize\n");
|
2011-09-27 06:26:04 +08:00
|
|
|
} else {
|
2012-02-17 08:51:31 +08:00
|
|
|
pr_info("EXYNOS: PMU not supported\n");
|
2011-09-27 06:26:04 +08:00
|
|
|
}
|
2011-07-18 18:21:23 +08:00
|
|
|
|
2011-09-27 06:22:11 +08:00
|
|
|
return 0;
|
2011-07-18 18:21:23 +08:00
|
|
|
}
|
2012-02-17 08:51:31 +08:00
|
|
|
arch_initcall(exynos_pmu_init);
|
