2014-03-01 07:41:22 +08:00
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/*
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*
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* Implementation of primary alsa driver code base for Intel HD Audio.
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*
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* Copyright(c) 2004 Intel Corporation. All rights reserved.
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*
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* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
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* PeiSen Hou <pshou@realtek.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/initval.h>
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#include "hda_priv.h"
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#include "hda_controller.h"
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#define CREATE_TRACE_POINTS
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#include "hda_intel_trace.h"
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2014-03-01 07:41:24 +08:00
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/* DSP lock helpers */
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#ifdef CONFIG_SND_HDA_DSP_LOADER
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#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
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#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
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#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
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#define dsp_is_locked(dev) ((dev)->locked)
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#else
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#define dsp_lock_init(dev) do {} while (0)
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#define dsp_lock(dev) do {} while (0)
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#define dsp_unlock(dev) do {} while (0)
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#define dsp_is_locked(dev) 0
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#endif
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2014-03-01 07:41:22 +08:00
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/*
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* AZX stream operations.
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*/
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/* start a stream */
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2014-03-01 07:41:24 +08:00
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static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
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2014-03-01 07:41:22 +08:00
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{
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/*
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* Before stream start, initialize parameter
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*/
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azx_dev->insufficient = 1;
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/* enable SIE */
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azx_writel(chip, INTCTL,
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azx_readl(chip, INTCTL) | (1 << azx_dev->index));
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/* set DMA start and interrupt mask */
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) |
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SD_CTL_DMA_START | SD_INT_MASK);
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}
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/* stop DMA */
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static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
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{
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) &
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~(SD_CTL_DMA_START | SD_INT_MASK));
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
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}
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/* stop a stream */
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void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
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{
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azx_stream_clear(chip, azx_dev);
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/* disable SIE */
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azx_writel(chip, INTCTL,
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azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
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}
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EXPORT_SYMBOL_GPL(azx_stream_stop);
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/* reset stream */
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2014-03-01 07:41:24 +08:00
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static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
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2014-03-01 07:41:22 +08:00
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{
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unsigned char val;
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int timeout;
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azx_stream_clear(chip, azx_dev);
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) |
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SD_CTL_STREAM_RESET);
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udelay(3);
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timeout = 300;
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while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
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SD_CTL_STREAM_RESET) && --timeout)
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;
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val &= ~SD_CTL_STREAM_RESET;
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azx_sd_writeb(chip, azx_dev, SD_CTL, val);
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udelay(3);
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timeout = 300;
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/* waiting for hardware to report that the stream is out of reset */
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while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
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SD_CTL_STREAM_RESET) && --timeout)
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;
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/* reset first position - may not be synced with hw at this time */
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*azx_dev->posbuf = 0;
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}
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/*
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* set up the SD for streaming
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*/
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2014-03-01 07:41:24 +08:00
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static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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2014-03-01 07:41:22 +08:00
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{
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unsigned int val;
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/* make sure the run bit is zero for SD */
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azx_stream_clear(chip, azx_dev);
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/* program the stream_tag */
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val = azx_sd_readl(chip, azx_dev, SD_CTL);
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val = (val & ~SD_CTL_STREAM_TAG_MASK) |
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(azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
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if (!azx_snoop(chip))
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val |= SD_CTL_TRAFFIC_PRIO;
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azx_sd_writel(chip, azx_dev, SD_CTL, val);
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/* program the length of samples in cyclic buffer */
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azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
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/* program the stream format */
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/* this value needs to be the same as the one programmed */
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azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
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/* program the stream LVI (last valid index) of the BDL */
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azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
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/* program the BDL address */
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/* lower BDL address */
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azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
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/* upper BDL address */
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azx_sd_writel(chip, azx_dev, SD_BDLPU,
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upper_32_bits(azx_dev->bdl.addr));
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/* enable the position buffer */
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if (chip->position_fix[0] != POS_FIX_LPIB ||
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chip->position_fix[1] != POS_FIX_LPIB) {
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if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
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azx_writel(chip, DPLBASE,
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(u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
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}
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/* set the interrupt enable bits in the descriptor control register */
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azx_sd_writel(chip, azx_dev, SD_CTL,
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azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
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return 0;
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}
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/* assign a stream for the PCM */
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static inline struct azx_dev *
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azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
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{
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int dev, i, nums;
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struct azx_dev *res = NULL;
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/* make a non-zero unique key for the substream */
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int key = (substream->pcm->device << 16) | (substream->number << 2) |
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(substream->stream + 1);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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dev = chip->playback_index_offset;
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nums = chip->playback_streams;
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} else {
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dev = chip->capture_index_offset;
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nums = chip->capture_streams;
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}
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for (i = 0; i < nums; i++, dev++) {
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struct azx_dev *azx_dev = &chip->azx_dev[dev];
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dsp_lock(azx_dev);
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if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
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res = azx_dev;
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if (res->assigned_key == key) {
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res->opened = 1;
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res->assigned_key = key;
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dsp_unlock(azx_dev);
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return azx_dev;
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}
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}
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dsp_unlock(azx_dev);
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}
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if (res) {
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dsp_lock(res);
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res->opened = 1;
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res->assigned_key = key;
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dsp_unlock(res);
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}
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return res;
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}
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/* release the assigned stream */
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static inline void azx_release_device(struct azx_dev *azx_dev)
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{
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azx_dev->opened = 0;
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}
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static cycle_t azx_cc_read(const struct cyclecounter *cc)
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{
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struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
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struct snd_pcm_substream *substream = azx_dev->substream;
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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struct azx *chip = apcm->chip;
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return azx_readl(chip, WALLCLK);
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}
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static void azx_timecounter_init(struct snd_pcm_substream *substream,
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bool force, cycle_t last)
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{
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struct azx_dev *azx_dev = get_azx_dev(substream);
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struct timecounter *tc = &azx_dev->azx_tc;
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struct cyclecounter *cc = &azx_dev->azx_cc;
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u64 nsec;
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cc->read = azx_cc_read;
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cc->mask = CLOCKSOURCE_MASK(32);
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/*
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* Converting from 24 MHz to ns means applying a 125/3 factor.
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* To avoid any saturation issues in intermediate operations,
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* the 125 factor is applied first. The division is applied
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* last after reading the timecounter value.
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* Applying the 1/3 factor as part of the multiplication
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* requires at least 20 bits for a decent precision, however
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* overflows occur after about 4 hours or less, not a option.
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*/
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cc->mult = 125; /* saturation after 195 years */
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cc->shift = 0;
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nsec = 0; /* audio time is elapsed time since trigger */
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timecounter_init(tc, cc, nsec);
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if (force)
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/*
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* force timecounter to use predefined value,
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* used for synchronized starts
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*/
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tc->cycle_last = last;
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}
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static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
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u64 nsec)
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{
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
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u64 codec_frames, codec_nsecs;
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if (!hinfo->ops.get_delay)
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return nsec;
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codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
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codec_nsecs = div_u64(codec_frames * 1000000000LL,
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substream->runtime->rate);
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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return nsec + codec_nsecs;
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return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
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}
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/*
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* set up a BDL entry
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*/
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2014-03-01 07:41:24 +08:00
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static int setup_bdle(struct azx *chip,
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struct snd_dma_buffer *dmab,
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struct azx_dev *azx_dev, u32 **bdlp,
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int ofs, int size, int with_ioc)
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2014-03-01 07:41:22 +08:00
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{
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u32 *bdl = *bdlp;
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while (size > 0) {
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dma_addr_t addr;
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int chunk;
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if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
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return -EINVAL;
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addr = snd_sgbuf_get_addr(dmab, ofs);
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/* program the address field of the BDL entry */
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bdl[0] = cpu_to_le32((u32)addr);
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bdl[1] = cpu_to_le32(upper_32_bits(addr));
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/* program the size field of the BDL entry */
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chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
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/* one BDLE cannot cross 4K boundary on CTHDA chips */
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if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
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u32 remain = 0x1000 - (ofs & 0xfff);
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if (chunk > remain)
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chunk = remain;
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}
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bdl[2] = cpu_to_le32(chunk);
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/* program the IOC to enable interrupt
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* only when the whole fragment is processed
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*/
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size -= chunk;
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bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
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bdl += 4;
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azx_dev->frags++;
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ofs += chunk;
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}
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*bdlp = bdl;
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return ofs;
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}
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/*
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* set up BDL entries
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*/
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static int azx_setup_periods(struct azx *chip,
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struct snd_pcm_substream *substream,
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struct azx_dev *azx_dev)
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{
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u32 *bdl;
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int i, ofs, periods, period_bytes;
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int pos_adj = 0;
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/* reset BDL address */
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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period_bytes = azx_dev->period_bytes;
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periods = azx_dev->bufsize / period_bytes;
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/* program the initial BDL entries */
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bdl = (u32 *)azx_dev->bdl.area;
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ofs = 0;
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azx_dev->frags = 0;
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if (chip->bdl_pos_adj)
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pos_adj = chip->bdl_pos_adj[chip->dev_index];
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if (!azx_dev->no_period_wakeup && pos_adj > 0) {
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struct snd_pcm_runtime *runtime = substream->runtime;
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|
|
int pos_align = pos_adj;
|
|
|
|
pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
|
|
|
|
if (!pos_adj)
|
|
|
|
pos_adj = pos_align;
|
|
|
|
else
|
|
|
|
pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
|
|
|
|
pos_align;
|
|
|
|
pos_adj = frames_to_bytes(runtime, pos_adj);
|
|
|
|
if (pos_adj >= period_bytes) {
|
|
|
|
dev_warn(chip->card->dev,"Too big adjustment %d\n",
|
|
|
|
pos_adj);
|
|
|
|
pos_adj = 0;
|
|
|
|
} else {
|
|
|
|
ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
|
|
|
|
azx_dev,
|
|
|
|
&bdl, ofs, pos_adj, true);
|
|
|
|
if (ofs < 0)
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
pos_adj = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < periods; i++) {
|
|
|
|
if (i == periods - 1 && pos_adj)
|
|
|
|
ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
|
|
|
|
azx_dev, &bdl, ofs,
|
|
|
|
period_bytes - pos_adj, 0);
|
|
|
|
else
|
|
|
|
ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
|
|
|
|
azx_dev, &bdl, ofs,
|
|
|
|
period_bytes,
|
|
|
|
!azx_dev->no_period_wakeup);
|
|
|
|
if (ofs < 0)
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
|
|
|
dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
|
|
|
|
azx_dev->bufsize, period_bytes);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PCM ops
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int azx_pcm_close(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
struct azx_dev *azx_dev = get_azx_dev(substream);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
mutex_lock(&chip->open_mutex);
|
|
|
|
spin_lock_irqsave(&chip->reg_lock, flags);
|
|
|
|
azx_dev->substream = NULL;
|
|
|
|
azx_dev->running = 0;
|
|
|
|
spin_unlock_irqrestore(&chip->reg_lock, flags);
|
|
|
|
azx_release_device(azx_dev);
|
|
|
|
hinfo->ops.close(hinfo, apcm->codec, substream);
|
|
|
|
snd_hda_power_down(apcm->codec);
|
|
|
|
mutex_unlock(&chip->open_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *hw_params)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dsp_lock(get_azx_dev(substream));
|
|
|
|
if (dsp_is_locked(get_azx_dev(substream))) {
|
|
|
|
ret = -EBUSY;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = chip->ops->substream_alloc_pages(chip, substream,
|
|
|
|
params_buffer_bytes(hw_params));
|
|
|
|
unlock:
|
|
|
|
dsp_unlock(get_azx_dev(substream));
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct azx_dev *azx_dev = get_azx_dev(substream);
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/* reset BDL address */
|
|
|
|
dsp_lock(azx_dev);
|
|
|
|
if (!dsp_is_locked(azx_dev)) {
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_CTL, 0);
|
|
|
|
azx_dev->bufsize = 0;
|
|
|
|
azx_dev->period_bytes = 0;
|
|
|
|
azx_dev->format_val = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
|
|
|
|
|
|
|
|
err = chip->ops->substream_free_pages(chip, substream);
|
|
|
|
azx_dev->prepared = 0;
|
|
|
|
dsp_unlock(azx_dev);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int azx_pcm_prepare(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
struct azx_dev *azx_dev = get_azx_dev(substream);
|
|
|
|
struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
|
|
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
|
|
unsigned int bufsize, period_bytes, format_val, stream_tag;
|
|
|
|
int err;
|
|
|
|
struct hda_spdif_out *spdif =
|
|
|
|
snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
|
|
|
|
unsigned short ctls = spdif ? spdif->ctls : 0;
|
|
|
|
|
|
|
|
dsp_lock(azx_dev);
|
|
|
|
if (dsp_is_locked(azx_dev)) {
|
|
|
|
err = -EBUSY;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
|
|
|
azx_stream_reset(chip, azx_dev);
|
|
|
|
format_val = snd_hda_calc_stream_format(runtime->rate,
|
|
|
|
runtime->channels,
|
|
|
|
runtime->format,
|
|
|
|
hinfo->maxbps,
|
|
|
|
ctls);
|
|
|
|
if (!format_val) {
|
|
|
|
dev_err(chip->card->dev,
|
|
|
|
"invalid format_val, rate=%d, ch=%d, format=%d\n",
|
|
|
|
runtime->rate, runtime->channels, runtime->format);
|
|
|
|
err = -EINVAL;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
|
|
|
bufsize = snd_pcm_lib_buffer_bytes(substream);
|
|
|
|
period_bytes = snd_pcm_lib_period_bytes(substream);
|
|
|
|
|
|
|
|
dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
|
|
|
|
bufsize, format_val);
|
|
|
|
|
|
|
|
if (bufsize != azx_dev->bufsize ||
|
|
|
|
period_bytes != azx_dev->period_bytes ||
|
|
|
|
format_val != azx_dev->format_val ||
|
|
|
|
runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
|
|
|
|
azx_dev->bufsize = bufsize;
|
|
|
|
azx_dev->period_bytes = period_bytes;
|
|
|
|
azx_dev->format_val = format_val;
|
|
|
|
azx_dev->no_period_wakeup = runtime->no_period_wakeup;
|
|
|
|
err = azx_setup_periods(chip, substream, azx_dev);
|
|
|
|
if (err < 0)
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* when LPIB delay correction gives a small negative value,
|
|
|
|
* we ignore it; currently set the threshold statically to
|
|
|
|
* 64 frames
|
|
|
|
*/
|
|
|
|
if (runtime->period_size > 64)
|
|
|
|
azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
|
|
|
|
else
|
|
|
|
azx_dev->delay_negative_threshold = 0;
|
|
|
|
|
|
|
|
/* wallclk has 24Mhz clock source */
|
|
|
|
azx_dev->period_wallclk = (((runtime->period_size * 24000) /
|
|
|
|
runtime->rate) * 1000);
|
|
|
|
azx_setup_controller(chip, azx_dev);
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
azx_dev->fifo_size =
|
|
|
|
azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
|
|
|
|
else
|
|
|
|
azx_dev->fifo_size = 0;
|
|
|
|
|
|
|
|
stream_tag = azx_dev->stream_tag;
|
|
|
|
/* CA-IBG chips need the playback stream starting from 1 */
|
|
|
|
if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
|
|
|
|
stream_tag > chip->capture_streams)
|
|
|
|
stream_tag -= chip->capture_streams;
|
|
|
|
err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
|
|
|
|
azx_dev->format_val, substream);
|
|
|
|
|
|
|
|
unlock:
|
|
|
|
if (!err)
|
|
|
|
azx_dev->prepared = 1;
|
|
|
|
dsp_unlock(azx_dev);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
struct azx_dev *azx_dev;
|
|
|
|
struct snd_pcm_substream *s;
|
|
|
|
int rstart = 0, start, nsync = 0, sbits = 0;
|
|
|
|
int nwait, timeout;
|
|
|
|
|
|
|
|
azx_dev = get_azx_dev(substream);
|
|
|
|
trace_azx_pcm_trigger(chip, azx_dev, cmd);
|
|
|
|
|
|
|
|
if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
|
|
|
|
return -EPIPE;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
rstart = 1;
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
start = 1;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
start = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
|
continue;
|
|
|
|
azx_dev = get_azx_dev(s);
|
|
|
|
sbits |= 1 << azx_dev->index;
|
|
|
|
nsync++;
|
|
|
|
snd_pcm_trigger_done(s, substream);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock(&chip->reg_lock);
|
|
|
|
|
|
|
|
/* first, set SYNC bits of corresponding streams */
|
|
|
|
if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
|
|
|
|
azx_writel(chip, OLD_SSYNC,
|
|
|
|
azx_readl(chip, OLD_SSYNC) | sbits);
|
|
|
|
else
|
|
|
|
azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
|
|
|
|
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
|
continue;
|
|
|
|
azx_dev = get_azx_dev(s);
|
|
|
|
if (start) {
|
|
|
|
azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
|
|
|
|
if (!rstart)
|
|
|
|
azx_dev->start_wallclk -=
|
|
|
|
azx_dev->period_wallclk;
|
|
|
|
azx_stream_start(chip, azx_dev);
|
|
|
|
} else {
|
|
|
|
azx_stream_stop(chip, azx_dev);
|
|
|
|
}
|
|
|
|
azx_dev->running = start;
|
|
|
|
}
|
|
|
|
spin_unlock(&chip->reg_lock);
|
|
|
|
if (start) {
|
|
|
|
/* wait until all FIFOs get ready */
|
|
|
|
for (timeout = 5000; timeout; timeout--) {
|
|
|
|
nwait = 0;
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
|
continue;
|
|
|
|
azx_dev = get_azx_dev(s);
|
|
|
|
if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
|
|
|
|
SD_STS_FIFO_READY))
|
|
|
|
nwait++;
|
|
|
|
}
|
|
|
|
if (!nwait)
|
|
|
|
break;
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* wait until all RUN bits are cleared */
|
|
|
|
for (timeout = 5000; timeout; timeout--) {
|
|
|
|
nwait = 0;
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
|
continue;
|
|
|
|
azx_dev = get_azx_dev(s);
|
|
|
|
if (azx_sd_readb(chip, azx_dev, SD_CTL) &
|
|
|
|
SD_CTL_DMA_START)
|
|
|
|
nwait++;
|
|
|
|
}
|
|
|
|
if (!nwait)
|
|
|
|
break;
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_lock(&chip->reg_lock);
|
|
|
|
/* reset SYNC bits */
|
|
|
|
if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
|
|
|
|
azx_writel(chip, OLD_SSYNC,
|
|
|
|
azx_readl(chip, OLD_SSYNC) & ~sbits);
|
|
|
|
else
|
|
|
|
azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
|
|
|
|
if (start) {
|
|
|
|
azx_timecounter_init(substream, 0, 0);
|
|
|
|
if (nsync > 1) {
|
|
|
|
cycle_t cycle_last;
|
|
|
|
|
|
|
|
/* same start cycle for master and group */
|
|
|
|
azx_dev = get_azx_dev(substream);
|
|
|
|
cycle_last = azx_dev->azx_tc.cycle_last;
|
|
|
|
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
|
continue;
|
|
|
|
azx_timecounter_init(s, 1, cycle_last);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock(&chip->reg_lock);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* get the current DMA position with correction on VIA chips */
|
|
|
|
static unsigned int azx_via_get_position(struct azx *chip,
|
|
|
|
struct azx_dev *azx_dev)
|
|
|
|
{
|
|
|
|
unsigned int link_pos, mini_pos, bound_pos;
|
|
|
|
unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
|
|
|
|
unsigned int fifo_size;
|
|
|
|
|
|
|
|
link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
|
|
|
|
if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
/* Playback, no problem using link position */
|
|
|
|
return link_pos;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Capture */
|
|
|
|
/* For new chipset,
|
|
|
|
* use mod to get the DMA position just like old chipset
|
|
|
|
*/
|
|
|
|
mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
|
|
|
|
mod_dma_pos %= azx_dev->period_bytes;
|
|
|
|
|
|
|
|
/* azx_dev->fifo_size can't get FIFO size of in stream.
|
|
|
|
* Get from base address + offset.
|
|
|
|
*/
|
|
|
|
fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
|
|
|
|
|
|
|
|
if (azx_dev->insufficient) {
|
|
|
|
/* Link position never gather than FIFO size */
|
|
|
|
if (link_pos <= fifo_size)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
azx_dev->insufficient = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (link_pos <= fifo_size)
|
|
|
|
mini_pos = azx_dev->bufsize + link_pos - fifo_size;
|
|
|
|
else
|
|
|
|
mini_pos = link_pos - fifo_size;
|
|
|
|
|
|
|
|
/* Find nearest previous boudary */
|
|
|
|
mod_mini_pos = mini_pos % azx_dev->period_bytes;
|
|
|
|
mod_link_pos = link_pos % azx_dev->period_bytes;
|
|
|
|
if (mod_link_pos >= fifo_size)
|
|
|
|
bound_pos = link_pos - mod_link_pos;
|
|
|
|
else if (mod_dma_pos >= mod_mini_pos)
|
|
|
|
bound_pos = mini_pos - mod_mini_pos;
|
|
|
|
else {
|
|
|
|
bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
|
|
|
|
if (bound_pos >= azx_dev->bufsize)
|
|
|
|
bound_pos = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Calculate real DMA position we want */
|
|
|
|
return bound_pos + mod_dma_pos;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int azx_get_position(struct azx *chip,
|
|
|
|
struct azx_dev *azx_dev,
|
|
|
|
bool with_check)
|
|
|
|
{
|
|
|
|
struct snd_pcm_substream *substream = azx_dev->substream;
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
unsigned int pos;
|
|
|
|
int stream = substream->stream;
|
|
|
|
struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
|
|
|
|
int delay = 0;
|
|
|
|
|
|
|
|
switch (chip->position_fix[stream]) {
|
|
|
|
case POS_FIX_LPIB:
|
|
|
|
/* read LPIB */
|
|
|
|
pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
|
|
|
|
break;
|
|
|
|
case POS_FIX_VIACOMBO:
|
|
|
|
pos = azx_via_get_position(chip, azx_dev);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* use the position buffer */
|
|
|
|
pos = le32_to_cpu(*azx_dev->posbuf);
|
|
|
|
if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
|
|
|
|
if (!pos || pos == (u32)-1) {
|
|
|
|
dev_info(chip->card->dev,
|
|
|
|
"Invalid position buffer, using LPIB read method instead.\n");
|
|
|
|
chip->position_fix[stream] = POS_FIX_LPIB;
|
|
|
|
pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
|
|
|
|
} else
|
|
|
|
chip->position_fix[stream] = POS_FIX_POSBUF;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pos >= azx_dev->bufsize)
|
|
|
|
pos = 0;
|
|
|
|
|
|
|
|
/* calculate runtime delay from LPIB */
|
|
|
|
if (substream->runtime &&
|
|
|
|
chip->position_fix[stream] == POS_FIX_POSBUF &&
|
|
|
|
(chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
|
|
|
|
unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
|
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
delay = pos - lpib_pos;
|
|
|
|
else
|
|
|
|
delay = lpib_pos - pos;
|
|
|
|
if (delay < 0) {
|
|
|
|
if (delay >= azx_dev->delay_negative_threshold)
|
|
|
|
delay = 0;
|
|
|
|
else
|
|
|
|
delay += azx_dev->bufsize;
|
|
|
|
}
|
|
|
|
if (delay >= azx_dev->period_bytes) {
|
|
|
|
dev_info(chip->card->dev,
|
|
|
|
"Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
|
|
|
|
delay, azx_dev->period_bytes);
|
|
|
|
delay = 0;
|
|
|
|
chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
|
|
|
|
}
|
|
|
|
delay = bytes_to_frames(substream->runtime, delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (substream->runtime) {
|
|
|
|
if (hinfo->ops.get_delay)
|
|
|
|
delay += hinfo->ops.get_delay(hinfo, apcm->codec,
|
|
|
|
substream);
|
|
|
|
substream->runtime->delay = delay;
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_azx_get_position(chip, azx_dev, pos, delay);
|
|
|
|
return pos;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(azx_get_position);
|
|
|
|
|
|
|
|
static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
struct azx_dev *azx_dev = get_azx_dev(substream);
|
|
|
|
return bytes_to_frames(substream->runtime,
|
|
|
|
azx_get_position(chip, azx_dev, false));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
|
|
|
|
struct timespec *ts)
|
|
|
|
{
|
|
|
|
struct azx_dev *azx_dev = get_azx_dev(substream);
|
|
|
|
u64 nsec;
|
|
|
|
|
|
|
|
nsec = timecounter_read(&azx_dev->azx_tc);
|
|
|
|
nsec = div_u64(nsec, 3); /* can be optimized */
|
|
|
|
nsec = azx_adjust_codec_delay(substream, nsec);
|
|
|
|
|
|
|
|
*ts = ns_to_timespec(nsec);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_pcm_hardware azx_pcm_hw = {
|
|
|
|
.info = (SNDRV_PCM_INFO_MMAP |
|
|
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
|
|
|
SNDRV_PCM_INFO_BLOCK_TRANSFER |
|
|
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
|
|
|
/* No full-resume yet implemented */
|
|
|
|
/* SNDRV_PCM_INFO_RESUME |*/
|
|
|
|
SNDRV_PCM_INFO_PAUSE |
|
|
|
|
SNDRV_PCM_INFO_SYNC_START |
|
|
|
|
SNDRV_PCM_INFO_HAS_WALL_CLOCK |
|
|
|
|
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.rate_min = 48000,
|
|
|
|
.rate_max = 48000,
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.buffer_bytes_max = AZX_MAX_BUF_SIZE,
|
|
|
|
.period_bytes_min = 128,
|
|
|
|
.period_bytes_max = AZX_MAX_BUF_SIZE / 2,
|
|
|
|
.periods_min = 2,
|
|
|
|
.periods_max = AZX_MAX_FRAG,
|
|
|
|
.fifo_size = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int azx_pcm_open(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
struct azx_dev *azx_dev;
|
|
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
|
|
unsigned long flags;
|
|
|
|
int err;
|
|
|
|
int buff_step;
|
|
|
|
|
|
|
|
mutex_lock(&chip->open_mutex);
|
|
|
|
azx_dev = azx_assign_device(chip, substream);
|
|
|
|
if (azx_dev == NULL) {
|
|
|
|
mutex_unlock(&chip->open_mutex);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
runtime->hw = azx_pcm_hw;
|
|
|
|
runtime->hw.channels_min = hinfo->channels_min;
|
|
|
|
runtime->hw.channels_max = hinfo->channels_max;
|
|
|
|
runtime->hw.formats = hinfo->formats;
|
|
|
|
runtime->hw.rates = hinfo->rates;
|
|
|
|
snd_pcm_limit_hw_rates(runtime);
|
|
|
|
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
|
|
|
|
|
|
|
|
/* avoid wrap-around with wall-clock */
|
|
|
|
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
|
|
|
|
20,
|
|
|
|
178000000);
|
|
|
|
|
|
|
|
if (chip->align_buffer_size)
|
|
|
|
/* constrain buffer sizes to be multiple of 128
|
|
|
|
bytes. This is more efficient in terms of memory
|
|
|
|
access but isn't required by the HDA spec and
|
|
|
|
prevents users from specifying exact period/buffer
|
|
|
|
sizes. For example for 44.1kHz, a period size set
|
|
|
|
to 20ms will be rounded to 19.59ms. */
|
|
|
|
buff_step = 128;
|
|
|
|
else
|
|
|
|
/* Don't enforce steps on buffer sizes, still need to
|
|
|
|
be multiple of 4 bytes (HDA spec). Tested on Intel
|
|
|
|
HDA controllers, may not work on all devices where
|
|
|
|
option needs to be disabled */
|
|
|
|
buff_step = 4;
|
|
|
|
|
|
|
|
snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
|
|
|
|
buff_step);
|
|
|
|
snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
|
|
|
|
buff_step);
|
|
|
|
snd_hda_power_up_d3wait(apcm->codec);
|
|
|
|
err = hinfo->ops.open(hinfo, apcm->codec, substream);
|
|
|
|
if (err < 0) {
|
|
|
|
azx_release_device(azx_dev);
|
|
|
|
snd_hda_power_down(apcm->codec);
|
|
|
|
mutex_unlock(&chip->open_mutex);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
snd_pcm_limit_hw_rates(runtime);
|
|
|
|
/* sanity check */
|
|
|
|
if (snd_BUG_ON(!runtime->hw.channels_min) ||
|
|
|
|
snd_BUG_ON(!runtime->hw.channels_max) ||
|
|
|
|
snd_BUG_ON(!runtime->hw.formats) ||
|
|
|
|
snd_BUG_ON(!runtime->hw.rates)) {
|
|
|
|
azx_release_device(azx_dev);
|
|
|
|
hinfo->ops.close(hinfo, apcm->codec, substream);
|
|
|
|
snd_hda_power_down(apcm->codec);
|
|
|
|
mutex_unlock(&chip->open_mutex);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* disable WALLCLOCK timestamps for capture streams
|
|
|
|
until we figure out how to handle digital inputs */
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
|
|
runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&chip->reg_lock, flags);
|
|
|
|
azx_dev->substream = substream;
|
|
|
|
azx_dev->running = 0;
|
|
|
|
spin_unlock_irqrestore(&chip->reg_lock, flags);
|
|
|
|
|
|
|
|
runtime->private_data = azx_dev;
|
|
|
|
snd_pcm_set_sync(substream);
|
|
|
|
mutex_unlock(&chip->open_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int azx_pcm_mmap(struct snd_pcm_substream *substream,
|
|
|
|
struct vm_area_struct *area)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
|
|
|
|
struct azx *chip = apcm->chip;
|
|
|
|
if (chip->ops->pcm_mmap_prepare)
|
|
|
|
chip->ops->pcm_mmap_prepare(substream, area);
|
|
|
|
return snd_pcm_lib_default_mmap(substream, area);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_pcm_ops azx_pcm_ops = {
|
|
|
|
.open = azx_pcm_open,
|
|
|
|
.close = azx_pcm_close,
|
|
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
|
|
.hw_params = azx_pcm_hw_params,
|
|
|
|
.hw_free = azx_pcm_hw_free,
|
|
|
|
.prepare = azx_pcm_prepare,
|
|
|
|
.trigger = azx_pcm_trigger,
|
|
|
|
.pointer = azx_pcm_pointer,
|
|
|
|
.wall_clock = azx_get_wallclock_tstamp,
|
|
|
|
.mmap = azx_pcm_mmap,
|
|
|
|
.page = snd_pcm_sgbuf_ops_page,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void azx_pcm_free(struct snd_pcm *pcm)
|
|
|
|
{
|
|
|
|
struct azx_pcm *apcm = pcm->private_data;
|
|
|
|
if (apcm) {
|
|
|
|
list_del(&apcm->list);
|
|
|
|
kfree(apcm);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
|
|
|
|
|
|
|
|
int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
|
|
|
|
struct hda_pcm *cpcm)
|
|
|
|
{
|
|
|
|
struct azx *chip = bus->private_data;
|
|
|
|
struct snd_pcm *pcm;
|
|
|
|
struct azx_pcm *apcm;
|
|
|
|
int pcm_dev = cpcm->device;
|
|
|
|
unsigned int size;
|
|
|
|
int s, err;
|
|
|
|
|
|
|
|
list_for_each_entry(apcm, &chip->pcm_list, list) {
|
|
|
|
if (apcm->pcm->device == pcm_dev) {
|
|
|
|
dev_err(chip->card->dev, "PCM %d already exists\n",
|
|
|
|
pcm_dev);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
|
|
|
|
cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
|
|
|
|
cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
|
|
|
|
&pcm);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
|
|
|
|
apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
|
|
|
|
if (apcm == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
apcm->chip = chip;
|
|
|
|
apcm->pcm = pcm;
|
|
|
|
apcm->codec = codec;
|
|
|
|
pcm->private_data = apcm;
|
|
|
|
pcm->private_free = azx_pcm_free;
|
|
|
|
if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
|
|
|
|
pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
|
|
|
|
list_add_tail(&apcm->list, &chip->pcm_list);
|
|
|
|
cpcm->pcm = pcm;
|
|
|
|
for (s = 0; s < 2; s++) {
|
|
|
|
apcm->hinfo[s] = &cpcm->stream[s];
|
|
|
|
if (cpcm->stream[s].substreams)
|
|
|
|
snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
|
|
|
|
}
|
|
|
|
/* buffer pre-allocation */
|
|
|
|
size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
|
|
|
|
if (size > MAX_PREALLOC_SIZE)
|
|
|
|
size = MAX_PREALLOC_SIZE;
|
|
|
|
snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
|
|
|
|
chip->card->dev,
|
|
|
|
size, MAX_PREALLOC_SIZE);
|
|
|
|
/* link to codec */
|
|
|
|
pcm->dev = &codec->dev;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(azx_attach_pcm_stream);
|
|
|
|
|
2014-03-01 07:41:24 +08:00
|
|
|
#ifdef CONFIG_SND_HDA_DSP_LOADER
|
|
|
|
/*
|
|
|
|
* DSP loading code (e.g. for CA0132)
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* use the first stream for loading DSP */
|
|
|
|
static struct azx_dev *
|
|
|
|
azx_get_dsp_loader_dev(struct azx *chip)
|
|
|
|
{
|
|
|
|
return &chip->azx_dev[chip->playback_index_offset];
|
|
|
|
}
|
|
|
|
|
|
|
|
int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|
|
|
unsigned int byte_size,
|
|
|
|
struct snd_dma_buffer *bufp)
|
|
|
|
{
|
|
|
|
u32 *bdl;
|
|
|
|
struct azx *chip = bus->private_data;
|
|
|
|
struct azx_dev *azx_dev;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
|
|
|
|
|
dsp_lock(azx_dev);
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
|
|
if (azx_dev->running || azx_dev->locked) {
|
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
|
err = -EBUSY;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
azx_dev->prepared = 0;
|
|
|
|
chip->saved_azx_dev = *azx_dev;
|
|
|
|
azx_dev->locked = 1;
|
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
|
|
|
|
|
err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
|
|
|
|
byte_size, bufp);
|
|
|
|
if (err < 0)
|
|
|
|
goto err_alloc;
|
|
|
|
|
|
|
|
azx_dev->bufsize = byte_size;
|
|
|
|
azx_dev->period_bytes = byte_size;
|
|
|
|
azx_dev->format_val = format;
|
|
|
|
|
|
|
|
azx_stream_reset(chip, azx_dev);
|
|
|
|
|
|
|
|
/* reset BDL address */
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
|
|
|
|
|
|
|
|
azx_dev->frags = 0;
|
|
|
|
bdl = (u32 *)azx_dev->bdl.area;
|
|
|
|
err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
|
|
|
|
if (err < 0)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
azx_setup_controller(chip, azx_dev);
|
|
|
|
dsp_unlock(azx_dev);
|
|
|
|
return azx_dev->stream_tag;
|
|
|
|
|
|
|
|
error:
|
|
|
|
chip->ops->dma_free_pages(chip, bufp);
|
|
|
|
err_alloc:
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
|
|
if (azx_dev->opened)
|
|
|
|
*azx_dev = chip->saved_azx_dev;
|
|
|
|
azx_dev->locked = 0;
|
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
|
unlock:
|
|
|
|
dsp_unlock(azx_dev);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(azx_load_dsp_prepare);
|
|
|
|
|
|
|
|
void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
|
|
|
|
{
|
|
|
|
struct azx *chip = bus->private_data;
|
|
|
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
|
|
|
|
|
if (start)
|
|
|
|
azx_stream_start(chip, azx_dev);
|
|
|
|
else
|
|
|
|
azx_stream_stop(chip, azx_dev);
|
|
|
|
azx_dev->running = start;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(azx_load_dsp_trigger);
|
|
|
|
|
|
|
|
void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|
|
|
struct snd_dma_buffer *dmab)
|
|
|
|
{
|
|
|
|
struct azx *chip = bus->private_data;
|
|
|
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
|
|
|
|
|
if (!dmab->area || !azx_dev->locked)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dsp_lock(azx_dev);
|
|
|
|
/* reset BDL address */
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
|
|
|
|
azx_sd_writel(chip, azx_dev, SD_CTL, 0);
|
|
|
|
azx_dev->bufsize = 0;
|
|
|
|
azx_dev->period_bytes = 0;
|
|
|
|
azx_dev->format_val = 0;
|
|
|
|
|
|
|
|
chip->ops->dma_free_pages(chip, dmab);
|
|
|
|
dmab->area = NULL;
|
|
|
|
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
|
|
if (azx_dev->opened)
|
|
|
|
*azx_dev = chip->saved_azx_dev;
|
|
|
|
azx_dev->locked = 0;
|
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
|
dsp_unlock(azx_dev);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(azx_load_dsp_cleanup);
|
|
|
|
#endif /* CONFIG_SND_HDA_DSP_LOADER */
|
|
|
|
|
2014-03-01 07:41:23 +08:00
|
|
|
int azx_alloc_stream_pages(struct azx *chip)
|
|
|
|
{
|
|
|
|
int i, err;
|
|
|
|
struct snd_card *card = chip->card;
|
|
|
|
|
|
|
|
for (i = 0; i < chip->num_streams; i++) {
|
|
|
|
dsp_lock_init(&chip->azx_dev[i]);
|
|
|
|
/* allocate memory for the BDL for each stream */
|
|
|
|
err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
|
|
|
|
BDL_SIZE,
|
|
|
|
&chip->azx_dev[i].bdl);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(card->dev, "cannot allocate BDL\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* allocate memory for the position buffer */
|
|
|
|
err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
|
|
|
|
chip->num_streams * 8, &chip->posbuf);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(card->dev, "cannot allocate posbuf\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(azx_alloc_stream_pages);
|
|
|
|
|
|
|
|
void azx_free_stream_pages(struct azx *chip)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
if (chip->azx_dev) {
|
|
|
|
for (i = 0; i < chip->num_streams; i++)
|
|
|
|
if (chip->azx_dev[i].bdl.area)
|
|
|
|
chip->ops->dma_free_pages(
|
|
|
|
chip, &chip->azx_dev[i].bdl);
|
|
|
|
}
|
|
|
|
if (chip->rb.area)
|
|
|
|
chip->ops->dma_free_pages(chip, &chip->rb);
|
|
|
|
if (chip->posbuf.area)
|
|
|
|
chip->ops->dma_free_pages(chip, &chip->posbuf);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(azx_free_stream_pages);
|
|
|
|
|
2014-03-01 07:41:22 +08:00
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DESCRIPTION("Common HDA driver funcitons");
|