48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
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#ifndef _ASM_POWERPC_PTE_HASH64_H
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#define _ASM_POWERPC_PTE_HASH64_H
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#ifdef __KERNEL__
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/*
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* Common bits between 4K and 64K pages in a linux-style PTE.
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* These match the bits in the (hardware-defined) PowerPC PTE as closely
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* as possible. Additional bits may be defined in pgtable-hash64-*.h
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*/
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#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
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#define _PAGE_USER 0x0002 /* matches one of the PP bits */
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#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
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#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
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#define _PAGE_GUARDED 0x0008
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#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
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#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
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#define _PAGE_DIRTY 0x0080 /* C: page changed */
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#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
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#define _PAGE_RW 0x0200 /* software: user write access allowed */
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#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
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/* Strong Access Ordering */
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#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
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#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
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#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
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/* PTEIDX nibble */
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#define _PTEIDX_SECONDARY 0x8
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#define _PTEIDX_GROUP_IX 0x7
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#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | \
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_PAGE_NO_CACHE | _PAGE_WRITETHRU | \
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_PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
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_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/pte-hash64-64k.h>
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#else
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#include <asm/pte-hash64-4k.h>
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_HASH64_H */
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