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OpenCloudOS-Kernel/arch/arm/mach-omap2/cm-regbits-44xx.h

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-04 16:11:33 +08:00
/* SPDX-License-Identifier: GPL-2.0-only */
ARM: OMAP4: PM: Adds CM1/2 register field masks This patch adds OMAP4 specific CM1 and CM2 module register field masks. Auto generated using a python script (gen_cm_shifts_and_mask.py) developed by Benoit Cousson, Paul Walmsley and Rajendra Nayak. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
2009-12-09 09:24:54 +08:00
/*
* OMAP44xx Clock Management register bits
*
ARM: OMAP4: cm: add bitfield width values The new common clk framework includes basic definitions for mux and divider clocks. These definitions depend on shift and width values instead of the pre-computed masks that the OMAP clk framework has traditionally used when accessing the register to control the mux or divisor. To ease this transition the masks are left intact and the width field is simply added alongside the shift and mask data. Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-09-20 08:04:14 +08:00
* Copyright (C) 2009-2012 Texas Instruments, Inc.
OMAP4: CM & PRM: Update PRCM register bitshifts and masks for ES2 This patch updates the PRM and CM register bitshifts and masks for OMAP4430 ES2.0. Replace as well the BITFIELD macro with the shift operator in order to be consistent with the previous OMAP2 & 3 format. Sort the register list in comments in order to have a consistent register order and avoid futur change during code generation. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
2010-09-28 04:02:55 +08:00
* Copyright (C) 2009-2010 Nokia Corporation
ARM: OMAP4: PM: Adds CM1/2 register field masks This patch adds OMAP4 specific CM1 and CM2 module register field masks. Auto generated using a python script (gen_cm_shifts_and_mask.py) developed by Benoit Cousson, Paul Walmsley and Rajendra Nayak. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
2009-12-09 09:24:54 +08:00
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
OMAP4: PRCM: Define shift macros as n instead of 1 << n The macros defining the shift bits in registers for various register bit fields are defined as 1 << n. Instead define them as n. They can then be used as val << n. The changes are generated by updating the script which autogenerates the files modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-27 11:13:12 +08:00
#define OMAP4430_ABE_STATDEP_SHIFT 3
#define OMAP4430_CLKTRCTRL_SHIFT 0
OMAP4: CM & PRM: Update PRCM register bitshifts and masks for ES2 This patch updates the PRM and CM register bitshifts and masks for OMAP4430 ES2.0. Replace as well the BITFIELD macro with the shift operator in order to be consistent with the previous OMAP2 & 3 format. Sort the register list in comments in order to have a consistent register order and avoid futur change during code generation. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
2010-09-28 04:02:55 +08:00
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
OMAP4: PRCM: Define shift macros as n instead of 1 << n The macros defining the shift bits in registers for various register bit fields are defined as 1 << n. Instead define them as n. They can then be used as val << n. The changes are generated by updating the script which autogenerates the files modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-27 11:13:12 +08:00
#define OMAP4430_DSS_STATDEP_SHIFT 8
#define OMAP4430_DUCATI_STATDEP_SHIFT 0
#define OMAP4430_GFX_STATDEP_SHIFT 10
#define OMAP4430_IDLEST_SHIFT 16
OMAP4: CM & PRM: Update PRCM register bitshifts and masks for ES2 This patch updates the PRM and CM register bitshifts and masks for OMAP4430 ES2.0. Replace as well the BITFIELD macro with the shift operator in order to be consistent with the previous OMAP2 & 3 format. Sort the register list in comments in order to have a consistent register order and avoid futur change during code generation. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
2010-09-28 04:02:55 +08:00
#define OMAP4430_IDLEST_MASK (0x3 << 16)
OMAP4: PRCM: Define shift macros as n instead of 1 << n The macros defining the shift bits in registers for various register bit fields are defined as 1 << n. Instead define them as n. They can then be used as val << n. The changes are generated by updating the script which autogenerates the files modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-27 11:13:12 +08:00
#define OMAP4430_IVAHD_STATDEP_SHIFT 2
#define OMAP4430_L3INIT_STATDEP_SHIFT 7
#define OMAP4430_L3_1_STATDEP_SHIFT 5
#define OMAP4430_L3_2_STATDEP_SHIFT 6
#define OMAP4430_L4CFG_STATDEP_SHIFT 12
#define OMAP4430_L4PER_STATDEP_SHIFT 13
#define OMAP4430_L4SEC_STATDEP_SHIFT 14
#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
#define OMAP4430_MEMIF_STATDEP_SHIFT 4
#define OMAP4430_MODULEMODE_SHIFT 0
OMAP4: CM & PRM: Update PRCM register bitshifts and masks for ES2 This patch updates the PRM and CM register bitshifts and masks for OMAP4430 ES2.0. Replace as well the BITFIELD macro with the shift operator in order to be consistent with the previous OMAP2 & 3 format. Sort the register list in comments in order to have a consistent register order and avoid futur change during code generation. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
2010-09-28 04:02:55 +08:00
#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
OMAP4: PRCM: Define shift macros as n instead of 1 << n The macros defining the shift bits in registers for various register bit fields are defined as 1 << n. Instead define them as n. They can then be used as val << n. The changes are generated by updating the script which autogenerates the files modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-27 11:13:12 +08:00
#define OMAP4430_TESLA_STATDEP_SHIFT 1
ARM: OMAP4: PM: Adds CM1/2 register field masks This patch adds OMAP4 specific CM1 and CM2 module register field masks. Auto generated using a python script (gen_cm_shifts_and_mask.py) developed by Benoit Cousson, Paul Walmsley and Rajendra Nayak. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
2009-12-09 09:24:54 +08:00
#endif