2019-01-22 02:10:19 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2015-10-21 05:28:57 +08:00
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/*
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* Driver for the Texas Instruments DP83848 PHY
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*
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2016-02-08 01:47:17 +08:00
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* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
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2015-10-21 05:28:57 +08:00
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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2016-02-08 01:47:18 +08:00
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#define TI_DP83848C_PHY_ID 0x20005ca0
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2017-01-17 16:08:16 +08:00
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#define TI_DP83620_PHY_ID 0x20005ce0
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2016-02-08 01:47:18 +08:00
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#define NS_DP83848C_PHY_ID 0x20005c90
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2016-02-08 01:47:20 +08:00
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#define TLK10X_PHY_ID 0x2000a210
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2015-10-21 05:28:57 +08:00
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/* Registers */
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2016-02-08 01:47:21 +08:00
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#define DP83848_MICR 0x11 /* MII Interrupt Control Register */
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#define DP83848_MISR 0x12 /* MII Interrupt Status Register */
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2015-10-21 05:28:57 +08:00
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/* MICR Register Fields */
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#define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
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#define DP83848_MICR_INTEN BIT(1) /* Interrupt Enable */
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/* MISR Register Fields */
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#define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
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#define DP83848_MISR_FHF_INT_EN BIT(1) /* False Carrier Counter */
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#define DP83848_MISR_ANC_INT_EN BIT(2) /* Auto-negotiation complete */
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#define DP83848_MISR_DUP_INT_EN BIT(3) /* Duplex Status */
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#define DP83848_MISR_SPD_INT_EN BIT(4) /* Speed status */
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#define DP83848_MISR_LINK_INT_EN BIT(5) /* Link status */
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#define DP83848_MISR_ED_INT_EN BIT(6) /* Energy detect */
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#define DP83848_MISR_LQM_INT_EN BIT(7) /* Link Quality Monitor */
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2016-02-08 01:47:19 +08:00
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#define DP83848_INT_EN_MASK \
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(DP83848_MISR_ANC_INT_EN | \
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DP83848_MISR_DUP_INT_EN | \
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DP83848_MISR_SPD_INT_EN | \
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DP83848_MISR_LINK_INT_EN)
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2015-10-21 05:28:57 +08:00
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static int dp83848_ack_interrupt(struct phy_device *phydev)
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{
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int err = phy_read(phydev, DP83848_MISR);
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return err < 0 ? err : 0;
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}
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static int dp83848_config_intr(struct phy_device *phydev)
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{
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2016-02-08 01:47:19 +08:00
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int control, ret;
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control = phy_read(phydev, DP83848_MICR);
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if (control < 0)
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return control;
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2015-10-21 05:28:57 +08:00
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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2016-02-08 01:47:19 +08:00
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control |= DP83848_MICR_INT_OE;
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control |= DP83848_MICR_INTEN;
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2015-10-21 05:28:57 +08:00
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2016-02-08 01:47:19 +08:00
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ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK);
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if (ret < 0)
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return ret;
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} else {
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control &= ~DP83848_MICR_INTEN;
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2015-10-21 05:28:57 +08:00
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}
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2016-02-08 01:47:19 +08:00
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return phy_write(phydev, DP83848_MICR, control);
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2015-10-21 05:28:57 +08:00
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}
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net: phy: dp83822: use BMCR_ANENABLE instead of BMSR_ANEGCAPABLE for DP83620
DP83620 register set is compatible with the DP83848, but it also supports
100base-FX. When the hardware is configured such as that fiber mode is
enabled, autonegotiation is not possible.
The chip, however, doesn't expose this information via BMSR_ANEGCAPABLE.
Instead, this bit is always set high, even if the particular hardware
configuration makes it so that auto negotiation is not possible [1]. Under
these circumstances, the phy subsystem keeps trying for autonegotiation to
happen, without success.
Hereby, we inspect BMCR_ANENABLE bit after genphy_config_init, which on
reset is set to 0 when auto negotiation is disabled, and so we use this
value instead of BMSR_ANEGCAPABLE.
[1] https://e2e.ti.com/support/interface/ethernet/f/903/p/697165/2571170
Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-06-08 18:23:39 +08:00
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static int dp83848_config_init(struct phy_device *phydev)
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{
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int err;
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int val;
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err = genphy_config_init(phydev);
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if (err < 0)
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return err;
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/* DP83620 always reports Auto Negotiation Ability on BMSR. Instead,
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* we check initial value of BMCR Auto negotiation enable bit
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*/
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val = phy_read(phydev, MII_BMCR);
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if (!(val & BMCR_ANENABLE))
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phydev->autoneg = AUTONEG_DISABLE;
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return 0;
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}
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2015-10-21 05:28:57 +08:00
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static struct mdio_device_id __maybe_unused dp83848_tbl[] = {
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2016-02-08 01:47:18 +08:00
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{ TI_DP83848C_PHY_ID, 0xfffffff0 },
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{ NS_DP83848C_PHY_ID, 0xfffffff0 },
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2017-01-17 16:08:16 +08:00
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{ TI_DP83620_PHY_ID, 0xfffffff0 },
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2016-02-08 01:47:20 +08:00
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{ TLK10X_PHY_ID, 0xfffffff0 },
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2015-10-21 05:28:57 +08:00
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, dp83848_tbl);
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net: phy: dp83822: use BMCR_ANENABLE instead of BMSR_ANEGCAPABLE for DP83620
DP83620 register set is compatible with the DP83848, but it also supports
100base-FX. When the hardware is configured such as that fiber mode is
enabled, autonegotiation is not possible.
The chip, however, doesn't expose this information via BMSR_ANEGCAPABLE.
Instead, this bit is always set high, even if the particular hardware
configuration makes it so that auto negotiation is not possible [1]. Under
these circumstances, the phy subsystem keeps trying for autonegotiation to
happen, without success.
Hereby, we inspect BMCR_ANENABLE bit after genphy_config_init, which on
reset is set to 0 when auto negotiation is disabled, and so we use this
value instead of BMSR_ANEGCAPABLE.
[1] https://e2e.ti.com/support/interface/ethernet/f/903/p/697165/2571170
Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-06-08 18:23:39 +08:00
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#define DP83848_PHY_DRIVER(_id, _name, _config_init) \
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2016-02-08 01:47:17 +08:00
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{ \
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.phy_id = _id, \
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.phy_id_mask = 0xfffffff0, \
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.name = _name, \
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2019-04-13 02:47:03 +08:00
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/* PHY_BASIC_FEATURES */ \
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2016-02-08 01:47:17 +08:00
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\
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.soft_reset = genphy_soft_reset, \
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net: phy: dp83822: use BMCR_ANENABLE instead of BMSR_ANEGCAPABLE for DP83620
DP83620 register set is compatible with the DP83848, but it also supports
100base-FX. When the hardware is configured such as that fiber mode is
enabled, autonegotiation is not possible.
The chip, however, doesn't expose this information via BMSR_ANEGCAPABLE.
Instead, this bit is always set high, even if the particular hardware
configuration makes it so that auto negotiation is not possible [1]. Under
these circumstances, the phy subsystem keeps trying for autonegotiation to
happen, without success.
Hereby, we inspect BMCR_ANENABLE bit after genphy_config_init, which on
reset is set to 0 when auto negotiation is disabled, and so we use this
value instead of BMSR_ANEGCAPABLE.
[1] https://e2e.ti.com/support/interface/ethernet/f/903/p/697165/2571170
Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-06-08 18:23:39 +08:00
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.config_init = _config_init, \
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2016-02-08 01:47:17 +08:00
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.suspend = genphy_suspend, \
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.resume = genphy_resume, \
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\
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/* IRQ related */ \
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.ack_interrupt = dp83848_ack_interrupt, \
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.config_intr = dp83848_config_intr, \
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}
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2015-10-21 05:28:57 +08:00
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2016-02-08 01:47:17 +08:00
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static struct phy_driver dp83848_driver[] = {
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net: phy: dp83822: use BMCR_ANENABLE instead of BMSR_ANEGCAPABLE for DP83620
DP83620 register set is compatible with the DP83848, but it also supports
100base-FX. When the hardware is configured such as that fiber mode is
enabled, autonegotiation is not possible.
The chip, however, doesn't expose this information via BMSR_ANEGCAPABLE.
Instead, this bit is always set high, even if the particular hardware
configuration makes it so that auto negotiation is not possible [1]. Under
these circumstances, the phy subsystem keeps trying for autonegotiation to
happen, without success.
Hereby, we inspect BMCR_ANENABLE bit after genphy_config_init, which on
reset is set to 0 when auto negotiation is disabled, and so we use this
value instead of BMSR_ANEGCAPABLE.
[1] https://e2e.ti.com/support/interface/ethernet/f/903/p/697165/2571170
Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-06-08 18:23:39 +08:00
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DP83848_PHY_DRIVER(TI_DP83848C_PHY_ID, "TI DP83848C 10/100 Mbps PHY",
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genphy_config_init),
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DP83848_PHY_DRIVER(NS_DP83848C_PHY_ID, "NS DP83848C 10/100 Mbps PHY",
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genphy_config_init),
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DP83848_PHY_DRIVER(TI_DP83620_PHY_ID, "TI DP83620 10/100 Mbps PHY",
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dp83848_config_init),
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DP83848_PHY_DRIVER(TLK10X_PHY_ID, "TI TLK10X 10/100 Mbps PHY",
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genphy_config_init),
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2015-10-21 05:28:57 +08:00
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};
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module_phy_driver(dp83848_driver);
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MODULE_DESCRIPTION("Texas Instruments DP83848 PHY driver");
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2017-01-06 04:44:50 +08:00
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MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
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2019-01-22 02:10:19 +08:00
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MODULE_LICENSE("GPL v2");
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